Add more intrinsic routines
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@ -75,6 +75,23 @@ XTCDECL
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VOID
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VOID
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HlSetInterruptFlag();
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HlSetInterruptFlag();
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XTCDECL
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VOID
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HlStoreGlobalDescriptorTable(OUT PVOID Destination);
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XTCDECL
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VOID
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HlStoreInterruptDescriptorTable(OUT PVOID Destination);
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XTCDECL
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VOID
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HlStoreSegment(IN USHORT Segment,
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OUT PVOID Destination);
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XTCDECL
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VOID
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HlStoreTaskRegister(OUT PVOID Destination);
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XTCDECL
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XTCDECL
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VOID
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VOID
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HlWriteControlRegister(IN USHORT ControlRegister,
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HlWriteControlRegister(IN USHORT ControlRegister,
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@ -49,6 +49,14 @@
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#define CR4_XSAVE 0x00020000
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#define CR4_XSAVE 0x00020000
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#define CR4_RESERVED3 0xFFFC0000
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#define CR4_RESERVED3 0xFFFC0000
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/* Segment defintions */
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#define SEGMENT_CS 0x2E
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#define SEGMENT_DS 0x3E
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#define SEGMENT_ES 0x26
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#define SEGMENT_SS 0x36
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#define SEGMENT_FS 0x64
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#define SEGMENT_GS 0x65
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/* CPUID features enumeration list */
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/* CPUID features enumeration list */
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typedef enum _CPUID_FEATURES
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typedef enum _CPUID_FEATURES
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{
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{
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@ -75,6 +75,23 @@ XTCDECL
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VOID
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VOID
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HlSetInterruptFlag();
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HlSetInterruptFlag();
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XTCDECL
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VOID
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HlStoreGlobalDescriptorTable(OUT PVOID Destination);
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XTCDECL
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VOID
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HlStoreInterruptDescriptorTable(OUT PVOID Destination);
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XTCDECL
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VOID
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HlStoreSegment(IN USHORT Segment,
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OUT PVOID Destination);
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XTCDECL
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VOID
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HlStoreTaskRegister(OUT PVOID Destination);
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XTCDECL
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XTCDECL
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VOID
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VOID
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HlWriteControlRegister(IN USHORT ControlRegister,
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HlWriteControlRegister(IN USHORT ControlRegister,
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@ -49,6 +49,14 @@
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#define CR4_XSAVE 0x00020000
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#define CR4_XSAVE 0x00020000
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#define CR4_RESERVED3 0xFFFC0000
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#define CR4_RESERVED3 0xFFFC0000
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/* Segment defintions */
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#define SEGMENT_CS 0x2E
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#define SEGMENT_DS 0x3E
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#define SEGMENT_ES 0x26
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#define SEGMENT_SS 0x36
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#define SEGMENT_FS 0x64
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#define SEGMENT_GS 0x65
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/* CPUID features enumeration list */
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/* CPUID features enumeration list */
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typedef enum _CPUID_FEATURES
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typedef enum _CPUID_FEATURES
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{
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{
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@ -357,6 +357,116 @@ HlSetInterruptFlag()
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asm volatile("sti");
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asm volatile("sti");
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}
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}
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/**
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* Stores GDT register into the given memory area.
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*
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* @param Destination
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* Supplies a pointer to the memory area where GDT will be stored.
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*
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* @return This routine does not return any value.
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*
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* @since XT 1.0
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*/
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XTCDECL
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VOID
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HlStoreGlobalDescriptorTable(OUT PVOID Destination)
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{
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asm volatile("sgdt %0"
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:
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: "m" (*(PSHORT)Destination)
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: "memory");
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}
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/**
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* Stores IDT register into the given memory area.
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*
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* @param Destination
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* Supplies a pointer to the memory area where IDT will be stored.
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*
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* @return This routine does not return any value.
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*
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* @since XT 1.0
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*/
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XTCDECL
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VOID
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HlStoreInterruptDescriptorTable(OUT PVOID Destination)
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{
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asm volatile("sidt %0"
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:
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: "m" (*(PSHORT)Destination)
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: "memory");
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}
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/**
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* Stores specified segment into the given memory area.
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*
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* @param Segment
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* Supplies a segment identification.
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*
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* @param Destination
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* Supplies a pointer to the memory area where segment data will be stored.
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*
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* @return This routine does not return any value.
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*
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* @since XT 1.0
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*/
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XTCDECL
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VOID
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HlStoreSegment(IN USHORT Segment,
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OUT PVOID Destination)
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{
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switch(Segment)
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{
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case SEGMENT_CS:
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asm volatile("movl %%cs, %0"
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: "=r" (*(PUINT)Destination));
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break;
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case SEGMENT_DS:
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asm volatile("movl %%ds, %0"
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: "=r" (*(PUINT)Destination));
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break;
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case SEGMENT_ES:
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asm volatile("movl %%es, %0"
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: "=r" (*(PUINT)Destination));
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break;
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case SEGMENT_FS:
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asm volatile("movl %%fs, %0"
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: "=r" (*(PUINT)Destination));
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break;
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case SEGMENT_GS:
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asm volatile("movl %%gs, %0"
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: "=r" (*(PUINT)Destination));
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break;
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case SEGMENT_SS:
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asm volatile("movl %%ss, %0"
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: "=r" (*(PUINT)Destination));
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break;
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default:
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Destination = NULL;
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break;
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}
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}
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/**
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* Stores TR into the given memory area.
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*
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* @param Destination
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* Supplies a pointer to the memory area where TR will be stores.
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*
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* @return This routine does not return any value.
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*
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* @since XT 1.0
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*/
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XTCDECL
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VOID
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HlStoreTaskRegister(OUT PVOID Destination)
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{
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asm volatile("str %0"
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:
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: "m" (*(PULONG)Destination)
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: "memory");
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}
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/**
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/**
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* Writes a value to the specified CPU control register.
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* Writes a value to the specified CPU control register.
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*
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*
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@ -348,6 +348,116 @@ HlSetInterruptFlag()
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asm volatile("sti");
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asm volatile("sti");
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}
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}
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/**
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* Stores GDT register into the given memory area.
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*
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* @param Destination
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* Supplies a pointer to the memory area where GDT will be stored.
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*
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* @return This routine does not return any value.
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*
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* @since XT 1.0
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*/
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XTCDECL
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VOID
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HlStoreGlobalDescriptorTable(OUT PVOID Destination)
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{
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asm volatile("sgdt %0"
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:
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: "m" (*(PSHORT)Destination)
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: "memory");
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}
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/**
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* Stores IDT register into the given memory area.
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*
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* @param Destination
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* Supplies a pointer to the memory area where IDT will be stored.
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*
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* @return This routine does not return any value.
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*
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* @since XT 1.0
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*/
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XTCDECL
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VOID
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HlStoreInterruptDescriptorTable(OUT PVOID Destination)
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{
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asm volatile("sidt %0"
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:
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: "m" (*(PSHORT)Destination)
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: "memory");
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}
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/**
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* Stores specified segment into the given memory area.
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*
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* @param Segment
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* Supplies a segment identification.
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*
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* @param Destination
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* Supplies a pointer to the memory area where segment data will be stored.
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*
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* @return This routine does not return any value.
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*
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* @since XT 1.0
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*/
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XTCDECL
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VOID
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HlStoreSegment(IN USHORT Segment,
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OUT PVOID Destination)
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{
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switch(Segment)
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{
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case SEGMENT_CS:
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asm volatile("movl %%cs, %0"
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: "=r" (*(PUINT)Destination));
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break;
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case SEGMENT_DS:
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asm volatile("movl %%ds, %0"
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: "=r" (*(PUINT)Destination));
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break;
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case SEGMENT_ES:
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asm volatile("movl %%es, %0"
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: "=r" (*(PUINT)Destination));
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break;
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case SEGMENT_FS:
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asm volatile("movl %%fs, %0"
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: "=r" (*(PUINT)Destination));
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break;
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case SEGMENT_GS:
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asm volatile("movl %%gs, %0"
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: "=r" (*(PUINT)Destination));
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break;
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case SEGMENT_SS:
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asm volatile("movl %%ss, %0"
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: "=r" (*(PUINT)Destination));
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break;
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default:
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Destination = NULL;
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break;
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}
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}
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/**
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* Stores TR into the given memory area.
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*
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* @param Destination
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* Supplies a pointer to the memory area where TR will be stores.
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*
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* @return This routine does not return any value.
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*
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* @since XT 1.0
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*/
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XTCDECL
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VOID
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HlStoreTaskRegister(OUT PVOID Destination)
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{
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asm volatile("str %0"
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:
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: "m" (*(PULONG)Destination)
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: "memory");
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}
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/**
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/**
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* Writes a value to the specified CPU control register.
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* Writes a value to the specified CPU control register.
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*
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*
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