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04e22c127e
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Initial memory manager initialization code
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2024-04-07 10:26:12 +02:00 |
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d7b103f85d
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Add forward references for PTE related structures
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2024-04-03 16:03:17 +02:00 |
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c6f3422c49
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Update PTE related structures
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2024-04-03 16:00:26 +02:00 |
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4b2d8ded72
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No parameters are expected, explicitly
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2024-02-20 16:55:12 +01:00 |
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badb16e37d
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Add lock queue to processor control block
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2024-02-05 19:21:19 +01:00 |
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af687603d0
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Add kernel stack guard pages definition
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2024-02-04 19:21:42 +01:00 |
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5acf8b4abd
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Add page size enumeration list
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2024-01-18 14:22:51 +01:00 |
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e64cf4d0aa
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Add CR4_LA57 definition
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2024-01-14 21:06:02 +01:00 |
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0d1fcde3a5
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Add missing StallScaleFactor to KPROCESSOR_BLOCK
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2023-11-28 23:08:35 +01:00 |
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f6c621c2a6
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Basic processor initialization code
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2023-11-28 22:31:39 +01:00 |
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e5adc31af7
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Implement basic APIC support, including X2APIC
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2023-11-27 22:38:15 +01:00 |
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4ca4e298f0
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Add more PIC/APIC related definitions
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2023-11-26 23:35:14 +01:00 |
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4701351bd7
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Add missing SYNC_LEVEL definition
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2023-11-25 22:14:45 +01:00 |
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14a966043e
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Add missing Interrupt request level definitions
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2023-11-25 18:50:59 +01:00 |
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0e6bf984a5
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Add APIC vector definitions
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2023-11-25 18:33:01 +01:00 |
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55cc62f5a0
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Rename KIRQL to KRUNLEVEL type
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2023-11-25 00:32:55 +01:00 |
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a3c28cee73
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Initial XTLDR APIC support, finds and maps base APIC address for kernel
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2023-11-20 15:18:22 +01:00 |
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83c0accc5f
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Update EFLAGS masks
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2023-11-09 16:12:24 +01:00 |
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362eefc2b3
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Fixes in AMD64 version of KepInitializeThreadContext() to get rid of PageFault exception
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2023-11-07 15:34:49 +01:00 |
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91ce0f9947
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Compensate missing return address, which is a 4-byte on i686 and an 8-byte on amd64
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2023-11-05 20:07:13 +01:00 |
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f05a262da2
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Cleanup XTDK and XTOSKRNL headers
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2023-10-29 09:58:47 +01:00 |
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798e4c1d22
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Cleanup MM subsystem headers
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2023-10-29 00:52:05 +02:00 |
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600c86949b
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Cleanup RTL subsystem headers
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2023-10-29 00:14:01 +02:00 |
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d920cae481
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Fix build by defining more routines used by XTLDR
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2023-10-28 23:41:52 +02:00 |
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ad15c55a39
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Cleanup AR subsystem headers
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2023-10-28 23:35:34 +02:00 |
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358b20f1a1
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Reorder routines
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2023-04-04 22:35:06 +02:00 |
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10ccf67e8e
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Add missing forward declarations
ci/woodpecker/push/build Pipeline was successful
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2023-03-14 22:50:32 +01:00 |
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5677719038
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Initialize thread context for AMD64
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2023-03-14 17:37:20 +01:00 |
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fd8eec1d86
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Add EFLAGS and THREAD_ENVIRONMENT_BLOCK for amd64
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2023-03-05 19:03:34 +01:00 |
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c5a9253ea8
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Implement ArLoadLocalDescriptorTable() routine
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2023-03-02 23:04:36 +01:00 |
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870a6680b0
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Add thread information block
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2023-03-01 00:14:06 +01:00 |
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ef23acc3bc
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Add Deferred Procedure Call (DPC) and processor power state related structures
ci/woodpecker/push/build Pipeline was successful
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2023-02-27 19:58:47 +01:00 |
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e41de62dab
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Implement ArYieldProcessor() routine
ci/woodpecker/push/build Pipeline was successful
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2023-02-27 17:28:20 +01:00 |
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c8428241dd
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Add missing headers containing forward references of MM routines
ci/woodpecker/push/build Pipeline was successful
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2023-02-20 22:22:32 +01:00 |
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b1c2b209e3
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Implement RtlGetStackLimits() routine
ci/woodpecker/push/build Pipeline was successful
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2023-02-15 20:12:58 +01:00 |
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2e790bd9b2
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Add pages related macros and definitions
ci/woodpecker/push/build Pipeline was successful
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2023-02-13 23:01:20 +01:00 |
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e94cb2d3a7
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Processor identification structures
ci/woodpecker/push/build Pipeline was successful
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2023-02-10 17:14:12 +01:00 |
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e645cf664c
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Set process and thread information in processor control block
ci/woodpecker/push/build Pipeline was successful
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2023-02-09 17:30:24 +01:00 |
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9132c47cd9
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Initial process and thread related structures
ci/woodpecker/push/build Pipeline failed
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2023-02-08 23:40:58 +01:00 |
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c6cadbd655
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Initialize MXCSR register
ci/woodpecker/push/build Pipeline was successful
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2023-02-05 00:30:12 +01:00 |
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5eaf7d63a3
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Initialize Page Attribute Table
ci/woodpecker/push/build Pipeline was successful
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2023-02-05 00:14:34 +01:00 |
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55cdae7c83
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Initialize AMD64 processor registers
ci/woodpecker/push/build Pipeline was successful
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2023-02-04 23:40:03 +01:00 |
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269214ed34
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Another improvements to GDT
ci/woodpecker/push/build Pipeline was successful
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2023-02-03 18:00:37 +01:00 |
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19f34d4b17
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Cleanup the code
ci/woodpecker/push/build Pipeline was successful
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2023-02-02 19:42:57 +01:00 |
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715f875c4f
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Set alignment and packing properly
ci/woodpecker/push/build Pipeline was successful
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2023-02-02 17:01:18 +01:00 |
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73fc7607cd
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There is no need to specify alignment of the structure in the forward reference
ci/woodpecker/push/build Pipeline was successful
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2023-02-02 15:37:57 +01:00 |
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21fbe6febe
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Add IDT related definitions
ci/woodpecker/push/build Pipeline was successful
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2023-02-01 20:14:10 +01:00 |
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a761d3125a
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Architecture specific initialization prior to processor structures initialization
ci/woodpecker/push/build Pipeline was successful
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2023-01-30 20:34:05 +01:00 |
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6f068513cd
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Initial processor block initialization
ci/woodpecker/push/build Pipeline was successful
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2023-01-30 19:07:05 +01:00 |
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ebe6792f2b
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Add MSR (Model Specific Registers) values
ci/woodpecker/push/build Pipeline was successful
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2023-01-30 17:59:00 +01:00 |
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