1045 Commits

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Author	SHA1	Message	Date
belliash	e4fa9bdead	CurrentPrcb is needed here	2023-02-10 17:29:18 +01:00
belliash	d72002187d	Partially implement ArpIdentifyProcessor()	2023-02-10 17:23:47 +01:00
belliash	e94cb2d3a7	Processor identification structures	2023-02-10 17:14:12 +01:00
belliash	e645cf664c	Set process and thread information in processor control block	2023-02-09 17:30:24 +01:00
belliash	47f399e987	Set current process and thread in processor control block	2023-02-09 00:02:45 +01:00
belliash	c4a52938d2	Implement KeGetCurrentThread() routine	2023-02-08 23:58:24 +01:00
belliash	e3a900088c	Initial process and thread related structures	2023-02-08 23:56:29 +01:00
belliash	9132c47cd9	Initial process and thread related structures	2023-02-08 23:40:58 +01:00
belliash	929d3dfae7	Implement KeGetCurrentProcessorBlock() and KeGetCurrentProcessorControlBlock() routines for both amd64 and i686	2023-02-08 16:39:05 +01:00
belliash	d8c68ed003	Add endian conversion routines	2023-02-08 16:33:57 +01:00
belliash	a32e18b237	Implement ArReadFSDualWord() routine	2023-02-07 23:19:22 +01:00
belliash	75c519a70c	Use more generic name for this macro use pointer used behind it will point to kernel debugger after it gets initialized	2023-02-07 19:37:44 +01:00
belliash	67768ae7a3	Mark ArpIdentifyProcessor() as unimplemented	2023-02-06 16:15:24 +01:00
belliash	f8d2ccc0d0	Add more debugging macros	2023-02-06 16:10:32 +01:00
belliash	9c7d961c5a	Architecture specific initialization after processor init is done	2023-02-06 15:53:11 +01:00
belliash	385f0e6de0	Not all AMD64 CPUs support large pages and global pages, unfortunately	2023-02-05 22:14:47 +01:00
belliash	76f22fbdc4	Initialize segments and processor registers for i686 architecture	2023-02-05 15:45:22 +01:00
belliash	2ba42c5270	Update ideas	2023-02-05 13:23:11 +01:00
belliash	911903d0eb	Add missing routine description	2023-02-05 10:08:49 +01:00
belliash	707c92e08a	Boot loader no longer needs to do anything related to the stack	2023-02-05 10:03:21 +01:00
belliash	d6aac59199	Let kernel initialize stack on it's own without relying on boot loader	2023-02-05 09:55:59 +01:00
belliash	0b743a5f26	Add stub routine for identifying processor	2023-02-05 00:42:30 +01:00
belliash	c6cadbd655	Initialize MXCSR register	2023-02-05 00:30:12 +01:00
belliash	5eaf7d63a3	Initialize Page Attribute Table	2023-02-05 00:14:34 +01:00
belliash	55cdae7c83	Initialize AMD64 processor registers	2023-02-04 23:40:03 +01:00
belliash	f181215341	Initialize segment registers	2023-02-04 00:17:07 +01:00
belliash	f37722b6e6	Distinguish ProcessorBlock and ProcessorControlBlock	2023-02-03 19:28:03 +01:00
belliash	b90f37dad4	Fill in Interrupt Descriptor Table (IDT)	2023-02-03 18:40:10 +01:00
belliash	648ad1636a	Cleanup TSS initialization code	2023-02-03 18:27:50 +01:00
belliash	269214ed34	Another improvements to GDT	2023-02-03 18:00:37 +01:00
belliash	a49d0804ce	Add trap handlers for both i686 and amd64	2023-02-02 23:31:32 +01:00
belliash	19f34d4b17	Cleanup the code	2023-02-02 19:42:57 +01:00
belliash	715f875c4f	Set alignment and packing properly	2023-02-02 17:01:18 +01:00
belliash	2e2b01742a	Definitions for setting structures alignment and packing	2023-02-02 15:47:21 +01:00
belliash	73fc7607cd	There is no need to specify alignment of the structure in the forward reference	2023-02-02 15:37:57 +01:00
belliash	404f2f85c6	Cleanup the Interrupt Stack Table	2023-02-01 23:47:57 +01:00
belliash	7fc1f04cd0	TSS entry is already put into GDT table, just initialize it	2023-02-01 23:37:12 +01:00
belliash	cbd21ced39	Use a size of the structure, not a pointer	2023-02-01 22:38:36 +01:00
belliash	dc1a94b982	This is 'Processor Block'	2023-02-01 22:02:07 +01:00
belliash	3522539d4b	Initialize Interrupt Descriptor Table (IDT)	2023-02-01 21:56:17 +01:00
belliash	1ef205d47b	Initialize DoubleFault and NonMaskableInterrupt TSS entries	2023-02-01 20:36:40 +01:00
belliash	e2813bcdaa	Fix entries in Global Descriptor Table (GDT)	2023-02-01 20:24:55 +01:00
belliash	21fbe6febe	Add IDT related definitions	2023-02-01 20:14:10 +01:00
belliash	5bbda188c6	IDT access levels and gate types	2023-02-01 00:51:13 +01:00
belliash	9a1e9b1084	Define TSS offsets	2023-01-30 23:43:10 +01:00
belliash	892c9eca86	Do not hardcode I/O map base	2023-01-30 22:38:41 +01:00
belliash	a761d3125a	Architecture specific initialization prior to processor structures initialization	2023-01-30 20:34:05 +01:00
belliash	6f068513cd	Initial processor block initialization	2023-01-30 19:07:05 +01:00
belliash	ebe6792f2b	Add MSR (Model Specific Registers) values	2023-01-30 17:59:00 +01:00
belliash	d3376ce33b	This is no longer an idea	2023-01-29 22:33:12 +01:00