Commit Graph
66 Commits
Author SHA1 Message Date
belliash 3131aac7a9 Move serial ports I/O address to architecture specific header
ci/woodpecker/push/build Pipeline was successful
2023-01-05 15:58:36 +01:00
belliash b7e5f1b5c1 Use CR constants instead of hardcoded values
ci/woodpecker/push/build Pipeline was successful
2023-01-04 16:33:28 +01:00
belliash fcfa575bff Implement HlReadTimeStampCounter() routine
ci/woodpecker/push/build Pipeline was successful
2022-12-27 23:28:27 +01:00
belliash f46615f92c Implement HlInvalidateTlbEntry(), HlReadModelSpecificRegister() and HlWriteModelSpecificRegister() routines
ci/woodpecker/push/build Pipeline was successful
2022-12-27 23:19:33 +01:00
belliash 602d89ef27 Fixes in HlIoPortInShort() and HlIoPortInLong() routines
ci/woodpecker/push/build Pipeline was successful
2022-12-27 22:43:19 +01:00
belliash 9828b23400 Implement HlIoPortInShort(), HlIoPortInLong(), HlIoPortOutShort() and HlIoPortOutLong() routines
ci/woodpecker/push/build Pipeline failed
2022-12-27 22:26:45 +01:00
belliash 5b75d005a7 Implement HlClearInterruptFlag() and HlSetInterruptFlag() intrinsic routines
ci/woodpecker/push/build Pipeline was successful
2022-12-27 18:54:01 +01:00
belliash 93ad0b4ea0 Set valid calling convention for HAL routines
ci/woodpecker/push/build Pipeline was successful
2022-12-23 14:41:11 +01:00
belliash 3ab1695968 Common routines for reading from and writing to CPU control registers
ci/woodpecker/push/build Pipeline was successful
2022-12-23 14:30:52 +01:00
belliash 6c4496f839 KERNEL_STACK_SIZE should be expressed in bytes as the name suggests, calculate number of pages where needed
ci/woodpecker/push/build Pipeline was successful
2022-12-21 22:24:16 +01:00
belliash 7c38efc802 Update boot sequence and check PE/COFF image machine type compatibility
ci/woodpecker/push/build Pipeline was successful
2022-12-20 19:11:15 +01:00
belliash 9f4db475bb Implement HlHalt() intrinsic routine and add basic definitions for kernel services
ci/woodpecker/push/build Pipeline was successful
2022-12-11 23:09:35 +01:00
belliash 324a88cc01 Implement HlCpuId() routine and corresponding structures for issueing CPUID instruction
ci/woodpecker/push/build Pipeline was successful
2022-12-11 17:40:56 +01:00
belliash 93fa2aed67 Implement BlMapVirtualMemory() routine for recursive mapping
ci/woodpecker/push/build Pipeline was successful
2022-12-06 23:32:31 +01:00
belliash b89121fded Implement routines for accessing and manipulating CPU control registers
ci/woodpecker/push/build Pipeline was successful
2022-12-02 23:03:42 +01:00
belliash 35f2c67138 Basic XT structures
ci/woodpecker/push/build Pipeline was successful
2022-07-29 16:31:59 +02:00