Remove unused header

xtoskrnl/CMakeLists.txt

@@ -20,6 +20,7 @@ list(APPEND XTOSKRNL_SOURCE
     ${XTOSKRNL_SOURCE_DIR}/hl/${ARCH}/cpu.cc
     ${XTOSKRNL_SOURCE_DIR}/hl/${ARCH}/pic.cc
     ${XTOSKRNL_SOURCE_DIR}/hl/${ARCH}/ioport.cc
+    ${XTOSKRNL_SOURCE_DIR}/hl/${ARCH}/irq.cc
     ${XTOSKRNL_SOURCE_DIR}/hl/${ARCH}/runlevel.cc
     ${XTOSKRNL_SOURCE_DIR}/hl/acpi.cc
     ${XTOSKRNL_SOURCE_DIR}/hl/cport.cc
@@ -31,7 +32,6 @@ list(APPEND XTOSKRNL_SOURCE
     ${XTOSKRNL_SOURCE_DIR}/kd/data.cc
     ${XTOSKRNL_SOURCE_DIR}/kd/dbgio.cc
     ${XTOSKRNL_SOURCE_DIR}/kd/exports.cc
-    ${XTOSKRNL_SOURCE_DIR}/ke/${ARCH}/irq.cc
     ${XTOSKRNL_SOURCE_DIR}/ke/${ARCH}/krnlinit.cc
     ${XTOSKRNL_SOURCE_DIR}/ke/${ARCH}/kthread.cc
     ${XTOSKRNL_SOURCE_DIR}/ke/${ARCH}/proc.cc

xtoskrnl/ar/amd64/archsup.S

@@ -13,20 +13,29 @@
 
 
 /**
- * Creates a trap handler for the specified vector.
+ * Creates a trap or interrupt handler for the specified vector.
  *
  * @param Vector
- *        Supplies a trap vector number.
+ *        Supplies a trap/interrupt vector number.
+ *
+ * @param Type
+ *        Specifies whether the handler is designed to handle an interrupt or a trap.
  *
  * @return This macro does not return any value.
  *
  * @since XT 1.0
  */
-.macro ArCreateTrapHandler Vector
+.macro ArCreateTrapHandler Vector Type
-.global ArTrap\Vector
+.global Ar\Type\Vector
-ArTrap\Vector:
+Ar\Type\Vector:
-    /* Push fake error code for non-error vectors */
+    /* Check handler type */
-    .if \Vector != 8 && \Vector != 10 && \Vector != 11 && \Vector != 12 && \Vector != 13 && \Vector != 14 && \Vector != 17 && \Vector != 30
+    .ifc \Type,Trap
+        /* Push fake error code for non-error vector traps */
+        .if \Vector != 8 && \Vector != 10 && \Vector != 11 && \Vector != 12 && \Vector != 13 && \Vector != 14 && \Vector != 17 && \Vector != 30
+            push $0
+        .endif
+    .else
+        /* Push fake error code for interrupts */
         push $0
     .endif
 
@@ -104,24 +113,39 @@ ArTrap\Vector:
     /* Test previous mode and swap GS if needed */
     movl $0, TrapPreviousMode(%rbp)
     mov %cs, %ax
-    and $1, %al
+    and $3, %al
     mov %al, TrapPreviousMode(%rbp)
-    jz KernelMode$\Vector
+    jz KernelMode\Type\Vector
     swapgs
+    jmp UserMode\Type\Vector
 
-KernelMode$\Vector:
+KernelMode\Type\Vector:
-    /* Push Frame Pointer, clear direction flag and pass to trap dispatcher */
+    /* Save kernel stack pointer (SS:RSP) */
+    movl %ss, %eax
+    mov %eax, TrapSegSs(%rbp)
+    lea TRAP_FRAME_SIZE(%rbp), %rax
+    mov %rax, TrapRsp(%rbp)
+
+UserMode\Type\Vector:
+    /* Push Frame Pointer and clear direction flag */
     mov %rsp, %rcx
     cld
-    call ArDispatchTrap
+
+    .ifc \Type,Trap
+        /* Pass to the trap dispatcher */
+        call ArDispatchTrap
+    .else
+        /* Pass to the interrupt dispatcher */
+        call ArDispatchTrap
+    .endif
 
     /* Test previous mode and swapgs if needed */
     testb $1, TrapPreviousMode(%rbp)
-    jz KernelModeReturn$\Vector
+    jz KernelModeReturn\Type\Vector
     cli
     swapgs
 
-KernelModeReturn$\Vector:
+KernelModeReturn\Type\Vector:
     /* Restore XMM registers */
     movdqa TrapXmm0(%rbp), %xmm0
     movdqa TrapXmm1(%rbp), %xmm1
@@ -173,9 +197,28 @@ KernelModeReturn$\Vector:
     iretq
 .endm
 
-/* Populate common trap handlers */
+/* Populate common interrupt and trap handlers */
 .irp i,0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F
     .irp j,0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F
-        ArCreateTrapHandler 0x\i\j
+        ArCreateTrapHandler 0x\i\j Interrupt
+        ArCreateTrapHandler 0x\i\j Trap
+    .endr
+.endr
+
+/* Define array of pointers to the interrupt handlers */
+.global ArInterruptEntry
+ArInterruptEntry:
+.irp i,0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F
+    .irp j,0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F
+        .quad ArInterrupt0x\i\j
+    .endr
+.endr
+
+/* Define array of pointers to the trap handlers */
+.global ArTrapEntry
+ArTrapEntry:
+.irp i,0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F
+    .irp j,0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F
+        .quad ArTrap0x\i\j
     .endr
 .endr

xtoskrnl/ar/amd64/procsup.cc

@@ -249,34 +249,35 @@ AR::ProcSup::InitializeIdt(IN PKPROCESSOR_BLOCK ProcessorBlock)
     for(Vector = 0; Vector < IDT_ENTRIES; Vector++)
     {
         /* Set the IDT to handle unexpected interrupts */
-        SetIdtGate(ProcessorBlock->IdtBase, Vector, (PVOID)ArTrap0xFF, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0, AMD64_INTERRUPT_GATE);
+        SetIdtGate(ProcessorBlock->IdtBase, Vector, (PVOID)ArInterruptEntry[Vector], KGDT_R0_CODE,
+                   KIDT_IST_RESERVED, KIDT_ACCESS_RING0, AMD64_INTERRUPT_GATE);
     }
 
     /* Setup IDT handlers for known interrupts and traps */
-    SetIdtGate(ProcessorBlock->IdtBase, 0x00, (PVOID)ArTrap0x00, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0, AMD64_TRAP_GATE);
+    SetIdtGate(ProcessorBlock->IdtBase, 0x00, (PVOID)ArTrapEntry[0x00], KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0, AMD64_TRAP_GATE);
-    SetIdtGate(ProcessorBlock->IdtBase, 0x01, (PVOID)ArTrap0x01, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0, AMD64_TRAP_GATE);
+    SetIdtGate(ProcessorBlock->IdtBase, 0x01, (PVOID)ArTrapEntry[0x01], KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0, AMD64_TRAP_GATE);
-    SetIdtGate(ProcessorBlock->IdtBase, 0x02, (PVOID)ArTrap0x02, KGDT_R0_CODE, KIDT_IST_PANIC, KIDT_ACCESS_RING0, AMD64_INTERRUPT_GATE);
+    SetIdtGate(ProcessorBlock->IdtBase, 0x02, (PVOID)ArTrapEntry[0x02], KGDT_R0_CODE, KIDT_IST_PANIC, KIDT_ACCESS_RING0, AMD64_INTERRUPT_GATE);
-    SetIdtGate(ProcessorBlock->IdtBase, 0x03, (PVOID)ArTrap0x03, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING3, AMD64_TRAP_GATE);
+    SetIdtGate(ProcessorBlock->IdtBase, 0x03, (PVOID)ArTrapEntry[0x03], KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING3, AMD64_TRAP_GATE);
-    SetIdtGate(ProcessorBlock->IdtBase, 0x04, (PVOID)ArTrap0x04, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING3, AMD64_TRAP_GATE);
+    SetIdtGate(ProcessorBlock->IdtBase, 0x04, (PVOID)ArTrapEntry[0x04], KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING3, AMD64_TRAP_GATE);
-    SetIdtGate(ProcessorBlock->IdtBase, 0x05, (PVOID)ArTrap0x05, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0, AMD64_TRAP_GATE);
+    SetIdtGate(ProcessorBlock->IdtBase, 0x05, (PVOID)ArTrapEntry[0x05], KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0, AMD64_TRAP_GATE);
-    SetIdtGate(ProcessorBlock->IdtBase, 0x06, (PVOID)ArTrap0x06, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0, AMD64_TRAP_GATE);
+    SetIdtGate(ProcessorBlock->IdtBase, 0x06, (PVOID)ArTrapEntry[0x06], KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0, AMD64_TRAP_GATE);
-    SetIdtGate(ProcessorBlock->IdtBase, 0x07, (PVOID)ArTrap0x07, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0, AMD64_TRAP_GATE);
+    SetIdtGate(ProcessorBlock->IdtBase, 0x07, (PVOID)ArTrapEntry[0x07], KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0, AMD64_TRAP_GATE);
-    SetIdtGate(ProcessorBlock->IdtBase, 0x08, (PVOID)ArTrap0x08, KGDT_R0_CODE, KIDT_IST_PANIC, KIDT_ACCESS_RING0, AMD64_TRAP_GATE);
+    SetIdtGate(ProcessorBlock->IdtBase, 0x08, (PVOID)ArTrapEntry[0x08], KGDT_R0_CODE, KIDT_IST_PANIC, KIDT_ACCESS_RING0, AMD64_TRAP_GATE);
-    SetIdtGate(ProcessorBlock->IdtBase, 0x09, (PVOID)ArTrap0x09, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0, AMD64_TRAP_GATE);
+    SetIdtGate(ProcessorBlock->IdtBase, 0x09, (PVOID)ArTrapEntry[0x09], KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0, AMD64_TRAP_GATE);
-    SetIdtGate(ProcessorBlock->IdtBase, 0x0A, (PVOID)ArTrap0x0A, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0, AMD64_TRAP_GATE);
+    SetIdtGate(ProcessorBlock->IdtBase, 0x0A, (PVOID)ArTrapEntry[0x0A], KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0, AMD64_TRAP_GATE);
-    SetIdtGate(ProcessorBlock->IdtBase, 0x0B, (PVOID)ArTrap0x0B, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0, AMD64_TRAP_GATE);
+    SetIdtGate(ProcessorBlock->IdtBase, 0x0B, (PVOID)ArTrapEntry[0x0B], KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0, AMD64_TRAP_GATE);
-    SetIdtGate(ProcessorBlock->IdtBase, 0x0C, (PVOID)ArTrap0x0C, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0, AMD64_TRAP_GATE);
+    SetIdtGate(ProcessorBlock->IdtBase, 0x0C, (PVOID)ArTrapEntry[0x0C], KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0, AMD64_TRAP_GATE);
-    SetIdtGate(ProcessorBlock->IdtBase, 0x0D, (PVOID)ArTrap0x0D, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0, AMD64_TRAP_GATE);
+    SetIdtGate(ProcessorBlock->IdtBase, 0x0D, (PVOID)ArTrapEntry[0x0D], KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0, AMD64_TRAP_GATE);
-    SetIdtGate(ProcessorBlock->IdtBase, 0x0E, (PVOID)ArTrap0x0E, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0, AMD64_TRAP_GATE);
+    SetIdtGate(ProcessorBlock->IdtBase, 0x0E, (PVOID)ArTrapEntry[0x0E], KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0, AMD64_TRAP_GATE);
-    SetIdtGate(ProcessorBlock->IdtBase, 0x10, (PVOID)ArTrap0x10, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0, AMD64_TRAP_GATE);
+    SetIdtGate(ProcessorBlock->IdtBase, 0x10, (PVOID)ArTrapEntry[0x10], KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0, AMD64_TRAP_GATE);
-    SetIdtGate(ProcessorBlock->IdtBase, 0x11, (PVOID)ArTrap0x11, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0, AMD64_TRAP_GATE);
+    SetIdtGate(ProcessorBlock->IdtBase, 0x11, (PVOID)ArTrapEntry[0x11], KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0, AMD64_TRAP_GATE);
-    SetIdtGate(ProcessorBlock->IdtBase, 0x12, (PVOID)ArTrap0x12, KGDT_R0_CODE, KIDT_IST_MCA, KIDT_ACCESS_RING0, AMD64_TRAP_GATE);
+    SetIdtGate(ProcessorBlock->IdtBase, 0x12, (PVOID)ArTrapEntry[0x12], KGDT_R0_CODE, KIDT_IST_MCA, KIDT_ACCESS_RING0, AMD64_TRAP_GATE);
-    SetIdtGate(ProcessorBlock->IdtBase, 0x13, (PVOID)ArTrap0x13, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0, AMD64_TRAP_GATE);
+    SetIdtGate(ProcessorBlock->IdtBase, 0x13, (PVOID)ArTrapEntry[0x13], KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0, AMD64_TRAP_GATE);
-    SetIdtGate(ProcessorBlock->IdtBase, 0x1F, (PVOID)ArTrap0x1F, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0, AMD64_INTERRUPT_GATE);
+    SetIdtGate(ProcessorBlock->IdtBase, 0x1F, (PVOID)ArTrapEntry[0x1F], KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0, AMD64_INTERRUPT_GATE);
-    SetIdtGate(ProcessorBlock->IdtBase, 0x2C, (PVOID)ArTrap0x2C, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING3, AMD64_TRAP_GATE);
+    SetIdtGate(ProcessorBlock->IdtBase, 0x2C, (PVOID)ArTrapEntry[0x2C], KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING3, AMD64_TRAP_GATE);
-    SetIdtGate(ProcessorBlock->IdtBase, 0x2D, (PVOID)ArTrap0x2D, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING3, AMD64_TRAP_GATE);
+    SetIdtGate(ProcessorBlock->IdtBase, 0x2D, (PVOID)ArTrapEntry[0x2D], KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING3, AMD64_TRAP_GATE);
-    SetIdtGate(ProcessorBlock->IdtBase, 0x2F, (PVOID)ArTrap0x2F, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0, AMD64_INTERRUPT_GATE);
+    SetIdtGate(ProcessorBlock->IdtBase, 0x2F, (PVOID)ArTrapEntry[0x2F], KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0, AMD64_INTERRUPT_GATE);
-    SetIdtGate(ProcessorBlock->IdtBase, 0xE1, (PVOID)ArTrap0xE1, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0, AMD64_INTERRUPT_GATE);
+    SetIdtGate(ProcessorBlock->IdtBase, 0xE1, (PVOID)ArTrapEntry[0xE1], KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0, AMD64_INTERRUPT_GATE);
 }
 
 /**

xtoskrnl/ar/i686/archsup.S

@@ -13,20 +13,29 @@
 
 
 /**
- * This macro creates a trap handler for the specified vector.
+ * Creates a trap or interrupt handler for the specified vector.
  *
  * @param Vector
- *        Supplies a trap vector number.
+ *        Supplies a trap/interrupt vector number.
+ *
+ * @param Type
+ *        Specifies whether the handler is designed to handle an interrupt or a trap.
  *
  * @return This macro does not return any value.
  *
  * @since XT 1.0
  */
-.macro ArCreateTrapHandler Vector
+.macro ArCreateTrapHandler Vector Type
-.global _ArTrap\Vector
+.global _Ar\Type\Vector
-_ArTrap\Vector:
+_Ar\Type\Vector:
-    /* Push fake error code for non-error vectors */
+    /* Check handler type */
-    .if \Vector != 8 && \Vector != 10 && \Vector != 11 && \Vector != 12 && \Vector != 13 && \Vector != 14 && \Vector != 17 && \Vector != 30
+    .ifc \Type,Trap
+        /* Push fake error code for non-error vector traps */
+        .if \Vector != 8 && \Vector != 10 && \Vector != 11 && \Vector != 12 && \Vector != 13 && \Vector != 14 && \Vector != 17 && \Vector != 30
+            push $0
+        .endif
+    .else
+        /* Push fake error code for interrupts */
         push $0
     .endif
 
@@ -75,31 +84,47 @@ _ArTrap\Vector:
     /* Test previous mode and swap GS if needed */
     movl $0, TrapPreviousMode(%ebp)
     mov %cs, %ax
-    and $1, %al
+    and $3, %al
     mov %al, TrapPreviousMode(%ebp)
-    jz KernelMode$\Vector
+    jz KernelMode\Type\Vector
     swapgs
+    jmp UserMode\Type\Vector
 
-KernelMode$\Vector:
+KernelMode\Type\Vector:
-    /* Push Frame Pointer, clear direction flag and pass to trap dispatcher */
+    /* Save kernel stack pointer (SS:ESP) */
+    movl %ss, %eax
+    mov %eax, TrapSegSs(%ebp)
+    lea TrapEsp(%ebp), %eax
+    mov %eax, TrapEsp(%ebp)
+
+UserMode\Type\Vector:
+    /* Push Frame Pointer and clear direction flag */
     push %esp
     cld
-    call _ArDispatchTrap
+
+    .ifc \Type,Trap
+        /* Pass to the trap dispatcher */
+        call _ArDispatchTrap
+    .else
+        /* Pass to the interrupt dispatcher */
+        call _ArDispatchTrap
+    .endif
 
     /* Clean up the stack */
     add $4, %esp
 
     /* Test previous mode and swapgs if needed */
     testb $1, TrapPreviousMode(%ebp)
-    jz KernelModeReturn$\Vector
+    jz KernelModeReturn\Type\Vector
     cli
     swapgs
 
-KernelModeReturn$\Vector:
+KernelModeReturn\Type\Vector:
     /* Restore segment selectors */
     mov TrapSegDs(%ebp), %ds
     mov TrapSegEs(%ebp), %es
     mov TrapSegFs(%ebp), %fs
+    mov TrapSegGs(%ebp), %gs
 
     /* Free stack space */
     add $(TRAP_FRAME_SIZE - TRAP_REGISTERS_SIZE), %esp
@@ -118,9 +143,28 @@ KernelModeReturn$\Vector:
     iretl
 .endm
 
-/* Populate common trap handlers */
+/* Populate common interrupt and trap handlers */
 .irp i,0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F
     .irp j,0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F
-        ArCreateTrapHandler 0x\i\j
+        ArCreateTrapHandler 0x\i\j Interrupt
+        ArCreateTrapHandler 0x\i\j Trap
+    .endr
+.endr
+
+/* Define array of pointers to the interrupt handlers */
+.global _ArInterruptEntry
+_ArInterruptEntry:
+.irp i,0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F
+    .irp j,0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F
+        .long _ArInterrupt0x\i\j
+    .endr
+.endr
+
+/* Define array of pointers to the trap handlers */
+.global _ArTrapEntry
+_ArTrapEntry:
+.irp i,0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F
+    .irp j,0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F
+        .long _ArTrap0x\i\j
     .endr
 .endr

xtoskrnl/ar/i686/procsup.cc

@@ -242,34 +242,35 @@ AR::ProcSup::InitializeIdt(IN PKPROCESSOR_BLOCK ProcessorBlock)
     for(Vector = 0; Vector < IDT_ENTRIES; Vector++)
     {
         /* Set the IDT to handle unexpected interrupts */
-        SetIdtGate(ProcessorBlock->IdtBase, Vector, (PVOID)ArTrap0xFF, KGDT_R0_CODE, 0, KIDT_ACCESS_RING0, I686_INTERRUPT_GATE);
+        SetIdtGate(ProcessorBlock->IdtBase, Vector, (PVOID)ArInterruptEntry[Vector],
+                   KGDT_R0_CODE, 0, KIDT_ACCESS_RING0, I686_INTERRUPT_GATE);
     }
 
     /* Setup IDT handlers for known interrupts and traps */
-    SetIdtGate(ProcessorBlock->IdtBase, 0x00, (PVOID)ArTrap0x00, KGDT_R0_CODE, 0, KIDT_ACCESS_RING0, I686_TRAP_GATE);
+    SetIdtGate(ProcessorBlock->IdtBase, 0x00, (PVOID)ArTrapEntry[0x00], KGDT_R0_CODE, 0, KIDT_ACCESS_RING0, I686_TRAP_GATE);
-    SetIdtGate(ProcessorBlock->IdtBase, 0x01, (PVOID)ArTrap0x01, KGDT_R0_CODE, 0, KIDT_ACCESS_RING0, I686_TRAP_GATE);
+    SetIdtGate(ProcessorBlock->IdtBase, 0x01, (PVOID)ArTrapEntry[0x01], KGDT_R0_CODE, 0, KIDT_ACCESS_RING0, I686_TRAP_GATE);
-    SetIdtGate(ProcessorBlock->IdtBase, 0x02, (PVOID)ArTrap0x02, KGDT_R0_CODE, 0, KIDT_ACCESS_RING0, I686_INTERRUPT_GATE);
+    SetIdtGate(ProcessorBlock->IdtBase, 0x02, (PVOID)ArTrapEntry[0x02], KGDT_R0_CODE, 0, KIDT_ACCESS_RING0, I686_INTERRUPT_GATE);
-    SetIdtGate(ProcessorBlock->IdtBase, 0x03, (PVOID)ArTrap0x03, KGDT_R0_CODE, 0, KIDT_ACCESS_RING3, I686_TRAP_GATE);
+    SetIdtGate(ProcessorBlock->IdtBase, 0x03, (PVOID)ArTrapEntry[0x03], KGDT_R0_CODE, 0, KIDT_ACCESS_RING3, I686_TRAP_GATE);
-    SetIdtGate(ProcessorBlock->IdtBase, 0x04, (PVOID)ArTrap0x04, KGDT_R0_CODE, 0, KIDT_ACCESS_RING3, I686_TRAP_GATE);
+    SetIdtGate(ProcessorBlock->IdtBase, 0x04, (PVOID)ArTrapEntry[0x04], KGDT_R0_CODE, 0, KIDT_ACCESS_RING3, I686_TRAP_GATE);
-    SetIdtGate(ProcessorBlock->IdtBase, 0x05, (PVOID)ArTrap0x05, KGDT_R0_CODE, 0, KIDT_ACCESS_RING0, I686_TRAP_GATE);
+    SetIdtGate(ProcessorBlock->IdtBase, 0x05, (PVOID)ArTrapEntry[0x05], KGDT_R0_CODE, 0, KIDT_ACCESS_RING0, I686_TRAP_GATE);
-    SetIdtGate(ProcessorBlock->IdtBase, 0x06, (PVOID)ArTrap0x06, KGDT_R0_CODE, 0, KIDT_ACCESS_RING0, I686_TRAP_GATE);
+    SetIdtGate(ProcessorBlock->IdtBase, 0x06, (PVOID)ArTrapEntry[0x06], KGDT_R0_CODE, 0, KIDT_ACCESS_RING0, I686_TRAP_GATE);
-    SetIdtGate(ProcessorBlock->IdtBase, 0x07, (PVOID)ArTrap0x07, KGDT_R0_CODE, 0, KIDT_ACCESS_RING0, I686_TRAP_GATE);
+    SetIdtGate(ProcessorBlock->IdtBase, 0x07, (PVOID)ArTrapEntry[0x07], KGDT_R0_CODE, 0, KIDT_ACCESS_RING0, I686_TRAP_GATE);
-    SetIdtGate(ProcessorBlock->IdtBase, 0x08, (PVOID)ArTrap0x08, KGDT_R0_CODE, 0, KIDT_ACCESS_RING0, I686_TRAP_GATE);
+    SetIdtGate(ProcessorBlock->IdtBase, 0x08, (PVOID)ArTrapEntry[0x08], KGDT_R0_CODE, 0, KIDT_ACCESS_RING0, I686_TRAP_GATE);
-    SetIdtGate(ProcessorBlock->IdtBase, 0x09, (PVOID)ArTrap0x09, KGDT_R0_CODE, 0, KIDT_ACCESS_RING0, I686_TRAP_GATE);
+    SetIdtGate(ProcessorBlock->IdtBase, 0x09, (PVOID)ArTrapEntry[0x09], KGDT_R0_CODE, 0, KIDT_ACCESS_RING0, I686_TRAP_GATE);
-    SetIdtGate(ProcessorBlock->IdtBase, 0x0A, (PVOID)ArTrap0x0A, KGDT_R0_CODE, 0, KIDT_ACCESS_RING0, I686_TRAP_GATE);
+    SetIdtGate(ProcessorBlock->IdtBase, 0x0A, (PVOID)ArTrapEntry[0x0A], KGDT_R0_CODE, 0, KIDT_ACCESS_RING0, I686_TRAP_GATE);
-    SetIdtGate(ProcessorBlock->IdtBase, 0x0B, (PVOID)ArTrap0x0B, KGDT_R0_CODE, 0, KIDT_ACCESS_RING0, I686_TRAP_GATE);
+    SetIdtGate(ProcessorBlock->IdtBase, 0x0B, (PVOID)ArTrapEntry[0x0B], KGDT_R0_CODE, 0, KIDT_ACCESS_RING0, I686_TRAP_GATE);
-    SetIdtGate(ProcessorBlock->IdtBase, 0x0C, (PVOID)ArTrap0x0C, KGDT_R0_CODE, 0, KIDT_ACCESS_RING0, I686_TRAP_GATE);
+    SetIdtGate(ProcessorBlock->IdtBase, 0x0C, (PVOID)ArTrapEntry[0x0C], KGDT_R0_CODE, 0, KIDT_ACCESS_RING0, I686_TRAP_GATE);
-    SetIdtGate(ProcessorBlock->IdtBase, 0x0D, (PVOID)ArTrap0x0D, KGDT_R0_CODE, 0, KIDT_ACCESS_RING0, I686_TRAP_GATE);
+    SetIdtGate(ProcessorBlock->IdtBase, 0x0D, (PVOID)ArTrapEntry[0x0D], KGDT_R0_CODE, 0, KIDT_ACCESS_RING0, I686_TRAP_GATE);
-    SetIdtGate(ProcessorBlock->IdtBase, 0x0E, (PVOID)ArTrap0x0E, KGDT_R0_CODE, 0, KIDT_ACCESS_RING0, I686_TRAP_GATE);
+    SetIdtGate(ProcessorBlock->IdtBase, 0x0E, (PVOID)ArTrapEntry[0x0E], KGDT_R0_CODE, 0, KIDT_ACCESS_RING0, I686_TRAP_GATE);
-    SetIdtGate(ProcessorBlock->IdtBase, 0x10, (PVOID)ArTrap0x10, KGDT_R0_CODE, 0, KIDT_ACCESS_RING0, I686_TRAP_GATE);
+    SetIdtGate(ProcessorBlock->IdtBase, 0x10, (PVOID)ArTrapEntry[0x10], KGDT_R0_CODE, 0, KIDT_ACCESS_RING0, I686_TRAP_GATE);
-    SetIdtGate(ProcessorBlock->IdtBase, 0x11, (PVOID)ArTrap0x11, KGDT_R0_CODE, 0, KIDT_ACCESS_RING0, I686_TRAP_GATE);
+    SetIdtGate(ProcessorBlock->IdtBase, 0x11, (PVOID)ArTrapEntry[0x11], KGDT_R0_CODE, 0, KIDT_ACCESS_RING0, I686_TRAP_GATE);
-    SetIdtGate(ProcessorBlock->IdtBase, 0x12, (PVOID)ArTrap0x12, KGDT_R0_CODE, 0, KIDT_ACCESS_RING0, I686_TRAP_GATE);
+    SetIdtGate(ProcessorBlock->IdtBase, 0x12, (PVOID)ArTrapEntry[0x12], KGDT_R0_CODE, 0, KIDT_ACCESS_RING0, I686_TRAP_GATE);
-    SetIdtGate(ProcessorBlock->IdtBase, 0x13, (PVOID)ArTrap0x13, KGDT_R0_CODE, 0, KIDT_ACCESS_RING0, I686_TRAP_GATE);
+    SetIdtGate(ProcessorBlock->IdtBase, 0x13, (PVOID)ArTrapEntry[0x13], KGDT_R0_CODE, 0, KIDT_ACCESS_RING0, I686_TRAP_GATE);
-    SetIdtGate(ProcessorBlock->IdtBase, 0x2A, (PVOID)ArTrap0x2A, KGDT_R0_CODE, 0, KIDT_ACCESS_RING3, I686_TRAP_GATE);
+    SetIdtGate(ProcessorBlock->IdtBase, 0x2A, (PVOID)ArTrapEntry[0x2A], KGDT_R0_CODE, 0, KIDT_ACCESS_RING3, I686_TRAP_GATE);
-    SetIdtGate(ProcessorBlock->IdtBase, 0x2B, (PVOID)ArTrap0x2B, KGDT_R0_CODE, 0, KIDT_ACCESS_RING3, I686_TRAP_GATE);
+    SetIdtGate(ProcessorBlock->IdtBase, 0x2B, (PVOID)ArTrapEntry[0x2B], KGDT_R0_CODE, 0, KIDT_ACCESS_RING3, I686_TRAP_GATE);
-    SetIdtGate(ProcessorBlock->IdtBase, 0x2C, (PVOID)ArTrap0x2C, KGDT_R0_CODE, 0, KIDT_ACCESS_RING3, I686_TRAP_GATE);
+    SetIdtGate(ProcessorBlock->IdtBase, 0x2C, (PVOID)ArTrapEntry[0x2C], KGDT_R0_CODE, 0, KIDT_ACCESS_RING3, I686_TRAP_GATE);
-    SetIdtGate(ProcessorBlock->IdtBase, 0x2D, (PVOID)ArTrap0x2D, KGDT_R0_CODE, 0, KIDT_ACCESS_RING3, I686_TRAP_GATE);
+    SetIdtGate(ProcessorBlock->IdtBase, 0x2D, (PVOID)ArTrapEntry[0x2D], KGDT_R0_CODE, 0, KIDT_ACCESS_RING3, I686_TRAP_GATE);
-    SetIdtGate(ProcessorBlock->IdtBase, 0x2E, (PVOID)ArTrap0x2E, KGDT_R0_CODE, 0, KIDT_ACCESS_RING3, I686_TRAP_GATE);
+    SetIdtGate(ProcessorBlock->IdtBase, 0x2E, (PVOID)ArTrapEntry[0x2E], KGDT_R0_CODE, 0, KIDT_ACCESS_RING3, I686_TRAP_GATE);
 }
 
 /**
@@ -506,7 +507,7 @@ AR::ProcSup::SetDoubleFaultTssEntry(IN PKPROCESSOR_BLOCK ProcessorBlock,
     Tss->CR3 = CpuFunc::ReadControlRegister(3);
     Tss->Esp = (ULONG_PTR)KernelFaultStack;
     Tss->Esp0 = (ULONG_PTR)KernelFaultStack;
-    Tss->Eip = PtrToUlong(ArTrap0x08);
+    Tss->Eip = PtrToUlong(ArTrapEntry[0x08]);
     Tss->Cs = KGDT_R0_CODE;
     Tss->Ds = KGDT_R3_DATA | RPL_MASK;
     Tss->Es = KGDT_R3_DATA | RPL_MASK;
@@ -720,7 +721,7 @@ AR::ProcSup::SetNonMaskableInterruptTssEntry(IN PKPROCESSOR_BLOCK ProcessorBlock
     Tss->CR3 = CpuFunc::ReadControlRegister(3);
     Tss->Esp = (ULONG_PTR)KernelFaultStack;
     Tss->Esp0 = (ULONG_PTR)KernelFaultStack;
-    Tss->Eip = PtrToUlong(ArTrap0x02);
+    Tss->Eip = PtrToUlong(ArTrapEntry[0x02]);
     Tss->Cs = KGDT_R0_CODE;
     Tss->Ds = KGDT_R3_DATA | RPL_MASK;
     Tss->Es = KGDT_R3_DATA | RPL_MASK;

xtoskrnl/hl/amd64/irq.cc

@@ -1,9 +1,10 @@
 /**
  * PROJECT:         ExectOS
  * COPYRIGHT:       See COPYING.md in the top level directory
- * FILE:            xtoskrnl/ke/i686/irq.cc
+ * FILE:            xtoskrnl/hl/amd64/irq.cc
- * DESCRIPTION:     Kernel interrupts support for i686 architecture
+ * DESCRIPTION:     Interrupts support for amd64 architecture
  * DEVELOPERS:      Rafal Kupiec <belliash@codingworkshop.eu.org>
+ *                  Aiken Harris <harraiken91@gmail.com>
  */
 
 #include <xtos.hh>
@@ -24,7 +25,7 @@
  */
 XTAPI
 VOID
-KE::Irq::SetInterruptHandler(IN ULONG Vector,
+HL::Irq::SetInterruptHandler(IN ULONG Vector,
                              IN PVOID Handler)
 {
     PKPROCESSOR_BLOCK ProcessorBlock;
@@ -33,6 +34,11 @@ KE::Irq::SetInterruptHandler(IN ULONG Vector,
     ProcessorBlock = KE::Processor::GetCurrentProcessorBlock();
 
     /* Update interrupt handler */
-    ProcessorBlock->IdtBase[(UCHAR) Vector].Offset = (USHORT)((ULONG)Handler & 0xFFFF);
+    AR::ProcSup::SetIdtGate(ProcessorBlock->IdtBase,
-    ProcessorBlock->IdtBase[(UCHAR) Vector].ExtendedOffset = (USHORT)((ULONG)Handler >> 16);
+                            Vector,
+                            Handler,
+                            KGDT_R0_CODE,
+                            0,
+                            KIDT_ACCESS_RING0,
+                            AMD64_INTERRUPT_GATE);
 }

xtoskrnl/hl/i686/irq.cc

@@ -1,9 +1,10 @@
 /**
  * PROJECT:         ExectOS
  * COPYRIGHT:       See COPYING.md in the top level directory
- * FILE:            xtoskrnl/ke/amd64/irq.cc
+ * FILE:            xtoskrnl/hl/i686/irq.cc
- * DESCRIPTION:     Kernel interrupts support for amd64 architecture
+ * DESCRIPTION:     Interrupts support for i686 architecture
  * DEVELOPERS:      Rafal Kupiec <belliash@codingworkshop.eu.org>
+ *                  Aiken Harris <harraiken91@gmail.com>
  */
 
 #include <xtos.hh>
@@ -24,7 +25,7 @@
  */
 XTAPI
 VOID
-KE::Irq::SetInterruptHandler(IN ULONG Vector,
+HL::Irq::SetInterruptHandler(IN ULONG Vector,
                              IN PVOID Handler)
 {
     PKPROCESSOR_BLOCK ProcessorBlock;
@@ -33,7 +34,11 @@ KE::Irq::SetInterruptHandler(IN ULONG Vector,
     ProcessorBlock = KE::Processor::GetCurrentProcessorBlock();
 
     /* Update interrupt handler */
-    ProcessorBlock->IdtBase[(UCHAR) Vector].OffsetLow = ((ULONG_PTR)Handler & 0xFFFF);
+    AR::ProcSup::SetIdtGate(ProcessorBlock->IdtBase,
-    ProcessorBlock->IdtBase[(UCHAR) Vector].OffsetMiddle = (((ULONG_PTR)Handler >> 16) & 0xFFFF);
+                            Vector,
-    ProcessorBlock->IdtBase[(UCHAR) Vector].OffsetHigh = (ULONG_PTR)Handler >> 32;
+                            Handler,
+                            KGDT_R0_CODE,
+                            0,
+                            KIDT_ACCESS_RING0,
+                            I686_INTERRUPT_GATE);
 }

xtoskrnl/hl/x86/pic.cc

@@ -9,6 +9,41 @@
 #include <xtos.hh>
 
 
+/**
+ * Checks whether the APIC is supported by the processor.
+ *
+ * @return This routine returns TRUE if APIC is supported, or FALSE otherwise.
+ *
+ * @since XT 1.0
+ */
+XTAPI
+BOOLEAN
+HL::Pic::CheckApicSupport(VOID)
+{
+    CPUID_REGISTERS CpuRegisters;
+
+    /* Prepare CPUID registers */
+    CpuRegisters.Leaf = CPUID_GET_STANDARD1_FEATURES;
+    CpuRegisters.SubLeaf = 0;
+    CpuRegisters.Eax = 0;
+    CpuRegisters.Ebx = 0;
+    CpuRegisters.Ecx = 0;
+    CpuRegisters.Edx = 0;
+
+    /* Get CPUID */
+    AR::CpuFunc::CpuId(&CpuRegisters);
+
+    /* Check APIC status from the CPUID results */
+    if(!(CpuRegisters.Edx & CPUID_FEATURES_EDX_APIC))
+    {
+        /* APIC is not supported */
+        return FALSE;
+    }
+
+    /* APIC is supported */
+    return TRUE;
+}
+
 /**
  * Checks whether the x2APIC extension is supported by the processor.
  *
@@ -124,6 +159,14 @@ HL::Pic::InitializeApic(VOID)
     APIC_LVT_REGISTER LvtRegister;
     ULONG CpuNumber;
 
+    /* Check APIC support */
+    if(!CheckApicSupport())
+    {
+        /* APIC is not supported, raise kernel panic */
+        DebugPrint(L"FATAL ERROR: Local APIC not present.\n");
+        KE::Crash::Panic(0x5D, CPUID_GET_STANDARD1_FEATURES, 0x0, 0x0, CPUID_FEATURES_EDX_APIC);
+    }
+
     /* Determine APIC mode (xAPIC compatibility or x2APIC) */
     if(CheckX2ApicSupport())
     {
@@ -206,8 +249,8 @@ HL::Pic::InitializeApic(VOID)
     WriteApicRegister(APIC_LINT1, LvtRegister.Long);
 
     /* Register interrupt handlers */
-    KE::Irq::SetInterruptHandler(APIC_VECTOR_SPURIOUS, (PVOID)HandleApicSpuriousService);
+    HL::Irq::SetInterruptHandler(APIC_VECTOR_SPURIOUS, (PVOID)HandleApicSpuriousService);
-    KE::Irq::SetInterruptHandler(PIC1_VECTOR_SPURIOUS, (PVOID)HandlePicSpuriousService);
+    HL::Irq::SetInterruptHandler(PIC1_VECTOR_SPURIOUS, (PVOID)HandlePicSpuriousService);
 
     /* Clear any pre-existing errors */
     WriteApicRegister(APIC_ESR, 0);

xtoskrnl/includes/ar/amd64/asmsup.h

@@ -56,6 +56,8 @@
 #define TrapSegEs                               330
 #define TrapSegFs                               332
 #define TrapSegGs                               334
+#define TrapRsp                                 496
+#define TrapSegSs                               504
 
 /* KTRAP_FRAME length related definitions */
 #define TRAP_FRAME_SIZE                         512

xtoskrnl/includes/ar/amd64/assembly.hh

@@ -15,9 +15,14 @@
 /* TrampolineEnableXpa end address to calculate trampoline size */
 XTCLINK PVOID ArEnableExtendedPhysicalAddressingEnd[];
 
+/* External array of pointers to the interrupt handlers */
+XTCLINK ULONG_PTR ArInterruptEntry[256];
+
 /* TrampolineApStartup end address to calculate trampoline size */
 XTCLINK PVOID ArStartApplicationProcessorEnd[];
 
+/* External array of pointers to the trap handlers */
+XTCLINK ULONG_PTR ArTrapEntry[256];
 
 /* Forward reference for assembler code */
 XTCLINK
@@ -30,129 +35,4 @@ XTCDECL
 VOID
 ArStartApplicationProcessor(VOID);
 
-XTCLINK
-XTCDECL
-VOID
-ArTrap0x00(VOID);
-
-XTCLINK
-XTCDECL
-VOID
-ArTrap0x01(VOID);
-
-XTCLINK
-XTCDECL
-VOID
-ArTrap0x02(VOID);
-
-XTCLINK
-XTCDECL
-VOID
-ArTrap0x03(VOID);
-
-XTCLINK
-XTCDECL
-VOID
-ArTrap0x04(VOID);
-
-XTCLINK
-XTCDECL
-VOID
-ArTrap0x05(VOID);
-
-XTCLINK
-XTCDECL
-VOID
-ArTrap0x06(VOID);
-
-XTCLINK
-XTCDECL
-VOID
-ArTrap0x07(VOID);
-
-XTCLINK
-XTCDECL
-VOID
-ArTrap0x08(VOID);
-
-XTCLINK
-XTCDECL
-VOID
-ArTrap0x09(VOID);
-
-XTCLINK
-XTCDECL
-VOID
-ArTrap0x0A(VOID);
-
-XTCLINK
-XTCDECL
-VOID
-ArTrap0x0B(VOID);
-
-XTCLINK
-XTCDECL
-VOID
-ArTrap0x0C(VOID);
-
-XTCLINK
-XTCDECL
-VOID
-ArTrap0x0D(VOID);
-
-XTCLINK
-XTCDECL
-VOID
-ArTrap0x0E(VOID);
-
-XTCLINK
-XTCDECL
-VOID
-ArTrap0x10(VOID);
-
-XTCLINK
-XTCDECL
-VOID
-ArTrap0x11(VOID);
-
-XTCLINK
-XTCDECL
-VOID
-ArTrap0x12(VOID);
-
-XTCLINK
-XTCDECL
-VOID
-ArTrap0x13(VOID);
-
-XTCLINK
-XTCDECL
-VOID
-ArTrap0x1F(VOID);
-
-XTCLINK
-XTCDECL
-VOID
-ArTrap0x2C(VOID);
-
-XTCLINK
-XTCDECL
-VOID
-ArTrap0x2D(VOID);
-
-XTCLINK
-XTCDECL
-VOID
-ArTrap0x2F(VOID);
-
-XTCLINK
-XTCDECL
-VOID
-ArTrap0xE1(VOID);
-
-XTCLINK
-XTCDECL
-VOID
-ArTrap0xFF(VOID);
-
 #endif /* __XTOSKRNL_AR_ASSEMBLY_HH */

xtoskrnl/includes/ar/amd64/procsup.hh

@@ -31,6 +31,13 @@ namespace AR
                                                        OUT PVOID *TrampolineCode,
                                                        OUT PULONG_PTR TrampolineSize);
             STATIC XTAPI VOID InitializeProcessor(IN PVOID ProcessorStructures);
+            STATIC XTAPI VOID SetIdtGate(IN PKIDTENTRY Idt,
+                                         IN USHORT Vector,
+                                         IN PVOID Handler,
+                                         IN USHORT Selector,
+                                         IN USHORT Ist,
+                                         IN USHORT Dpl,
+                                         IN USHORT Type);
 
         private:
             STATIC XTAPI VOID IdentifyProcessor(VOID);
@@ -62,13 +69,6 @@ namespace AR
             STATIC XTAPI VOID SetGdtEntryBase(IN PKGDTENTRY Gdt,
                                               IN USHORT Selector,
                                               IN ULONG_PTR Base);
-            STATIC XTAPI VOID SetIdtGate(IN PKIDTENTRY Idt,
-                                         IN USHORT Vector,
-                                         IN PVOID Handler,
-                                         IN USHORT Selector,
-                                         IN USHORT Ist,
-                                         IN USHORT Dpl,
-                                         IN USHORT Type);
     };
 }
 

xtoskrnl/includes/ar/i686/asmsup.h

@@ -24,9 +24,11 @@
 #define TrapSegEs                               38
 #define TrapSegFs                               40
 #define TrapSegGs                               42
+#define TrapEsp                                 92
+#define TrapSegSs                               96
 
 /* KTRAP_FRAME length related definitions */
 #define TRAP_FRAME_SIZE                         100
 #define TRAP_REGISTERS_SIZE                     56
 
-#endif /* __XTOSKRNL_AMD64_ASMSUP_H */
+#endif /* __XTOSKRNL_I686_ASMSUP_H */

xtoskrnl/includes/ar/i686/assembly.hh

@@ -12,9 +12,14 @@
 #include <xtos.hh>
 
 
+/* External array of pointers to the interrupt handlers */
+XTCLINK ULONG_PTR ArInterruptEntry[256];
+
 /* TrampolineApStartup end address to calculate trampoline size */
 XTCLINK PVOID ArStartApplicationProcessorEnd[];
 
+/* External array of pointers to the trap handlers */
+XTCLINK ULONG_PTR ArTrapEntry[256];
 
 /* Forward reference for assembler code */
 XTCLINK
@@ -22,130 +27,4 @@ XTCDECL
 VOID
 ArStartApplicationProcessor(VOID);
 
-XTCLINK
-XTCDECL
-VOID
-ArTrap0x00(VOID);
-
-XTCLINK
-XTCDECL
-VOID
-ArTrap0x01(VOID);
-
-XTCLINK
-XTCDECL
-VOID
-ArTrap0x02(VOID);
-
-XTCLINK
-XTCDECL
-VOID
-ArTrap0x03(VOID);
-
-XTCLINK
-XTCDECL
-VOID
-ArTrap0x04(VOID);
-
-XTCLINK
-XTCDECL
-VOID
-ArTrap0x05(VOID);
-
-XTCLINK
-XTCDECL
-VOID
-ArTrap0x06(VOID);
-
-XTCLINK
-XTCDECL
-VOID
-ArTrap0x07(VOID);
-
-XTCLINK
-XTCDECL
-VOID
-ArTrap0x08(VOID);
-
-XTCLINK
-XTCDECL
-VOID
-ArTrap0x09(VOID);
-
-XTCLINK
-XTCDECL
-VOID
-ArTrap0x0A(VOID);
-
-XTCLINK
-XTCDECL
-VOID
-ArTrap0x0B(VOID);
-
-XTCLINK
-XTCDECL
-VOID
-ArTrap0x0C(VOID);
-
-XTCLINK
-XTCDECL
-VOID
-ArTrap0x0D(VOID);
-
-XTCLINK
-XTCDECL
-VOID
-ArTrap0x0E(VOID);
-
-XTCLINK
-XTCDECL
-VOID
-ArTrap0x10(VOID);
-
-XTCLINK
-XTCDECL
-VOID
-ArTrap0x11(VOID);
-
-XTCLINK
-XTCDECL
-VOID
-ArTrap0x12(VOID);
-
-XTCLINK
-XTCDECL
-VOID
-ArTrap0x13(VOID);
-
-XTCLINK
-XTCDECL
-VOID
-ArTrap0x2A(VOID);
-
-XTCLINK
-XTCDECL
-VOID
-ArTrap0x2B(VOID);
-
-XTCLINK
-XTCDECL
-VOID
-ArTrap0x2C(VOID);
-
-XTCLINK
-XTCDECL
-VOID
-ArTrap0x2D(VOID);
-
-XTCLINK
-XTCDECL
-VOID
-ArTrap0x2E(VOID);
-
-XTCLINK
-XTCDECL
-VOID
-ArTrap0xFF(VOID);
-
-
 #endif /* __XTOSKRNL_AR_ASSEMBLY_HH */

xtoskrnl/includes/ar/i686/procsup.hh

@@ -34,6 +34,13 @@ namespace AR
                                                        OUT PVOID *TrampolineCode,
                                                        OUT PULONG_PTR TrampolineSize);
             STATIC XTAPI VOID InitializeProcessor(IN PVOID ProcessorStructures);
+            STATIC XTAPI VOID SetIdtGate(IN PKIDTENTRY Idt,
+                                         IN USHORT Vector,
+                                         IN PVOID Handler,
+                                         IN USHORT Selector,
+                                         IN USHORT Ist,
+                                         IN USHORT Dpl,
+                                         IN USHORT Type);
 
         private:
             STATIC XTAPI VOID IdentifyProcessor(VOID);
@@ -67,13 +74,6 @@ namespace AR
             STATIC XTAPI VOID SetGdtEntryBase(IN PKGDTENTRY Gdt,
                                               IN USHORT Selector,
                                               IN ULONG_PTR Base);
-            STATIC XTAPI VOID SetIdtGate(IN PKIDTENTRY Idt,
-                                         IN USHORT Vector,
-                                         IN PVOID Handler,
-                                         IN USHORT Selector,
-                                         IN USHORT Ist,
-                                         IN USHORT Dpl,
-                                         IN USHORT Type);
             STATIC XTAPI VOID SetNonMaskableInterruptTssEntry(IN PKPROCESSOR_BLOCK ProcessorBlock,
                                                               IN PVOID KernelFaultStack);
 

xtoskrnl/includes/hl.hh

@@ -18,6 +18,7 @@
 #include <hl/init.hh>
 #include <hl/ioport.hh>
 #include <hl/ioreg.hh>
+#include <hl/irq.hh>
 #include <hl/pic.hh>
 #include <hl/runlevel.hh>
 

xtoskrnl/includes/hl/irq.hh

@@ -1,19 +1,19 @@
 /**
  * PROJECT:         ExectOS
  * COPYRIGHT:       See COPYING.md in the top level directory
- * FILE:            xtoskrnl/includes/ke/irq.hh
+ * FILE:            xtoskrnl/includes/hl/irq.hh
- * DESCRIPTION:     Kernel interrupts support
+ * DESCRIPTION:     Interrupts support
  * DEVELOPERS:      Aiken Harris <harraiken91@gmail.com>
  */
 
-#ifndef __XTOSKRNL_KE_IRQ_HH
+#ifndef __XTOSKRNL_HL_IRQ_HH
-#define __XTOSKRNL_KE_IRQ_HH
+#define __XTOSKRNL_HL_IRQ_HH
 
 #include <xtos.hh>
 
 
-/* Kernel Library */
+/* Hardware Layer */
-namespace KE
+namespace HL
 {
     class Irq
     {
@@ -23,4 +23,4 @@ namespace KE
     };
 }
 
-#endif /* __XTOSKRNL_KE_IRQ_HH */
+#endif /* __XTOSKRNL_HL_IRQ_HH */

xtoskrnl/includes/hl/pic.hh

@@ -32,6 +32,7 @@ namespace HL
                                                      IN ULONGLONG Value);
 
         private:
+            STATIC XTAPI BOOLEAN CheckApicSupport(VOID);
             STATIC XTAPI BOOLEAN CheckX2ApicSupport(VOID);
             STATIC XTCDECL VOID HandleApicSpuriousService(VOID);
             STATIC XTCDECL VOID HandlePicSpuriousService(VOID);

xtoskrnl/includes/ke.hh

@@ -16,7 +16,7 @@
 #include <ke/crash.hh>
 #include <ke/dpc.hh>
 #include <ke/event.hh>
-#include <ke/irq.hh>
+#include <ke/guard.hh>
 #include <ke/kprocess.hh>
 #include <ke/krnlinit.hh>
 #include <ke/kthread.hh>

xtoskrnl/includes/ke/crash.hh

@@ -20,11 +20,11 @@ namespace KE
         public:
             STATIC XTAPI VOID HaltSystem(VOID);
             STATIC XTAPI VOID Panic(IN ULONG Code);
-            STATIC XTAPI VOID PanicEx(IN ULONG Code,
+            STATIC XTAPI VOID Panic(IN ULONG Code,
-                                      IN ULONG_PTR Parameter1,
+                                    IN ULONG_PTR Parameter1,
-                                      IN ULONG_PTR Parameter2,
+                                    IN ULONG_PTR Parameter2,
-                                      IN ULONG_PTR Parameter3,
+                                    IN ULONG_PTR Parameter3,
-                                      IN ULONG_PTR Parameter4);
+                                    IN ULONG_PTR Parameter4);
     };
 }
 

xtoskrnl/includes/ke/guard.hh

@@ -0,0 +1,61 @@
+/**
+ * PROJECT:         ExectOS
+ * COPYRIGHT:       See COPYING.md in the top level directory
+ * FILE:            xtoskrnl/includes/ke/guard.hh
+ * DESCRIPTION:     Kernel synchronization guard
+ * DEVELOPERS:      Aiken Harris <harraiken91@gmail.com>
+ */
+
+#ifndef __XTOSKRNL_KE_GUARD_HH
+#define __XTOSKRNL_KE_GUARD_HH
+
+#include <xtos.hh>
+#include <ke/spinlock.hh>
+
+/* Kernel Library */
+namespace KE
+{
+    class QueuedSpinLockGuard
+    {
+        private:
+            KSPIN_LOCK_QUEUE_LEVEL QueuedLockLevel;
+
+        public:
+            QueuedSpinLockGuard(IN OUT KSPIN_LOCK_QUEUE_LEVEL LockLevel)
+            {
+                QueuedLockLevel = LockLevel;
+                KE::SpinLock::AcquireQueuedSpinLock(QueuedLockLevel);
+            }
+
+            ~QueuedSpinLockGuard()
+            {
+                KE::SpinLock::ReleaseQueuedSpinLock(QueuedLockLevel);
+            }
+
+            QueuedSpinLockGuard(const QueuedSpinLockGuard&) = delete;
+            QueuedSpinLockGuard& operator=(const QueuedSpinLockGuard&) = delete;
+    };
+
+    class SpinLockGuard
+    {
+        private:
+            PKSPIN_LOCK Lock;
+
+        public:
+            SpinLockGuard(IN OUT PKSPIN_LOCK SpinLock)
+            {
+                Lock = SpinLock;
+                KE::SpinLock::AcquireSpinLock(Lock);
+            }
+
+            ~SpinLockGuard()
+            {
+                KE::SpinLock::ReleaseSpinLock(Lock);
+            }
+
+            SpinLockGuard(const SpinLockGuard&) = delete;
+            SpinLockGuard& operator=(const SpinLockGuard&) = delete;
+    };
+}
+
+#endif /* __XTOSKRNL_KE_GUARD_HH */

xtoskrnl/includes/ke/info.hh

@@ -1,27 +0,0 @@
-/**
- * PROJECT:         ExectOS
- * COPYRIGHT:       See COPYING.md in the top level directory
- * FILE:            xtoskrnl/includes/ke/info.hh
- * DESCRIPTION:     Generic kernel information support
- * DEVELOPERS:      Aiken Harris <harraiken91@gmail.com>
- */
-
-#ifndef __XTOSKRNL_KE_INFO_HH
-#define __XTOSKRNL_KE_INFO_HH
-
-#include <xtos.hh>
-
-
-/* Kernel Library */
-namespace KE
-{
-    class Info
-    {
-        public:
-            STATIC XTAPI SYSTEM_FIRMWARE_TYPE GetFirmwareType(VOID);
-            STATIC XTAPI XTSTATUS GetKernelParameter(IN PCWSTR ParameterName,
-                                                      OUT PCWSTR *Parameter);
-    };
-}
-
-#endif /* __XTOSKRNL_KE_INFO_HH */

xtoskrnl/includes/ke/spinlock.hh

@@ -44,47 +44,6 @@ namespace KE
             STATIC XTFASTCALL VOID ReleaseSpinLock(IN OUT PKSPIN_LOCK SpinLock);
             STATIC XTFASTCALL BOOLEAN TestSpinLock(IN PKSPIN_LOCK SpinLock);
     };
-
-    class QueuedSpinLockGuard
-    {
-        private:
-            KSPIN_LOCK_QUEUE_LEVEL QueuedLockLevel;
-
-        public:
-            QueuedSpinLockGuard(IN OUT KSPIN_LOCK_QUEUE_LEVEL LockLevel)
-            {
-                QueuedLockLevel = LockLevel;
-                KE::SpinLock::AcquireQueuedSpinLock(QueuedLockLevel);
-            }
-
-            ~QueuedSpinLockGuard()
-            {
-                KE::SpinLock::ReleaseQueuedSpinLock(QueuedLockLevel);
-            }
-
-            QueuedSpinLockGuard(const QueuedSpinLockGuard&) = delete;
-            QueuedSpinLockGuard& operator=(const QueuedSpinLockGuard&) = delete;
-    };
-
-    class SpinLockGuard
-    {
-        private:
-            PKSPIN_LOCK SpinLock;
-
-        public:
-            SpinLockGuard(IN OUT PKSPIN_LOCK SpinLock)
-            {
-                KE::SpinLock::AcquireSpinLock(SpinLock);
-            }
-
-            ~SpinLockGuard()
-            {
-                KE::SpinLock::ReleaseSpinLock(SpinLock);
-            }
-
-            SpinLockGuard(const SpinLockGuard&) = delete;
-            SpinLockGuard& operator=(const SpinLockGuard&) = delete;
-    };
 }
 
 #endif /* __XTOSKRNL_KE_SPINLOCK_HH */

xtoskrnl/ke/crash.cc

@@ -43,7 +43,7 @@ XTAPI
 VOID
 KE::Crash::Panic(IN ULONG Code)
 {
-    PanicEx(Code, 0, 0, 0, 0);
+    Panic(Code, 0, 0, 0, 0);
 }
 
 /**
@@ -70,12 +70,13 @@ KE::Crash::Panic(IN ULONG Code)
  */
 XTAPI
 VOID
-KE::Crash::PanicEx(IN ULONG Code,
+KE::Crash::Panic(IN ULONG Code,
-               IN ULONG_PTR Parameter1,
+                 IN ULONG_PTR Parameter1,
-               IN ULONG_PTR Parameter2,
+                 IN ULONG_PTR Parameter2,
-               IN ULONG_PTR Parameter3,
+                 IN ULONG_PTR Parameter3,
-               IN ULONG_PTR Parameter4)
+                 IN ULONG_PTR Parameter4)
 {
-    KD::DebugIo::KdPrint(L"Fatal System Error: 0x%08lx\nKernel Panic!\n\n", Code);
+    KD::DebugIo::KdPrint(L"Fatal System Error: 0x%08lx (0x%zx 0x%zx 0x%zx 0x%zx)\nKernel Panic!\n\n",
+                         Code, Parameter1, Parameter2, Parameter3, Parameter4);
     HaltSystem();
 }

xtoskrnl/rtl/amd64/exsup.cc

@@ -74,7 +74,7 @@ __CxxFrameHandler3(IN PEXCEPTION_RECORD ExceptionRecord,
 
     /* Disable interrupts and hang */
     AR::CpuFunc::ClearInterruptFlag();
-    KE::Crash::Panic(0); // CXX_FRAME_HANDLER_CALLED
+    KE::Crash::Panic(0);
 
     /* Continue search */
     return ExceptionContinueSearch;
@@ -129,5 +129,5 @@ _purecall(VOID)
 
     /* Disable interrupts and hang */
     AR::CpuFunc::ClearInterruptFlag();
-    KE::Crash::Panic(0); // PURE_VIRTUAL_FUNCTION_CALL
+    KE::Crash::Panic(0);
 }

xtoskrnl/rtl/i686/exsup.cc

@@ -74,7 +74,7 @@ __CxxFrameHandler3(IN PEXCEPTION_RECORD ExceptionRecord,
 
     /* Disable interrupts and hang */
     AR::CpuFunc::ClearInterruptFlag();
-    KE::Crash::Panic(0); // CXX_FRAME_HANDLER_CALLED
+    KE::Crash::Panic(0);
 
     /* Continue search */
     return ExceptionContinueSearch;
@@ -129,5 +129,5 @@ _purecall(VOID)
 
     /* Disable interrupts and hang */
     AR::CpuFunc::ClearInterruptFlag();
-    KE::Crash::Panic(0); // PURE_VIRTUAL_FUNCTION_CALL
+    KE::Crash::Panic(0);
 }