From ca87eab663e792d5711ee6d6696d9d73c828981d Mon Sep 17 00:00:00 2001 From: Aiken Harris Date: Tue, 30 Jul 2024 14:46:08 +0200 Subject: [PATCH 1/8] Temporary fake trampoline --- xtoskrnl/ar/amd64/archsup.S | 15 +++++++++++++++ xtoskrnl/ar/i686/archsup.S | 12 ++++++++++++ 2 files changed, 27 insertions(+) diff --git a/xtoskrnl/ar/amd64/archsup.S b/xtoskrnl/ar/amd64/archsup.S index 1c18ab2..3c530c4 100644 --- a/xtoskrnl/ar/amd64/archsup.S +++ b/xtoskrnl/ar/amd64/archsup.S @@ -12,6 +12,21 @@ .text +.global ArStartApplicationProcessor +ArStartApplicationProcessor: + /* 16-bit code (real mode) */ + .code16 + + cli + cld + hlt + + /* 32-bit code (protected mode) */ + .code32 + + /* 64-bit code (long mode) */ + .code64 + /** * This macro creates a trap handler for the specified vector. * diff --git a/xtoskrnl/ar/i686/archsup.S b/xtoskrnl/ar/i686/archsup.S index e80ac42..dec4396 100644 --- a/xtoskrnl/ar/i686/archsup.S +++ b/xtoskrnl/ar/i686/archsup.S @@ -12,6 +12,18 @@ .text +.global _ArStartApplicationProcessor +_ArStartApplicationProcessor: + /* 16-bit code (real mode) */ + .code16 + + cli + cld + hlt + + /* 32-bit code (protected mode) */ + .code32 + /** * This macro creates a trap handler for the specified vector. * -- 2.50.1 From 188e4e7a3d4b078aa356b3825a7bc42d8deeca3f Mon Sep 17 00:00:00 2001 From: Aiken Harris Date: Tue, 30 Jul 2024 15:15:50 +0200 Subject: [PATCH 2/8] Start application processor --- sdk/xtdk/amd64/hltypes.h | 6 ++++++ sdk/xtdk/i686/hltypes.h | 6 ++++++ xtoskrnl/hl/x86/cpu.c | 33 +++++++++++++++++++++++++++++++++ xtoskrnl/includes/amd64/ari.h | 4 ++++ xtoskrnl/includes/i686/ari.h | 4 ++++ 5 files changed, 53 insertions(+) diff --git a/sdk/xtdk/amd64/hltypes.h b/sdk/xtdk/amd64/hltypes.h index 4c57ae2..92fd90f 100644 --- a/sdk/xtdk/amd64/hltypes.h +++ b/sdk/xtdk/amd64/hltypes.h @@ -51,6 +51,12 @@ #define APIC_DM_INIT 0x00000500 #define APIC_DM_STARTUP 0x00000600 #define APIC_DM_EXTINT 0x00000700 +#define APIC_DM_ASSERT 0x00004000 +#define APIC_DM_LEVEL 0x00008000 +#define APIC_DM_BROADCAST 0x00080000 + +/* APIC delivery status */ +#define APIC_DELIVERY_PENDING 0x00001000 /* APIC trigger modes */ #define APIC_TGM_EDGE 0 diff --git a/sdk/xtdk/i686/hltypes.h b/sdk/xtdk/i686/hltypes.h index 440976b..defdfc6 100644 --- a/sdk/xtdk/i686/hltypes.h +++ b/sdk/xtdk/i686/hltypes.h @@ -56,6 +56,12 @@ #define APIC_DM_INIT 0x00000500 #define APIC_DM_STARTUP 0x00000600 #define APIC_DM_EXTINT 0x00000700 +#define APIC_DM_ASSERT 0x00004000 +#define APIC_DM_LEVEL 0x00008000 +#define APIC_DM_BROADCAST 0x00080000 + +/* APIC delivery status */ +#define APIC_DELIVERY_PENDING 0x00001000 /* APIC trigger modes */ #define APIC_TGM_EDGE 0 diff --git a/xtoskrnl/hl/x86/cpu.c b/xtoskrnl/hl/x86/cpu.c index 65f321f..7aff72d 100644 --- a/xtoskrnl/hl/x86/cpu.c +++ b/xtoskrnl/hl/x86/cpu.c @@ -45,3 +45,36 @@ HlInitializeProcessor(VOID) /* Set the APIC running level */ HlSetRunLevel(KeGetCurrentProcessorBlock()->RunLevel); } + +XTAPI +XTSTATUS +HlStartProcessor(IN ULONG CpuId, + IN PHYSICAL_ADDRESS EntryPoint) +{ + ULONG Attempt; + + /* Wait until command register is clear */ + while((HlReadApicRegister(APIC_ICR0) & APIC_DELIVERY_PENDING) != 0); + + /* Trigger INIT IPI and wait for delivery bit to be cleared */ + HlpSendIpi(CpuId, APIC_DM_INIT | APIC_DM_LEVEL | APIC_DM_ASSERT); + while((HlReadApicRegister(APIC_ICR0) & APIC_DELIVERY_PENDING) != 0); + + /* Deassert INIT IPI to take CPU out of reset and wait for delivery bit to be cleared */ + HlpSendIpi(CpuId, APIC_DM_INIT | APIC_DM_LEVEL); + while((HlReadApicRegister(APIC_ICR0) & APIC_DELIVERY_PENDING) != 0); + + /* Two attempts to send STARTUP IPI */ + for(Attempt = 0; Attempt < 2; Attempt++) + { + /* Trigger STARTUP IPI and wait for delivery bit to be cleared */ + HlpSendIpi(CpuId, APIC_DM_STARTUP | (EntryPoint.LowPart >> 12)); + while((HlReadApicRegister(APIC_ICR0) & APIC_DELIVERY_PENDING) != 0); + } + + /* Memory barrier */ + ArMemoryBarrier(); + + /* Return success */ + return STATUS_SUCCESS; +} diff --git a/xtoskrnl/includes/amd64/ari.h b/xtoskrnl/includes/amd64/ari.h index 1b63daa..7e9a1b2 100644 --- a/xtoskrnl/includes/amd64/ari.h +++ b/xtoskrnl/includes/amd64/ari.h @@ -117,6 +117,10 @@ XTCDECL VOID ArSetInterruptFlag(VOID); +XTCDECL +VOID +ArStartApplicationProcessor(); + XTCDECL VOID ArStoreGlobalDescriptorTable(OUT PVOID Destination); diff --git a/xtoskrnl/includes/i686/ari.h b/xtoskrnl/includes/i686/ari.h index 377e7f3..5009b76 100644 --- a/xtoskrnl/includes/i686/ari.h +++ b/xtoskrnl/includes/i686/ari.h @@ -113,6 +113,10 @@ XTCDECL VOID ArSetInterruptFlag(VOID); +XTCDECL +VOID +ArStartApplicationProcessor(); + XTCDECL VOID ArStoreGlobalDescriptorTable(OUT PVOID Destination); -- 2.50.1 From 6fea2fa1e5e788ee3e653fd2dc1f0f1bc45dfe38 Mon Sep 17 00:00:00 2001 From: Aiken Harris Date: Tue, 30 Jul 2024 15:21:31 +0200 Subject: [PATCH 3/8] 2 attempts only --- xtoskrnl/hl/x86/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/xtoskrnl/hl/x86/cpu.c b/xtoskrnl/hl/x86/cpu.c index 7aff72d..b585ca6 100644 --- a/xtoskrnl/hl/x86/cpu.c +++ b/xtoskrnl/hl/x86/cpu.c @@ -51,7 +51,7 @@ XTSTATUS HlStartProcessor(IN ULONG CpuId, IN PHYSICAL_ADDRESS EntryPoint) { - ULONG Attempt; + UCHAR Attempt; /* Wait until command register is clear */ while((HlReadApicRegister(APIC_ICR0) & APIC_DELIVERY_PENDING) != 0); -- 2.50.1 From 8d3b4ff95a63a51eb9b63e7e002e9294669247d5 Mon Sep 17 00:00:00 2001 From: Aiken Harris Date: Wed, 31 Jul 2024 21:16:39 +0200 Subject: [PATCH 4/8] Start application processors --- xtoskrnl/hl/init.c | 3 ++ xtoskrnl/hl/x86/cpu.c | 80 +++++++++++++++++++++++++++++++++++++++++ xtoskrnl/includes/hli.h | 9 +++++ 3 files changed, 92 insertions(+) diff --git a/xtoskrnl/hl/init.c b/xtoskrnl/hl/init.c index 6119f9a..6d526c3 100644 --- a/xtoskrnl/hl/init.c +++ b/xtoskrnl/hl/init.c @@ -36,6 +36,9 @@ HlInitializeSystem(VOID) return Status; } + /* Start all application processors */ + HlStartAllProcessors(); + /* Return success */ return STATUS_SUCCESS; } diff --git a/xtoskrnl/hl/x86/cpu.c b/xtoskrnl/hl/x86/cpu.c index b585ca6..4bec2db 100644 --- a/xtoskrnl/hl/x86/cpu.c +++ b/xtoskrnl/hl/x86/cpu.c @@ -78,3 +78,83 @@ HlStartProcessor(IN ULONG CpuId, /* Return success */ return STATUS_SUCCESS; } + +XTAPI +XTSTATUS +HlStartAllProcessors(VOID) +{ + PHYSICAL_ADDRESS ApPhysicalAddress; + PVOID ApVirtualAddress; + BOOLEAN Interrupts; + XTSTATUS Status; + USHORT Cpu; + +/* Temp bootstrap code size */ +#define AP_SPINUP_PAGE_COUNT 5 + + /* Check if at least one AP is present */ + if(HlpSystemInfo.CpuCount > 1) + { + /* Allocate 5 pages for AP bootstrap code and ensure it is low memory */ + Status = MmAllocateHardwareMemory(AP_SPINUP_PAGE_COUNT, FALSE, &ApPhysicalAddress); + if(Status != STATUS_SUCCESS || ApPhysicalAddress.QuadPart > (0x100000 - AP_SPINUP_PAGE_COUNT * MM_PAGE_SIZE)) + { + /* Not enough free pages at low memory available, return error */ + return STATUS_INSUFFICIENT_RESOURCES; + } + + /* Map AP bootstrap code */ + Status = MmMapHardwareMemory(ApPhysicalAddress, AP_SPINUP_PAGE_COUNT, TRUE, &ApVirtualAddress); + if(Status != STATUS_SUCCESS) + { + /* Failed to map AP bootstrap code, return error */ + return STATUS_INSUFFICIENT_RESOURCES; + } + + /* Copy AP bootstrap code into low memory */ + RtlCopyMemory(ApVirtualAddress, &ArStartApplicationProcessor, AP_SPINUP_PAGE_COUNT * MM_PAGE_SIZE); + + /* Iterate over all CPUs and start them */ + for(Cpu = 0; Cpu < HlpSystemInfo.CpuCount; Cpu++) + { + /* Check if this CPU is the BSP */ + if(HlpSystemInfo.CpuInfo[Cpu].ApicId == HlpGetCpuApicId()) + { + /* This is the BSP, set proper flag and mark as started */ + HlpSystemInfo.CpuInfo[Cpu].Bsp = TRUE; + HlpSystemInfo.CpuInfo[Cpu].Started = TRUE; + + /* Continue with next CPU */ + continue; + } + + /* Temp debugging */ + DebugPrint(L"Starting CPU #%lu (ACPI ID: %u, APIC ID: %u)\n", Cpu, HlpSystemInfo.CpuInfo[Cpu].AcpiId, HlpSystemInfo.CpuInfo[Cpu].ApicId); + + /* Check if interrupts are enabled and disable them */ + Interrupts = ArInterruptsEnabled(); + ArClearInterruptFlag(); + + /* Start the AP */ + Status = HlStartProcessor(HlpSystemInfo.CpuInfo[Cpu].ApicId, ApPhysicalAddress); + if(Status == STATUS_SUCCESS) + { + /* Mark AP as started */ + HlpSystemInfo.CpuInfo[Cpu].Started = TRUE; + } + + /* Check if interrupts were originally enabled */ + if(Interrupts) + { + /* Re-enable interrupts */ + ArSetInterruptFlag(); + } + } + + /* Unmap AP bootstrap code */ + MmUnmapHardwareMemory(ApVirtualAddress, AP_SPINUP_PAGE_COUNT, TRUE); + } + + /* Return success */ + return STATUS_SUCCESS; +} diff --git a/xtoskrnl/includes/hli.h b/xtoskrnl/includes/hli.h index b32c9a3..bca7e06 100644 --- a/xtoskrnl/includes/hli.h +++ b/xtoskrnl/includes/hli.h @@ -82,6 +82,15 @@ XTFASTCALL VOID HlSetRunLevel(IN KRUNLEVEL RunLevel); +XTAPI +XTSTATUS +HlStartAllProcessors(VOID); + +XTAPI +XTSTATUS +HlStartProcessor(IN ULONG CpuId, + IN PHYSICAL_ADDRESS ApEntryPoint); + XTAPI VOID HlpCacheAcpiTable(IN PACPI_DESCRIPTION_HEADER AcpiTable); -- 2.50.1 From 5cff5b4c0ce0543a33fe78209e133b931bc02f4f Mon Sep 17 00:00:00 2001 From: Aiken Harris Date: Tue, 13 Aug 2024 16:12:52 +0200 Subject: [PATCH 5/8] ap bootstrap code in dedicated file --- xtoskrnl/CMakeLists.txt | 1 + xtoskrnl/ar/amd64/archsmp.S | 28 ++++++++++++++++++++++++++++ xtoskrnl/ar/amd64/archsup.S | 15 --------------- xtoskrnl/ar/i686/archsmp.S | 25 +++++++++++++++++++++++++ xtoskrnl/ar/i686/archsup.S | 12 ------------ 5 files changed, 54 insertions(+), 27 deletions(-) create mode 100644 xtoskrnl/ar/amd64/archsmp.S create mode 100644 xtoskrnl/ar/i686/archsmp.S diff --git a/xtoskrnl/CMakeLists.txt b/xtoskrnl/CMakeLists.txt index d6a2f57..26282a9 100644 --- a/xtoskrnl/CMakeLists.txt +++ b/xtoskrnl/CMakeLists.txt @@ -22,6 +22,7 @@ list(APPEND LIBXTOS_SOURCE # Specify list of kernel source code files list(APPEND XTOSKRNL_SOURCE + ${XTOSKRNL_SOURCE_DIR}/ar/${ARCH}/archsmp.S ${XTOSKRNL_SOURCE_DIR}/ar/${ARCH}/archsup.S ${XTOSKRNL_SOURCE_DIR}/ar/${ARCH}/cpufunc.c ${XTOSKRNL_SOURCE_DIR}/ar/${ARCH}/globals.c diff --git a/xtoskrnl/ar/amd64/archsmp.S b/xtoskrnl/ar/amd64/archsmp.S new file mode 100644 index 0000000..c71d7fc --- /dev/null +++ b/xtoskrnl/ar/amd64/archsmp.S @@ -0,0 +1,28 @@ +/** + * PROJECT: ExectOS + * COPYRIGHT: See COPYING.md in the top level directory + * FILE: xtoskrnl/ar/amd64/archsmp.S + * DESCRIPTION: AP bootstrap code for AMD64 architecture + * DEVELOPERS: Aiken Harris + */ + +#include + +.altmacro +.text + + +.global ArStartApplicationProcessor +ArStartApplicationProcessor: + /* 16-bit code (real mode) */ + .code16 + + cli + cld + hlt + + /* 32-bit code (protected mode) */ + .code32 + + /* 64-bit code (long mode) */ + .code64 diff --git a/xtoskrnl/ar/amd64/archsup.S b/xtoskrnl/ar/amd64/archsup.S index 3c530c4..1c18ab2 100644 --- a/xtoskrnl/ar/amd64/archsup.S +++ b/xtoskrnl/ar/amd64/archsup.S @@ -12,21 +12,6 @@ .text -.global ArStartApplicationProcessor -ArStartApplicationProcessor: - /* 16-bit code (real mode) */ - .code16 - - cli - cld - hlt - - /* 32-bit code (protected mode) */ - .code32 - - /* 64-bit code (long mode) */ - .code64 - /** * This macro creates a trap handler for the specified vector. * diff --git a/xtoskrnl/ar/i686/archsmp.S b/xtoskrnl/ar/i686/archsmp.S new file mode 100644 index 0000000..3f1f56f --- /dev/null +++ b/xtoskrnl/ar/i686/archsmp.S @@ -0,0 +1,25 @@ +/** + * PROJECT: ExectOS + * COPYRIGHT: See COPYING.md in the top level directory + * FILE: xtoskrnl/ar/i686/archsmp.S + * DESCRIPTION: AP bootstrap code for i686 architecture + * DEVELOPERS: Aiken Harris + */ + +#include + +.altmacro +.text + + +.global ArStartApplicationProcessor +ArStartApplicationProcessor: + /* 16-bit code (real mode) */ + .code16 + + cli + cld + hlt + + /* 32-bit code (protected mode) */ + .code32 diff --git a/xtoskrnl/ar/i686/archsup.S b/xtoskrnl/ar/i686/archsup.S index dec4396..e80ac42 100644 --- a/xtoskrnl/ar/i686/archsup.S +++ b/xtoskrnl/ar/i686/archsup.S @@ -12,18 +12,6 @@ .text -.global _ArStartApplicationProcessor -_ArStartApplicationProcessor: - /* 16-bit code (real mode) */ - .code16 - - cli - cld - hlt - - /* 32-bit code (protected mode) */ - .code32 - /** * This macro creates a trap handler for the specified vector. * -- 2.50.1 From bcb99b2f5e03869f4edee2aecdf2643b4f3e049c Mon Sep 17 00:00:00 2001 From: Aiken Harris Date: Tue, 13 Aug 2024 19:20:45 +0200 Subject: [PATCH 6/8] increase ram, fix debug port --- sdk/firmware/bochsrc_amd64.cfg | 4 ++-- sdk/firmware/bochsrc_i686.cfg | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/sdk/firmware/bochsrc_amd64.cfg b/sdk/firmware/bochsrc_amd64.cfg index 03fea9c..4701a1d 100644 --- a/sdk/firmware/bochsrc_amd64.cfg +++ b/sdk/firmware/bochsrc_amd64.cfg @@ -2,7 +2,7 @@ plugin_ctrl: usb_xhci=false, serial=true, e1000=false, extfpuirq=true, parallel=true, usb_uhci=false, biosdev=true, unmapped=true, gameport=true, ne2k=false, speaker=true, iodebug=false, pcipnic=false, usb_ohci=false config_interface: textconfig display_library: x -memory: host=64, guest=64 +memory: host=64, guest=2048 romimage: file="../sdk/firmware/ovmf_pure_amd64.fd", address=0x00000000, options=none vgaromimage: file="../sdk/firmware/vgabios.bin" boot: floppy @@ -45,7 +45,7 @@ error: action=report panic: action=ask keyboard: type=mf, serial_delay=250, paste_delay=100000, user_shortcut=none mouse: type=ps2, enabled=false, toggle=ctrl+mbutton -com1: enabled=true, mode=null +com1: enabled=true, mode=file, dev=dbgport.txt com2: enabled=false com3: enabled=false com4: enabled=false diff --git a/sdk/firmware/bochsrc_i686.cfg b/sdk/firmware/bochsrc_i686.cfg index 49ea10f..2bf2cdf 100644 --- a/sdk/firmware/bochsrc_i686.cfg +++ b/sdk/firmware/bochsrc_i686.cfg @@ -2,7 +2,7 @@ plugin_ctrl: usb_xhci=false, serial=true, e1000=false, extfpuirq=true, parallel=true, usb_uhci=false, biosdev=true, unmapped=true, gameport=true, ne2k=false, speaker=true, iodebug=false, pcipnic=false, usb_ohci=false config_interface: textconfig display_library: x -memory: host=64, guest=64 +memory: host=64, guest=2048 romimage: file="../sdk/firmware/ovmf_pure_i686.fd", address=0x00000000, options=none vgaromimage: file="../sdk/firmware/vgabios.bin" boot: floppy @@ -45,7 +45,7 @@ error: action=report panic: action=ask keyboard: type=mf, serial_delay=250, paste_delay=100000, user_shortcut=none mouse: type=ps2, enabled=false, toggle=ctrl+mbutton -com1: enabled=true, mode=null +com1: enabled=true, mode=file, dev=dbgport.txt com2: enabled=false com3: enabled=false com4: enabled=false -- 2.50.1 From d7a1b01b6363e5a314c83137300e7d8772157077 Mon Sep 17 00:00:00 2001 From: Aiken Harris Date: Tue, 13 Aug 2024 19:37:48 +0200 Subject: [PATCH 7/8] enable smp --- sdk/firmware/bochsrc_amd64.cfg | 2 +- sdk/firmware/bochsrc_i686.cfg | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/sdk/firmware/bochsrc_amd64.cfg b/sdk/firmware/bochsrc_amd64.cfg index 4701a1d..a857ce7 100644 --- a/sdk/firmware/bochsrc_amd64.cfg +++ b/sdk/firmware/bochsrc_amd64.cfg @@ -27,7 +27,7 @@ optramimage3: file=none optramimage4: file=none pci: enabled=1, chipset=i440fx, slot1=cirrus, slot2=none, slot3=none, slot4=none, slot5=none vga: extension=cirrus, update_freq=5, realtime=1, ddc=builtin -cpu: count=1:1:1, ips=400000000, quantum=16, model=bx_generic, reset_on_triple_fault=0, cpuid_limit_winnt=0, ignore_bad_msrs=1, mwait_is_nop=0 +cpu: count=2:2:1, ips=400000000, quantum=16, model=bx_generic, reset_on_triple_fault=0, cpuid_limit_winnt=0, ignore_bad_msrs=1, mwait_is_nop=0 cpuid: level=6, stepping=3, model=3, family=6, vendor_string="GenuineIntel", brand_string=" Intel(R) Pentium(R) 4 CPU " cpuid: mmx=true, apic=xapic, simd=sse4_2, sse4a=false, misaligned_sse=false, sep=true cpuid: movbe=false, adx=false, aes=false, sha=false, xsave=false, xsaveopt=false, x86_64=true diff --git a/sdk/firmware/bochsrc_i686.cfg b/sdk/firmware/bochsrc_i686.cfg index 2bf2cdf..fd5cbe2 100644 --- a/sdk/firmware/bochsrc_i686.cfg +++ b/sdk/firmware/bochsrc_i686.cfg @@ -27,7 +27,7 @@ optramimage3: file=none optramimage4: file=none pci: enabled=1, chipset=i440fx, slot1=cirrus, slot2=none, slot3=none, slot4=none, slot5=none vga: extension=cirrus, update_freq=5, realtime=1, ddc=builtin -cpu: count=1:1:1, ips=400000000, quantum=16, model=bx_generic, reset_on_triple_fault=0, cpuid_limit_winnt=0, ignore_bad_msrs=1, mwait_is_nop=0 +cpu: count=2:2:1, ips=400000000, quantum=16, model=bx_generic, reset_on_triple_fault=0, cpuid_limit_winnt=0, ignore_bad_msrs=1, mwait_is_nop=0 cpuid: level=6, stepping=3, model=3, family=6, vendor_string="GenuineIntel", brand_string=" Intel(R) Pentium(R) 4 CPU " cpuid: mmx=true, apic=xapic, simd=sse4_2, sse4a=false, misaligned_sse=false, sep=true cpuid: movbe=false, adx=false, aes=false, sha=false, xsave=false, xsaveopt=false, x86_64=true -- 2.50.1 From 5670398077a57dfc02f63e589055c5f167ab2523 Mon Sep 17 00:00:00 2001 From: Aiken Harris Date: Wed, 14 Aug 2024 13:03:05 +0200 Subject: [PATCH 8/8] update AP bootstrap code --- xtoskrnl/ar/amd64/archsmp.S | 59 ++++++++++++++++++++++++++++++++++++- xtoskrnl/hl/x86/cpu.c | 5 ++++ 2 files changed, 63 insertions(+), 1 deletion(-) diff --git a/xtoskrnl/ar/amd64/archsmp.S b/xtoskrnl/ar/amd64/archsmp.S index c71d7fc..ac50bf1 100644 --- a/xtoskrnl/ar/amd64/archsmp.S +++ b/xtoskrnl/ar/amd64/archsmp.S @@ -12,17 +12,74 @@ .text +.global ArBootstrapPageMap + .global ArStartApplicationProcessor ArStartApplicationProcessor: /* 16-bit code (real mode) */ .code16 + /* Turn off interrupts and clear direction flag */ cli cld - hlt + + /* Load temporary GDT */ + lgdt (ArpApTemporaryGdtSize - ArStartApplicationProcessor + 0x1000) + + /* Enable bit 0 in CR0 to enable Protected Mode */ + movl %cr0, %eax + orl $0x1, %eax + movl %eax, %cr0 + + /* Long jump into 32bits */ + ljmpl $0x8, $(ApplicationProcessor32 - ArStartApplicationProcessor + 0x1000) /* 32-bit code (protected mode) */ .code32 +ApplicationProcessor32: + + /* Fix segment registers */ + mov $0x10, %ax + mov %ax, %ds + mov %ax, %es + mov %ax, %fs + mov %ax, %gs + mov %ax, %ss + + /* Enable LM and NX in the EFER. */ + mov $0xC0000080, %ecx + rdmsr + or $0x900, %eax + wrmsr + + /* Enable PAE and PSE */ + mov %cr4, %eax + or $0x668, %eax + mov %eax, %cr4 + + /* Install page map in CR3 */ + mov (ArBootstrapPageMap - ArStartApplicationProcessor + 0x1000), %eax + mov %eax, %cr3 + + /* Enable paging */ + mov %cr0, %eax + or $0x80010000, %eax + mov %eax, %cr0 + + /* Long jump into 64bits */ + ljmpl $0x8, $(ApplicationProcessor64 - ArStartApplicationProcessor + 0x1000) /* 64-bit code (long mode) */ .code64 +ApplicationProcessor64: + + /* HALT CPU in long mode */ + hlt + +.align 8 +ArpApTemporaryGdtDesc: .quad 0x0000000000000000, 0x00CF9A000000FFFF, 0x00CF92000000FFFF, 0x00AF9A000000FFFF +ArpApTemporaryGdtSize: .short ArpApTemporaryGdtSize - ArpApTemporaryGdtDesc - 1 +ArpApTemporaryGdtBase: .long ArpApTemporaryGdtDesc - ArStartApplicationProcessor + 0x1000 +ArBootstrapPageMap: .quad 0x0000000000000000 + +ArStartApplicationProcessorEnd: diff --git a/xtoskrnl/hl/x86/cpu.c b/xtoskrnl/hl/x86/cpu.c index 4bec2db..986f779 100644 --- a/xtoskrnl/hl/x86/cpu.c +++ b/xtoskrnl/hl/x86/cpu.c @@ -79,6 +79,8 @@ HlStartProcessor(IN ULONG CpuId, return STATUS_SUCCESS; } +extern ULONG_PTR ArBootstrapPageMap; + XTAPI XTSTATUS HlStartAllProcessors(VOID) @@ -95,6 +97,9 @@ HlStartAllProcessors(VOID) /* Check if at least one AP is present */ if(HlpSystemInfo.CpuCount > 1) { + /* Save page map address in the bootstrap code */ + ArBootstrapPageMap = ArReadControlRegister(3); + /* Allocate 5 pages for AP bootstrap code and ensure it is low memory */ Status = MmAllocateHardwareMemory(AP_SPINUP_PAGE_COUNT, FALSE, &ApPhysicalAddress); if(Status != STATUS_SUCCESS || ApPhysicalAddress.QuadPart > (0x100000 - AP_SPINUP_PAGE_COUNT * MM_PAGE_SIZE)) -- 2.50.1