From a01ccff6dc527cca43aa65f6de2b2b141f9217b0 Mon Sep 17 00:00:00 2001 From: PerikiyoXD Date: Thu, 23 Nov 2023 17:02:30 +0100 Subject: [PATCH 1/3] POSIX compliant stream redirection Reviewed-on: https://git.codingworkshop.eu.org/xt-sys/exectos/pulls/1 Reviewed-by: Rafal Kupiec Co-authored-by: PerikiyoXD Co-committed-by: PerikiyoXD --- sdk/cmake/qemu.cmake | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/sdk/cmake/qemu.cmake b/sdk/cmake/qemu.cmake index 1bb638f..c70f67b 100644 --- a/sdk/cmake/qemu.cmake +++ b/sdk/cmake/qemu.cmake @@ -8,14 +8,14 @@ endif() # This target creates a disk image add_custom_target(diskimg DEPENDS install - COMMAND sh -c "dd if=/dev/zero of=${EXECTOS_BINARY_DIR}/output/disk.img bs=512 count=${PROJECT_DISK_IMAGE_BLOCKS} &>/dev/null" + COMMAND sh -c "dd if=/dev/zero of=${EXECTOS_BINARY_DIR}/output/disk.img bs=512 count=${PROJECT_DISK_IMAGE_BLOCKS} 2> /dev/null 1> /dev/null" COMMAND parted ${EXECTOS_BINARY_DIR}/output/disk.img -s -a minimal mklabel gpt COMMAND parted ${EXECTOS_BINARY_DIR}/output/disk.img -s -a minimal mkpart EFI FAT32 2048s ${PROJECT_PART_IMAGE_BLOCKS}s COMMAND parted ${EXECTOS_BINARY_DIR}/output/disk.img -s -a minimal toggle 1 boot - COMMAND sh -c "dd if=/dev/zero of=${EXECTOS_BINARY_DIR}/output/part.img bs=512 count=${PROJECT_PART_IMAGE_BLOCKS} &>/dev/null" + COMMAND sh -c "dd if=/dev/zero of=${EXECTOS_BINARY_DIR}/output/part.img bs=512 count=${PROJECT_PART_IMAGE_BLOCKS} 2> /dev/null 1> /dev/null" COMMAND mformat -i ${EXECTOS_BINARY_DIR}/output/part.img -h32 -t32 -n64 -L32 COMMAND sh -c "mcopy -s -i ${EXECTOS_BINARY_DIR}/output/part.img ${EXECTOS_BINARY_DIR}/output/binaries/* ::" - COMMAND sh -c "dd if=${EXECTOS_BINARY_DIR}/output/part.img of=${EXECTOS_BINARY_DIR}/output/disk.img bs=512 count=${PROJECT_PART_IMAGE_BLOCKS} seek=2048 conv=notrunc &>/dev/null" + COMMAND sh -c "dd if=${EXECTOS_BINARY_DIR}/output/part.img of=${EXECTOS_BINARY_DIR}/output/disk.img bs=512 count=${PROJECT_PART_IMAGE_BLOCKS} seek=2048 conv=notrunc 2> /dev/null 1> /dev/null" COMMAND rm ${EXECTOS_BINARY_DIR}/output/part.img VERBATIM) -- 2.45.1 From a270c08dcf9bd03a2dbe6a665bab5f52094af7e9 Mon Sep 17 00:00:00 2001 From: PerikiyoXD Date: Thu, 23 Nov 2023 23:22:54 +0100 Subject: [PATCH 2/3] feat: Add CPU vendor and features identification Add functionality to identify the CPU vendor and features using the CPUID instruction. The CPU vendor information is stored in the Processor Control Block (PRCB), including the vendor name and a corresponding enumeration. CPU features are also retrieved and stored in the PRCB. Previously, the CPU vendor was not properly stored in the PRCB, caused by a missing type cast. Using Rtl functions to copy the CPU vendor name to the PRCB. Details: - Introduced functions `ArpSetCpuVendor` and `ArpSetCpuFeatures` to set CPU vendor and features, respectively. - Modified `ArpIdentifyProcessor` to call the new functions for vendor and features identification. - Added `CPU_FEATURES` structure to `KPROCESSOR_CONTROL_BLOCK` structure to store CPU features. Tests: - Tested x86_64 on QEMU. Verified that the CPU vendor and features are correctly identified and stored in the PRCB. --- sdk/xtdk/amd64/artypes.h | 89 +++++++++++++++++++++++++++++++-- sdk/xtdk/amd64/ketypes.h | 1 + sdk/xtdk/i686/artypes.h | 84 +++++++++++++++++++++++++++++-- sdk/xtdk/i686/ketypes.h | 1 + xtoskrnl/ar/amd64/procsup.c | 95 +++++++++++++++++++++++++++-------- xtoskrnl/ar/i686/procsup.c | 96 +++++++++++++++++++++++++++++------- xtoskrnl/includes/amd64/ar.h | 8 +++ xtoskrnl/includes/i686/ar.h | 8 +++ 8 files changed, 337 insertions(+), 45 deletions(-) diff --git a/sdk/xtdk/amd64/artypes.h b/sdk/xtdk/amd64/artypes.h index e2ad86b..e3607b0 100644 --- a/sdk/xtdk/amd64/artypes.h +++ b/sdk/xtdk/amd64/artypes.h @@ -110,11 +110,16 @@ #define X86_EFLAGS_VIP_MASK 0x00100000 #define X86_EFLAGS_ID_MASK 0x00200000 +/* CPUID vendor names */ +#define CPUID_VENDOR_NAME_AMD "AuthenticAMD" +#define CPUID_VENDOR_NAME_INTEL "GenuineIntel" + /* CPU vendor enumeration list */ typedef enum _CPU_VENDOR { - CPU_VENDOR_AMD = 0x68747541, - CPU_VENDOR_INTEL = 0x756e6547, + CPU_VENDOR_INVALID, + CPU_VENDOR_AMD, + CPU_VENDOR_INTEL, CPU_VENDOR_UNKNOWN = 0xFFFFFFFF } CPU_VENDOR, *PCPU_VENDOR; @@ -144,7 +149,7 @@ typedef enum _CPUID_FEATURES CPUID_FEATURES_ECX_X2APIC = 1 << 21, CPUID_FEATURES_ECX_MOVBE = 1 << 22, CPUID_FEATURES_ECX_POPCNT = 1 << 23, - CPUID_FEATURES_ECX_TSC = 1 << 24, + CPUID_FEATURES_ECX_TSC_DEADLINE = 1 << 24, CPUID_FEATURES_ECX_AES = 1 << 25, CPUID_FEATURES_ECX_XSAVE = 1 << 26, CPUID_FEATURES_ECX_OSXSAVE = 1 << 27, @@ -184,6 +189,84 @@ typedef enum _CPUID_FEATURES CPUID_FEATURES_EDX_PBE = 1 << 31 } CPUID_FEATURES, *PCPUID_FEATURES; +/* CPU features, as reported by CPUID instruction */ +typedef struct _CPU_FEATURES { + union { + struct { + BOOLEAN SSE3 : 1; + BOOLEAN PCLMUL : 1; + BOOLEAN DTES64 : 1; + BOOLEAN MONITOR : 1; + BOOLEAN DS_CPL : 1; + BOOLEAN VMX : 1; + BOOLEAN SMX : 1; + BOOLEAN EST : 1; + BOOLEAN TM2 : 1; + BOOLEAN SSSE3 : 1; + BOOLEAN CID : 1; + BOOLEAN SDBG : 1; + BOOLEAN FMA : 1; + BOOLEAN CX16 : 1; + BOOLEAN XTPR : 1; + BOOLEAN PDCM : 1; + BOOLEAN Reserved1 : 1; // Bit 16 is reserved + BOOLEAN PCID : 1; + BOOLEAN DCA : 1; + BOOLEAN SSE4_1 : 1; + BOOLEAN SSE4_2 : 1; + BOOLEAN X2APIC : 1; + BOOLEAN MOVBE : 1; + BOOLEAN POPCNT : 1; + BOOLEAN TSC_DEADLINE : 1; + BOOLEAN AES : 1; + BOOLEAN XSAVE : 1; + BOOLEAN OSXSAVE : 1; + BOOLEAN AVX : 1; + BOOLEAN F16C : 1; + BOOLEAN RDRAND : 1; + BOOLEAN HYPERVISOR : 1; + }; + UINT32 ExtendedFeatures; + }; + union { + struct { + BOOLEAN FPU : 1; + BOOLEAN VME : 1; + BOOLEAN DE : 1; + BOOLEAN PSE : 1; + BOOLEAN TSC : 1; + BOOLEAN MSR : 1; + BOOLEAN PAE : 1; + BOOLEAN MCE : 1; + BOOLEAN CX8 : 1; + BOOLEAN APIC : 1; + BOOLEAN Reserved2 : 1; // Bit 10 is reserved + BOOLEAN SEP : 1; + BOOLEAN MTRR : 1; + BOOLEAN PGE : 1; + BOOLEAN MCA : 1; + BOOLEAN CMOV : 1; + BOOLEAN PAT : 1; + BOOLEAN PSE36 : 1; + BOOLEAN PSN : 1; + BOOLEAN CLFLUSH : 1; + BOOLEAN Reserved3 : 1; // Bit 20 is reserved + BOOLEAN DS : 1; + BOOLEAN ACPI : 1; + BOOLEAN MMX : 1; + BOOLEAN FXSR : 1; + BOOLEAN SSE : 1; + BOOLEAN SSE2 : 1; + BOOLEAN SS : 1; + BOOLEAN HTT : 1; + BOOLEAN TM : 1; + BOOLEAN Reserved4 : 1; // Bit 30 is reserved + BOOLEAN PBE : 1; + }; + UINT64 Features; + }; +} CPU_FEATURES, *PCPU_FEATURES; + /* CPUID requests */ typedef enum _CPUID_REQUESTS { diff --git a/sdk/xtdk/amd64/ketypes.h b/sdk/xtdk/amd64/ketypes.h index ee5bcc3..8c3e8b2 100644 --- a/sdk/xtdk/amd64/ketypes.h +++ b/sdk/xtdk/amd64/ketypes.h @@ -514,6 +514,7 @@ typedef struct _KPROCESSOR_CONTROL_BLOCK ULONG64 RspBase; ULONG_PTR SetMember; CPU_IDENTIFICATION CpuId; + CPU_FEATURES CpuFeatures; KPROCESSOR_STATE ProcessorState; KDPC_DATA DpcData[2]; PVOID DpcStack; diff --git a/sdk/xtdk/i686/artypes.h b/sdk/xtdk/i686/artypes.h index 5dab6e1..1c8cd77 100644 --- a/sdk/xtdk/i686/artypes.h +++ b/sdk/xtdk/i686/artypes.h @@ -61,11 +61,16 @@ #define SEGMENT_FS 0x64 #define SEGMENT_GS 0x65 +/* CPUID vendor names */ +#define CPUID_VENDOR_NAME_AMD "AuthenticAMD" +#define CPUID_VENDOR_NAME_INTEL "GenuineIntel" + /* CPU vendor enumeration list */ typedef enum _CPU_VENDOR { - CPU_VENDOR_AMD = 0x68747541, - CPU_VENDOR_INTEL = 0x756e6547, + CPU_VENDOR_INVALID, + CPU_VENDOR_AMD, + CPU_VENDOR_INTEL, CPU_VENDOR_UNKNOWN = 0xFFFFFFFF } CPU_VENDOR, *PCPU_VENDOR; @@ -95,7 +100,7 @@ typedef enum _CPUID_FEATURES CPUID_FEATURES_ECX_X2APIC = 1 << 21, CPUID_FEATURES_ECX_MOVBE = 1 << 22, CPUID_FEATURES_ECX_POPCNT = 1 << 23, - CPUID_FEATURES_ECX_TSC = 1 << 24, + CPUID_FEATURES_ECX_TSC_DEADLINE = 1 << 24, CPUID_FEATURES_ECX_AES = 1 << 25, CPUID_FEATURES_ECX_XSAVE = 1 << 26, CPUID_FEATURES_ECX_OSXSAVE = 1 << 27, @@ -135,6 +140,79 @@ typedef enum _CPUID_FEATURES CPUID_FEATURES_EDX_PBE = 1 << 31 } CPUID_FEATURES, *PCPUID_FEATURES; +/* CPU features, as reported by CPUID instruction */ +typedef struct _CPU_FEATURES { + union { + struct { + BOOLEAN SSE3 : 1; + BOOLEAN PCLMUL : 1; + BOOLEAN DTES64 : 1; + BOOLEAN MONITOR : 1; + BOOLEAN DS_CPL : 1; + BOOLEAN VMX : 1; + BOOLEAN SMX : 1; + BOOLEAN EST : 1; + BOOLEAN TM2 : 1; + BOOLEAN SSSE3 : 1; + BOOLEAN CID : 1; + BOOLEAN SDBG : 1; + BOOLEAN FMA : 1; + BOOLEAN CX16 : 1; + BOOLEAN XTPR : 1; + BOOLEAN PDCM : 1; + BOOLEAN Reserved1 : 1; // Bit 16 is reserved + BOOLEAN PCID : 1; + BOOLEAN DCA : 1; + BOOLEAN SSE4_1 : 1; + BOOLEAN SSE4_2 : 1; + BOOLEAN X2APIC : 1; + BOOLEAN MOVBE : 1; + BOOLEAN POPCNT : 1; + BOOLEAN TSC_DEADLINE : 1; + BOOLEAN AES : 1; + BOOLEAN XSAVE : 1; + BOOLEAN OSXSAVE : 1; + BOOLEAN AVX : 1; + BOOLEAN F16C : 1; + BOOLEAN RDRAND : 1; + BOOLEAN HYPERVISOR : 1; + BOOLEAN FPU : 1; + BOOLEAN VME : 1; + BOOLEAN DE : 1; + BOOLEAN PSE : 1; + BOOLEAN TSC : 1; + BOOLEAN MSR : 1; + BOOLEAN PAE : 1; + BOOLEAN MCE : 1; + BOOLEAN CX8 : 1; + BOOLEAN APIC : 1; + BOOLEAN Reserved2 : 1; // Bit 10 is reserved + BOOLEAN SEP : 1; + BOOLEAN MTRR : 1; + BOOLEAN PGE : 1; + BOOLEAN MCA : 1; + BOOLEAN CMOV : 1; + BOOLEAN PAT : 1; + BOOLEAN PSE36 : 1; + BOOLEAN PSN : 1; + BOOLEAN CLFLUSH : 1; + BOOLEAN Reserved3 : 1; // Bit 20 is reserved + BOOLEAN DS : 1; + BOOLEAN ACPI : 1; + BOOLEAN MMX : 1; + BOOLEAN FXSR : 1; + BOOLEAN SSE : 1; + BOOLEAN SSE2 : 1; + BOOLEAN SS : 1; + BOOLEAN HTT : 1; + BOOLEAN TM : 1; + BOOLEAN Reserved4 : 1; // Bit 30 is reserved + BOOLEAN PBE : 1; + }; + UINT64 AsUINT64; + }; +} CPU_FEATURES, *PCPU_FEATURES; + /* CPUID requests */ typedef enum _CPUID_REQUESTS { diff --git a/sdk/xtdk/i686/ketypes.h b/sdk/xtdk/i686/ketypes.h index 7069eb5..30826a5 100644 --- a/sdk/xtdk/i686/ketypes.h +++ b/sdk/xtdk/i686/ketypes.h @@ -454,6 +454,7 @@ typedef struct _KPROCESSOR_CONTROL_BLOCK UCHAR Number; ULONG_PTR SetMember; CPU_IDENTIFICATION CpuId; + CPU_FEATURES CpuFeatures; KPROCESSOR_STATE ProcessorState; ULONG_PTR MultiThreadProcessorSet; KDPC_DATA DpcData[2]; diff --git a/xtoskrnl/ar/amd64/procsup.c b/xtoskrnl/ar/amd64/procsup.c index 5c165ec..f4d880e 100644 --- a/xtoskrnl/ar/amd64/procsup.c +++ b/xtoskrnl/ar/amd64/procsup.c @@ -108,8 +108,7 @@ ArSetGdtEntryBase(IN PKGDTENTRY Gdt, } /** - * Identifies processor type (vendor, model, stepping) as well as looks for available CPU features and stores them - * in Processor Control Block (PRCB). + * Sets the CPU vendor information in the processor control block (PRCB). * * @return This routine does not return any value. * @@ -117,29 +116,62 @@ ArSetGdtEntryBase(IN PKGDTENTRY Gdt, */ XTAPI VOID -ArpIdentifyProcessor(VOID) +ArpSetCpuVendor() { PKPROCESSOR_CONTROL_BLOCK Prcb; CPUID_REGISTERS CpuRegisters; - CPUID_SIGNATURE CpuSignature; - - /* Not fully implemented yet */ - UNIMPLEMENTED; + UINT32 VendorNameBytes[3]; /* Get current processor control block */ Prcb = KeGetCurrentProcessorControlBlock(); - /* Get CPU vendor by issueing CPUID instruction */ + /* Get CPU vendor by issuing CPUID instruction */ RtlZeroMemory(&CpuRegisters, sizeof(CPUID_REGISTERS)); CpuRegisters.Leaf = CPUID_GET_VENDOR_STRING; ArCpuId(&CpuRegisters); - /* Store CPU vendor in processor control block */ - Prcb->CpuId.Vendor = CpuRegisters.Ebx; - Prcb->CpuId.VendorName[0] = CpuRegisters.Ebx; - Prcb->CpuId.VendorName[4] = CpuRegisters.Edx; - Prcb->CpuId.VendorName[8] = CpuRegisters.Ecx; - Prcb->CpuId.VendorName[12] = '\0'; + /* Order CPU vendor name bytes */ + VendorNameBytes[0] = CpuRegisters.Ebx; + VendorNameBytes[1] = CpuRegisters.Edx; + VendorNameBytes[2] = CpuRegisters.Ecx; + + /* Copy CPU vendor name to processor control block */ + RtlZeroMemory(&Prcb->CpuId.VendorName[0], 13); + RtlCopyMemory(&Prcb->CpuId.VendorName[0], &VendorNameBytes[0], 12); + + /* Set CPU vendor on processor control block by comparing known vendor names */ + if (RtlCompareMemory(&Prcb->CpuId.VendorName[0], CPUID_VENDOR_NAME_AMD, 12) == 12) + { + Prcb->CpuId.Vendor = CPU_VENDOR_AMD; + } + else if (RtlCompareMemory(&Prcb->CpuId.VendorName[0], CPUID_VENDOR_NAME_INTEL, 12) == 12) + { + Prcb->CpuId.Vendor = CPU_VENDOR_INTEL; + } + else + { + Prcb->CpuId.Vendor = CPU_VENDOR_UNKNOWN; + } +} + +/** + * Sets the CPU features information in the processor control block (PRCB). + * + * @return This routine does not return any value. + * + * @since XT 1.0 + */ +XTAPI +VOID +ArpSetCpuFeatures(VOID) +{ + PKPROCESSOR_CONTROL_BLOCK Prcb; + CPUID_REGISTERS CpuRegisters; + CPUID_SIGNATURE CpuSignature; + UINT32 FeatureArray[2]; + + /* Get current processor control block */ + Prcb = KeGetCurrentProcessorControlBlock(); /* Get CPU features */ RtlZeroMemory(&CpuRegisters, sizeof(CPUID_REGISTERS)); @@ -153,24 +185,25 @@ ArpIdentifyProcessor(VOID) Prcb->CpuId.Stepping = CpuSignature.Stepping; /* CPU vendor specific quirks */ - if(Prcb->CpuId.Vendor == CPU_VENDOR_AMD) + if (Prcb->CpuId.Vendor == CPU_VENDOR_AMD) { /* AMD CPU */ Prcb->CpuId.Family = Prcb->CpuId.Family + CpuSignature.ExtendedFamily; - if(Prcb->CpuId.Model == 0xF) + + if (Prcb->CpuId.Model == 0xF) { Prcb->CpuId.Model = Prcb->CpuId.Model + (CpuSignature.ExtendedModel << 4); } } - else if(Prcb->CpuId.Vendor == CPU_VENDOR_INTEL) + else if (Prcb->CpuId.Vendor == CPU_VENDOR_INTEL) { /* Intel CPU */ - if(Prcb->CpuId.Family == 0xF) + if (Prcb->CpuId.Family == 0xF) { Prcb->CpuId.Family = Prcb->CpuId.Family + CpuSignature.ExtendedFamily; } - if((Prcb->CpuId.Family == 0xF) || (Prcb->CpuId.Family == 0x6)) + if ((Prcb->CpuId.Family == 0xF) || (Prcb->CpuId.Family == 0x6)) { Prcb->CpuId.Model = Prcb->CpuId.Model + (CpuSignature.ExtendedModel << 4); } @@ -181,7 +214,29 @@ ArpIdentifyProcessor(VOID) Prcb->CpuId.Vendor = CPU_VENDOR_UNKNOWN; } - /* TODO: Store a list of CPU features in processor control block */ + /* Store CPU features in processor control block */ + FeatureArray[0] = CpuRegisters.Edx; + FeatureArray[1] = CpuRegisters.Ecx; + RtlCopyMemory(&Prcb->CpuFeatures, &FeatureArray[0], sizeof(UINT64)); +} + +/** + * Identifies processor type (vendor, model, stepping) as well as looks for available CPU features and stores them + * in Processor Control Block (PRCB). + * + * @return This routine does not return any value. + * + * @since XT 1.0 + */ +XTAPI +VOID +ArpIdentifyProcessor(VOID) +{ + /* Set CPU vendor */ + ArpSetCpuVendor(); + + /* Set CPU features */ + ArpSetCpuFeatures(); } /** diff --git a/xtoskrnl/ar/i686/procsup.c b/xtoskrnl/ar/i686/procsup.c index 77d258e..5ed9cd1 100644 --- a/xtoskrnl/ar/i686/procsup.c +++ b/xtoskrnl/ar/i686/procsup.c @@ -105,8 +105,7 @@ ArSetGdtEntryBase(IN PKGDTENTRY Gdt, } /** - * Identifies processor type (vendor, model, stepping) as well as looks for available CPU features and stores them - * in Processor Control Block (PRCB). + * Sets the CPU vendor information in the processor control block (PRCB). * * @return This routine does not return any value. * @@ -114,14 +113,11 @@ ArSetGdtEntryBase(IN PKGDTENTRY Gdt, */ XTAPI VOID -ArpIdentifyProcessor(VOID) +ArpSetCpuVendor() { PKPROCESSOR_CONTROL_BLOCK Prcb; CPUID_REGISTERS CpuRegisters; - CPUID_SIGNATURE CpuSignature; - - /* Not fully implemented yet */ - UNIMPLEMENTED; + UINT32 VendorNameBytes[3]; /* Get current processor control block */ Prcb = KeGetCurrentProcessorControlBlock(); @@ -131,12 +127,48 @@ ArpIdentifyProcessor(VOID) CpuRegisters.Leaf = CPUID_GET_VENDOR_STRING; ArCpuId(&CpuRegisters); - /* Store CPU vendor in processor control block */ - Prcb->CpuId.Vendor = CpuRegisters.Ebx; - Prcb->CpuId.VendorName[0] = CpuRegisters.Ebx; - Prcb->CpuId.VendorName[4] = CpuRegisters.Edx; - Prcb->CpuId.VendorName[8] = CpuRegisters.Ecx; - Prcb->CpuId.VendorName[12] = '\0'; + /* Fix CPU vendor name bytes order */ + VendorNameBytes[0] = CpuRegisters.Ebx; + VendorNameBytes[1] = CpuRegisters.Edx; + VendorNameBytes[2] = CpuRegisters.Ecx; + + /* Copy CPU vendor name to processor control block */ + RtlZeroMemory(&Prcb->CpuId.VendorName[0], 13); + RtlCopyMemory(&Prcb->CpuId.VendorName[0], &VendorNameBytes[0], 12); + + /* Set CPU vendor on processor control block by comparing known vendor names */ + if (RtlCompareMemory(&Prcb->CpuId.VendorName[0], CPUID_VENDOR_NAME_AMD, 12) == 12) + { + Prcb->CpuId.Vendor = CPU_VENDOR_AMD; + } + else if (RtlCompareMemory(&Prcb->CpuId.VendorName[0], CPUID_VENDOR_NAME_INTEL, 12) == 12) + { + Prcb->CpuId.Vendor = CPU_VENDOR_INTEL; + } + else + { + Prcb->CpuId.Vendor = CPU_VENDOR_UNKNOWN; + } +} + +/** + * Sets the CPU features information in the processor control block (PRCB). + * + * @return This routine does not return any value. + * + * @since XT 1.0 + */ +XTAPI +VOID +ArpSetCpuFeatures(VOID) +{ + PKPROCESSOR_CONTROL_BLOCK Prcb; + CPUID_REGISTERS CpuRegisters; + CPUID_SIGNATURE CpuSignature; + UINT32 FeatureArray[2]; + + /* Get current processor control block */ + Prcb = KeGetCurrentProcessorControlBlock(); /* Get CPU features */ RtlZeroMemory(&CpuRegisters, sizeof(CPUID_REGISTERS)); @@ -149,25 +181,29 @@ ArpIdentifyProcessor(VOID) Prcb->CpuId.Model = CpuSignature.Model; Prcb->CpuId.Stepping = CpuSignature.Stepping; + /* Prcb->CpuId.Vendor print*/ + DebugPrint(L"CPU Signature: %s\n", Prcb->CpuId.Vendor); + /* CPU vendor specific quirks */ - if(Prcb->CpuId.Vendor == CPU_VENDOR_AMD) + if (Prcb->CpuId.Vendor == CPU_VENDOR_AMD) { /* AMD CPU */ Prcb->CpuId.Family = Prcb->CpuId.Family + CpuSignature.ExtendedFamily; - if(Prcb->CpuId.Model == 0xF) + + if (Prcb->CpuId.Model == 0xF) { Prcb->CpuId.Model = Prcb->CpuId.Model + (CpuSignature.ExtendedModel << 4); } } - else if(Prcb->CpuId.Vendor == CPU_VENDOR_INTEL) + else if (Prcb->CpuId.Vendor == CPU_VENDOR_INTEL) { /* Intel CPU */ - if(Prcb->CpuId.Family == 0xF) + if (Prcb->CpuId.Family == 0xF) { Prcb->CpuId.Family = Prcb->CpuId.Family + CpuSignature.ExtendedFamily; } - if((Prcb->CpuId.Family == 0xF) || (Prcb->CpuId.Family == 0x6)) + if ((Prcb->CpuId.Family == 0xF) || (Prcb->CpuId.Family == 0x6)) { Prcb->CpuId.Model = Prcb->CpuId.Model + (CpuSignature.ExtendedModel << 4); } @@ -178,7 +214,29 @@ ArpIdentifyProcessor(VOID) Prcb->CpuId.Vendor = CPU_VENDOR_UNKNOWN; } - /* TODO: Store a list of CPU features in processor control block */ + /* Store CPU features in processor control block */ + FeatureArray[0] = CpuRegisters.Edx; + FeatureArray[1] = CpuRegisters.Ecx; + RtlCopyMemory(&Prcb->CpuFeatures, &FeatureArray[0], sizeof(UINT64)); +} + +/** + * Identifies processor type (vendor, model, stepping) as well as looks for available CPU features and stores them + * in Processor Control Block (PRCB). + * + * @return This routine does not return any value. + * + * @since XT 1.0 + */ +XTAPI +VOID +ArpIdentifyProcessor(VOID) +{ + /* Set CPU vendor */ + ArpSetCpuVendor(); + + /* Set CPU features */ + ArpSetCpuFeatures(); } /** diff --git a/xtoskrnl/includes/amd64/ar.h b/xtoskrnl/includes/amd64/ar.h index 96d7fa2..5cef37b 100644 --- a/xtoskrnl/includes/amd64/ar.h +++ b/xtoskrnl/includes/amd64/ar.h @@ -288,4 +288,12 @@ ArpSetIdtGate(IN PKIDTENTRY Idt, IN USHORT Ist, IN USHORT Access); +XTAPI +VOID +ArpSetCpuVendor(VOID); + +XTAPI +VOID +ArpSetCpuFeatures(VOID); + #endif /* __XTOSKRNL_AMD64_AR_H */ diff --git a/xtoskrnl/includes/i686/ar.h b/xtoskrnl/includes/i686/ar.h index c127954..f77c0ef 100644 --- a/xtoskrnl/includes/i686/ar.h +++ b/xtoskrnl/includes/i686/ar.h @@ -284,4 +284,12 @@ XTAPI VOID ArpSetNonMaskableInterruptTssEntry(IN PKPROCESSOR_BLOCK ProcessorBlock); +XTAPI +VOID +ArpSetCpuVendor(VOID); + +XTAPI +VOID +ArpSetCpuFeatures(VOID); + #endif /* __XTOSKRNL_I686_AR_H */ -- 2.45.1 From 289b1bdebc760b5e7fda2717bde4690eb59588ba Mon Sep 17 00:00:00 2001 From: PerikiyoXD Date: Mon, 27 Nov 2023 22:04:31 +0100 Subject: [PATCH 3/3] Rework _CPU_FEATURES structure --- sdk/xtdk/amd64/artypes.h | 156 ++++++++++++++++++++------------------- sdk/xtdk/i686/artypes.h | 153 ++++++++++++++++++++------------------ 2 files changed, 165 insertions(+), 144 deletions(-) diff --git a/sdk/xtdk/amd64/artypes.h b/sdk/xtdk/amd64/artypes.h index e3607b0..5888d83 100644 --- a/sdk/xtdk/amd64/artypes.h +++ b/sdk/xtdk/amd64/artypes.h @@ -111,7 +111,7 @@ #define X86_EFLAGS_ID_MASK 0x00200000 /* CPUID vendor names */ -#define CPUID_VENDOR_NAME_AMD "AuthenticAMD" +#define CPUID_VENDOR_NAME_AMD "AuthenticAMD" #define CPUID_VENDOR_NAME_INTEL "GenuineIntel" /* CPU vendor enumeration list */ @@ -190,81 +190,89 @@ typedef enum _CPUID_FEATURES } CPUID_FEATURES, *PCPUID_FEATURES; /* CPU features, as reported by CPUID instruction */ -typedef struct _CPU_FEATURES { - union { - struct { - BOOLEAN SSE3 : 1; - BOOLEAN PCLMUL : 1; - BOOLEAN DTES64 : 1; - BOOLEAN MONITOR : 1; - BOOLEAN DS_CPL : 1; - BOOLEAN VMX : 1; - BOOLEAN SMX : 1; - BOOLEAN EST : 1; - BOOLEAN TM2 : 1; - BOOLEAN SSSE3 : 1; - BOOLEAN CID : 1; - BOOLEAN SDBG : 1; - BOOLEAN FMA : 1; - BOOLEAN CX16 : 1; - BOOLEAN XTPR : 1; - BOOLEAN PDCM : 1; - BOOLEAN Reserved1 : 1; // Bit 16 is reserved - BOOLEAN PCID : 1; - BOOLEAN DCA : 1; - BOOLEAN SSE4_1 : 1; - BOOLEAN SSE4_2 : 1; - BOOLEAN X2APIC : 1; - BOOLEAN MOVBE : 1; - BOOLEAN POPCNT : 1; - BOOLEAN TSC_DEADLINE : 1; - BOOLEAN AES : 1; - BOOLEAN XSAVE : 1; - BOOLEAN OSXSAVE : 1; - BOOLEAN AVX : 1; - BOOLEAN F16C : 1; - BOOLEAN RDRAND : 1; - BOOLEAN HYPERVISOR : 1; +typedef union _CPU_FEATURES +{ + UINT64 Value; + union + { + UINT32 Ecx; + UINT32 ExtendedFeatures; + struct + { + BYTE SSE3 : 1; + BYTE PCLMUL : 1; + BYTE DTES64 : 1; + BYTE MONITOR : 1; + BYTE DS_CPL : 1; + BYTE VMX : 1; + BYTE SMX : 1; + BYTE EST : 1; + BYTE TM2 : 1; + BYTE SSSE3 : 1; + BYTE CID : 1; + BYTE SDBG : 1; + BYTE FMA : 1; + BYTE CX16 : 1; + BYTE XTPR : 1; + BYTE PDCM : 1; + BYTE Reserved4 : 1; // Bit 16 is reserved + BYTE PCID : 1; + BYTE DCA : 1; + BYTE SSE4_1 : 1; + BYTE SSE4_2 : 1; + BYTE X2APIC : 1; + BYTE MOVBE : 1; + BYTE POPCNT : 1; + BYTE TSC_DEADLINE : 1; + BYTE AES : 1; + BYTE XSAVE : 1; + BYTE OSXSAVE : 1; + BYTE AVX : 1; + BYTE F16C : 1; + BYTE RDRAND : 1; + BYTE HYPERVISOR : 1; + }; }; - UINT32 ExtendedFeatures; - }; - union { - struct { - BOOLEAN FPU : 1; - BOOLEAN VME : 1; - BOOLEAN DE : 1; - BOOLEAN PSE : 1; - BOOLEAN TSC : 1; - BOOLEAN MSR : 1; - BOOLEAN PAE : 1; - BOOLEAN MCE : 1; - BOOLEAN CX8 : 1; - BOOLEAN APIC : 1; - BOOLEAN Reserved2 : 1; // Bit 10 is reserved - BOOLEAN SEP : 1; - BOOLEAN MTRR : 1; - BOOLEAN PGE : 1; - BOOLEAN MCA : 1; - BOOLEAN CMOV : 1; - BOOLEAN PAT : 1; - BOOLEAN PSE36 : 1; - BOOLEAN PSN : 1; - BOOLEAN CLFLUSH : 1; - BOOLEAN Reserved3 : 1; // Bit 20 is reserved - BOOLEAN DS : 1; - BOOLEAN ACPI : 1; - BOOLEAN MMX : 1; - BOOLEAN FXSR : 1; - BOOLEAN SSE : 1; - BOOLEAN SSE2 : 1; - BOOLEAN SS : 1; - BOOLEAN HTT : 1; - BOOLEAN TM : 1; - BOOLEAN Reserved4 : 1; // Bit 30 is reserved - BOOLEAN PBE : 1; + union + { + UINT32 Edx; + UINT32 Features; + struct + { + BYTE FPU : 1; + BYTE VME : 1; + BYTE DE : 1; + BYTE PSE : 1; + BYTE TSC : 1; + BYTE MSR : 1; + BYTE PAE : 1; + BYTE MCE : 1; + BYTE CX8 : 1; + BYTE APIC : 1; + BYTE Reserved1 : 1; // Bit 10 is reserved + BYTE SEP : 1; + BYTE MTRR : 1; + BYTE PGE : 1; + BYTE MCA : 1; + BYTE CMOV : 1; + BYTE PAT : 1; + BYTE PSE36 : 1; + BYTE PSN : 1; + BYTE CLFLUSH : 1; + BYTE Reserved2 : 1; // Bit 20 is reserved + BYTE DS : 1; + BYTE ACPI : 1; + BYTE MMX : 1; + BYTE FXSR : 1; + BYTE SSE : 1; + BYTE SSE2 : 1; + BYTE SS : 1; + BYTE HTT : 1; + BYTE TM : 1; + BYTE Reserved3 : 1; // Bit 30 is reserved + BYTE PBE : 1; + }; }; - UINT64 Features; - }; } CPU_FEATURES, *PCPU_FEATURES; /* CPUID requests */ diff --git a/sdk/xtdk/i686/artypes.h b/sdk/xtdk/i686/artypes.h index 1c8cd77..c9f2142 100644 --- a/sdk/xtdk/i686/artypes.h +++ b/sdk/xtdk/i686/artypes.h @@ -62,7 +62,7 @@ #define SEGMENT_GS 0x65 /* CPUID vendor names */ -#define CPUID_VENDOR_NAME_AMD "AuthenticAMD" +#define CPUID_VENDOR_NAME_AMD "AuthenticAMD" #define CPUID_VENDOR_NAME_INTEL "GenuineIntel" /* CPU vendor enumeration list */ @@ -141,76 +141,89 @@ typedef enum _CPUID_FEATURES } CPUID_FEATURES, *PCPUID_FEATURES; /* CPU features, as reported by CPUID instruction */ -typedef struct _CPU_FEATURES { - union { - struct { - BOOLEAN SSE3 : 1; - BOOLEAN PCLMUL : 1; - BOOLEAN DTES64 : 1; - BOOLEAN MONITOR : 1; - BOOLEAN DS_CPL : 1; - BOOLEAN VMX : 1; - BOOLEAN SMX : 1; - BOOLEAN EST : 1; - BOOLEAN TM2 : 1; - BOOLEAN SSSE3 : 1; - BOOLEAN CID : 1; - BOOLEAN SDBG : 1; - BOOLEAN FMA : 1; - BOOLEAN CX16 : 1; - BOOLEAN XTPR : 1; - BOOLEAN PDCM : 1; - BOOLEAN Reserved1 : 1; // Bit 16 is reserved - BOOLEAN PCID : 1; - BOOLEAN DCA : 1; - BOOLEAN SSE4_1 : 1; - BOOLEAN SSE4_2 : 1; - BOOLEAN X2APIC : 1; - BOOLEAN MOVBE : 1; - BOOLEAN POPCNT : 1; - BOOLEAN TSC_DEADLINE : 1; - BOOLEAN AES : 1; - BOOLEAN XSAVE : 1; - BOOLEAN OSXSAVE : 1; - BOOLEAN AVX : 1; - BOOLEAN F16C : 1; - BOOLEAN RDRAND : 1; - BOOLEAN HYPERVISOR : 1; - BOOLEAN FPU : 1; - BOOLEAN VME : 1; - BOOLEAN DE : 1; - BOOLEAN PSE : 1; - BOOLEAN TSC : 1; - BOOLEAN MSR : 1; - BOOLEAN PAE : 1; - BOOLEAN MCE : 1; - BOOLEAN CX8 : 1; - BOOLEAN APIC : 1; - BOOLEAN Reserved2 : 1; // Bit 10 is reserved - BOOLEAN SEP : 1; - BOOLEAN MTRR : 1; - BOOLEAN PGE : 1; - BOOLEAN MCA : 1; - BOOLEAN CMOV : 1; - BOOLEAN PAT : 1; - BOOLEAN PSE36 : 1; - BOOLEAN PSN : 1; - BOOLEAN CLFLUSH : 1; - BOOLEAN Reserved3 : 1; // Bit 20 is reserved - BOOLEAN DS : 1; - BOOLEAN ACPI : 1; - BOOLEAN MMX : 1; - BOOLEAN FXSR : 1; - BOOLEAN SSE : 1; - BOOLEAN SSE2 : 1; - BOOLEAN SS : 1; - BOOLEAN HTT : 1; - BOOLEAN TM : 1; - BOOLEAN Reserved4 : 1; // Bit 30 is reserved - BOOLEAN PBE : 1; +typedef union _CPU_FEATURES +{ + UINT64 Value; + union + { + UINT32 Ecx; + UINT32 ExtendedFeatures; + struct + { + BYTE SSE3 : 1; + BYTE PCLMUL : 1; + BYTE DTES64 : 1; + BYTE MONITOR : 1; + BYTE DS_CPL : 1; + BYTE VMX : 1; + BYTE SMX : 1; + BYTE EST : 1; + BYTE TM2 : 1; + BYTE SSSE3 : 1; + BYTE CID : 1; + BYTE SDBG : 1; + BYTE FMA : 1; + BYTE CX16 : 1; + BYTE XTPR : 1; + BYTE PDCM : 1; + BYTE Reserved1 : 1; // Bit 16 is reserved + BYTE PCID : 1; + BYTE DCA : 1; + BYTE SSE4_1 : 1; + BYTE SSE4_2 : 1; + BYTE X2APIC : 1; + BYTE MOVBE : 1; + BYTE POPCNT : 1; + BYTE TSC_DEADLINE : 1; + BYTE AES : 1; + BYTE XSAVE : 1; + BYTE OSXSAVE : 1; + BYTE AVX : 1; + BYTE F16C : 1; + BYTE RDRAND : 1; + BYTE HYPERVISOR : 1; + }; + }; + union + { + UINT32 Edx; + UINT32 Features; + struct + { + BYTE FPU : 1; + BYTE VME : 1; + BYTE DE : 1; + BYTE PSE : 1; + BYTE TSC : 1; + BYTE MSR : 1; + BYTE PAE : 1; + BYTE MCE : 1; + BYTE CX8 : 1; + BYTE APIC : 1; + BYTE Reserved2 : 1; // Bit 10 is reserved + BYTE SEP : 1; + BYTE MTRR : 1; + BYTE PGE : 1; + BYTE MCA : 1; + BYTE CMOV : 1; + BYTE PAT : 1; + BYTE PSE36 : 1; + BYTE PSN : 1; + BYTE CLFLUSH : 1; + BYTE Reserved3 : 1; // Bit 20 is reserved + BYTE DS : 1; + BYTE ACPI : 1; + BYTE MMX : 1; + BYTE FXSR : 1; + BYTE SSE : 1; + BYTE SSE2 : 1; + BYTE SS : 1; + BYTE HTT : 1; + BYTE TM : 1; + BYTE Reserved4 : 1; // Bit 30 is reserved + BYTE PBE : 1; + }; }; - UINT64 AsUINT64; - }; } CPU_FEATURES, *PCPU_FEATURES; /* CPUID requests */ -- 2.45.1