416 lines
10 KiB
C++
416 lines
10 KiB
C++
/**
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* PROJECT: ExectOS
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* COPYRIGHT: See COPYING.md in the top level directory
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* FILE: xtoskrnl/hl/x86/pic.cc
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* DESCRIPTION: Programmable Interrupt Controller (PIC) for x86 (i686/AMD64) support
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* DEVELOPERS: Rafal Kupiec <belliash@codingworkshop.eu.org>
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*/
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#include <xtos.hh>
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/**
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* Checks whether the x2APIC extension is supported by the processor.
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*
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* @return This routine returns TRUE if x2APIC is supported, or FALSE otherwise.
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*
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* @since XT 1.0
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*
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* @todo Check if bits 0 and 1 of DMAR ACPI table flags are set after implementing ACPI support.
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* Intel VT-d spec says x2apic should not be enabled if they are.
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*/
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XTAPI
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BOOLEAN
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HL::Pic::CheckX2ApicSupport(VOID)
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{
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CPUID_REGISTERS CpuRegisters;
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/* Prepare CPUID registers */
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CpuRegisters.Leaf = CPUID_GET_STANDARD1_FEATURES;
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CpuRegisters.SubLeaf = 0;
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CpuRegisters.Eax = 0;
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CpuRegisters.Ebx = 0;
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CpuRegisters.Ecx = 0;
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CpuRegisters.Edx = 0;
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/* Get CPUID */
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AR::CpuFunc::CpuId(&CpuRegisters);
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/* Check x2APIC status from the CPUID results */
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if(!(CpuRegisters.Ecx & CPUID_FEATURES_ECX_X2APIC))
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{
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/* x2APIC is not supported */
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return FALSE;
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}
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/* x2APIC is supported */
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return TRUE;
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}
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/**
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* Clears all errors on the APIC.
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*
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* @return This routine does not return any value.
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*
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* @since XT 1.0
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*/
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XTAPI
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VOID
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HL::Pic::ClearApicErrors(VOID)
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{
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/* Clear APIC errors */
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WriteApicRegister(APIC_ESR, 0);
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}
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/**
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* Gets the local APIC ID of the current processor.
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*
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* @return This routine returns the current processor's local APIC ID.
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*
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* @since XT 1.0
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*/
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XTAPI
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ULONG
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HL::Pic::GetCpuApicId(VOID)
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{
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ULONG ApicId;
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/* Read APIC ID register */
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ApicId = ReadApicRegister(APIC_ID);
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/* Return logical CPU ID depending on current APIC mode */
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return (ApicMode == APIC_MODE_COMPAT) ? ((ApicId & 0xFFFFFFFF) >> APIC_XAPIC_LDR_SHIFT) : ApicId;
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}
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/**
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* Allows an APIC spurious interrupts to end up.
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*
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* @return This routine does not return any value.
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*
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* @since XT 1.0
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*/
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XTCDECL
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VOID
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HL::Pic::HandleApicSpuriousService(VOID)
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{
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}
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/**
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* Allows a PIC spurious interrupts to end up.
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*
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* @return This routine does not return any value.
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*
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* @since XT 1.0
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*/
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XTCDECL
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VOID
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HL::Pic::HandlePicSpuriousService(VOID)
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{
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}
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/**
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* Initializes the APIC interrupt controller.
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*
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* @return This routine does not return any value.
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*
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* @since XT 1.0
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*/
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XTAPI
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VOID
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HL::Pic::InitializeApic(VOID)
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{
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APIC_SPURIOUS_REGISTER SpuriousRegister;
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APIC_BASE_REGISTER BaseRegister;
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APIC_LVT_REGISTER LvtRegister;
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ULONG CpuNumber;
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/* Determine APIC mode (xAPIC compatibility or x2APIC) */
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if(CheckX2ApicSupport())
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{
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/* Enable x2APIC mode */
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ApicMode = APIC_MODE_X2APIC;
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}
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else
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{
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/* Fall back to xAPIC compatibility mode */
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ApicMode = APIC_MODE_COMPAT;
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}
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/* Get current processor number */
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CpuNumber = KE::Processor::GetCurrentProcessorNumber();
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/* Enable the APIC */
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BaseRegister.LongLong = AR::CpuFunc::ReadModelSpecificRegister(APIC_LAPIC_MSR_BASE);
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BaseRegister.Enable = 1;
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BaseRegister.ExtendedMode = (ApicMode == APIC_MODE_X2APIC);
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BaseRegister.BootStrapProcessor = (CpuNumber == 0) ? 1 : 0;
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AR::CpuFunc::WriteModelSpecificRegister(APIC_LAPIC_MSR_BASE, BaseRegister.LongLong);
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/* Mask all interrupts by raising Task Priority Register (TPR) */
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WriteApicRegister(APIC_TPR, 0xFF);
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/* Perform initialization specific to xAPIC compatibility mode */
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if(ApicMode == APIC_MODE_COMPAT)
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{
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/* Use Flat Model for destination format (not supported in x2APIC) */
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WriteApicRegister(APIC_DFR, APIC_DF_FLAT);
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/* Set the logical APIC ID for this processor (read-only in x2APIC) */
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WriteApicRegister(APIC_LDR, (1UL << CpuNumber) << 24);
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}
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/* Configure the spurious interrupt vector */
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SpuriousRegister.Long = ReadApicRegister(APIC_SIVR);
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SpuriousRegister.Vector = APIC_VECTOR_SPURIOUS;
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SpuriousRegister.SoftwareEnable = 1;
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SpuriousRegister.CoreChecking = 0;
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WriteApicRegister(APIC_SIVR, SpuriousRegister.Long);
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/* Setup the LVT Error entry to deliver APIC errors on a dedicated vector */
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WriteApicRegister(APIC_ERRLVTR, APIC_VECTOR_ERROR);
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/* Program the APIC timer for periodic mode */
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LvtRegister.Long = 0;
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LvtRegister.Mask = 1;
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LvtRegister.DeliveryMode = APIC_DM_FIXED;
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LvtRegister.TimerMode = 1;
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LvtRegister.TriggerMode = APIC_TGM_EDGE;
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LvtRegister.Vector = APIC_VECTOR_PROFILE;
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WriteApicRegister(APIC_TMRLVTR, LvtRegister.Long);
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/* Configure the performance counter overflow */
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LvtRegister.Long = 0;
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LvtRegister.Mask = 0;
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LvtRegister.DeliveryMode = APIC_DM_FIXED;
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LvtRegister.TimerMode = 0;
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LvtRegister.TriggerMode = APIC_TGM_EDGE;
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LvtRegister.Vector = APIC_VECTOR_PERF;
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WriteApicRegister(APIC_PCLVTR, LvtRegister.Long);
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/* Configure the LINT0 pin */
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LvtRegister.Long = 0;
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LvtRegister.Mask = 1;
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LvtRegister.DeliveryMode = APIC_DM_FIXED;
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LvtRegister.TimerMode = 0;
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LvtRegister.TriggerMode = APIC_TGM_EDGE;
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LvtRegister.Vector = APIC_VECTOR_SPURIOUS;
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WriteApicRegister(APIC_LINT0, LvtRegister.Long);
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/* Configure the LINT1 pin */
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LvtRegister.Long = 0;
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LvtRegister.Mask = 0;
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LvtRegister.DeliveryMode = APIC_DM_NMI;
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LvtRegister.TimerMode = 0;
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LvtRegister.TriggerMode = APIC_TGM_EDGE;
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LvtRegister.Vector = APIC_VECTOR_NMI;
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WriteApicRegister(APIC_LINT1, LvtRegister.Long);
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/* Register interrupt handlers */
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KE::Irq::SetInterruptHandler(APIC_VECTOR_SPURIOUS, (PVOID)HandleApicSpuriousService);
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KE::Irq::SetInterruptHandler(PIC1_VECTOR_SPURIOUS, (PVOID)HandlePicSpuriousService);
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/* Clear any pre-existing errors */
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WriteApicRegister(APIC_ESR, 0);
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/* Re-enable all interrupts by lowering the Task Priority Register */
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WriteApicRegister(APIC_TPR, 0x00);
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}
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/**
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* Initializes the legacy PIC interrupt controller.
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*
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* @return This routine does not return any value.
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*
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* @since XT 1.0
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*/
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XTAPI
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VOID
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HL::Pic::InitializeLegacyPic(VOID)
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{
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PIC_I8259_ICW1 Icw1;
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PIC_I8259_ICW2 Icw2;
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PIC_I8259_ICW3 Icw3;
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PIC_I8259_ICW4 Icw4;
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/* Initialize ICW1 for PIC1 port */
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Icw1.Init = TRUE;
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Icw1.InterruptMode = EdgeTriggered;
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Icw1.InterruptVectorAddress = 0;
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Icw1.Interval = Interval8;
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Icw1.NeedIcw4 = TRUE;
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Icw1.OperatingMode = Cascade;
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HL::IoPort::WritePort8(PIC1_CONTROL_PORT, Icw1.Bits);
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/* Initialize ICW2 for PIC1 port */
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Icw2.Bits = 0x00;
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HL::IoPort::WritePort8(PIC1_DATA_PORT, Icw2.Bits);
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/* Initialize ICW3 for PIC1 port */
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Icw3.Bits = 0;
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Icw3.SlaveIrq2 = TRUE;
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HL::IoPort::WritePort8(PIC1_DATA_PORT, Icw3.Bits);
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/* Initialize ICW4 for PIC1 port */
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Icw4.BufferedMode = NonBuffered;
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Icw4.EoiMode = NormalEoi;
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Icw4.Reserved = 0;
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Icw4.SpecialFullyNestedMode = FALSE;
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Icw4.SystemMode = New8086Mode;
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HL::IoPort::WritePort8(PIC1_DATA_PORT, Icw4.Bits);
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/* Mask all interrupts on PIC1 port */
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HL::IoPort::WritePort8(PIC1_DATA_PORT, 0xFF);
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/* Initialize ICW1 for PIC2 port */
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Icw1.Init = TRUE;
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Icw1.InterruptMode = EdgeTriggered;
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Icw1.InterruptVectorAddress = 0;
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Icw1.Interval = Interval8;
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Icw1.NeedIcw4 = TRUE;
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Icw1.OperatingMode = Cascade;
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HL::IoPort::WritePort8(PIC2_CONTROL_PORT, Icw1.Bits);
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/* Initialize ICW2 for PIC2 port */
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Icw2.Bits = 0x08;
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HL::IoPort::WritePort8(PIC2_DATA_PORT, Icw2.Bits);
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/* Initialize ICW3 for PIC2 port */
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Icw3.Bits = 0;
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Icw3.SlaveId = 2;
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HL::IoPort::WritePort8(PIC2_DATA_PORT, Icw3.Bits);
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/* Initialize ICW4 for PIC2 port */
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Icw4.BufferedMode = NonBuffered;
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Icw4.EoiMode = NormalEoi;
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Icw4.Reserved = 0;
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Icw4.SpecialFullyNestedMode = FALSE;
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Icw4.SystemMode = New8086Mode;
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HL::IoPort::WritePort8(PIC2_DATA_PORT, Icw4.Bits);
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/* Mask all interrupts on PIC2 port */
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HL::IoPort::WritePort8(PIC2_DATA_PORT, 0xFF);
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}
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/**
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* Initializes the (A)PIC interrupt controller.
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*
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* @return This routine does not return any value.
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*
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* @since XT 1.0
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*
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* @todo Initialize APIC only when supported, otherwise fall back to legacy PIC.
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*/
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XTAPI
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VOID
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HL::Pic::InitializePic(VOID)
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{
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/* Initialize APIC */
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InitializeApic();
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/* Initialize legacy PIC */
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InitializeLegacyPic();
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}
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/**
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* Reads from the APIC register.
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*
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* @param Register
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* Supplies the APIC register to read from.
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*
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* @return This routine returns the value read from the APIC register.
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*
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* @since XT 1.0
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*/
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XTFASTCALL
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ULONGLONG
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HL::Pic::ReadApicRegister(IN APIC_REGISTER Register)
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{
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if(ApicMode == APIC_MODE_X2APIC)
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{
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/* Read from x2APIC MSR */
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return AR::CpuFunc::ReadModelSpecificRegister((ULONG)(APIC_X2APIC_MSR_BASE + Register));
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}
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else
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{
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/* Read from xAPIC */
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return IoRegister::ReadRegister32((PULONG)(APIC_BASE + (Register << 4)));
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}
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}
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/**
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* Signals to the APIC that handling an interrupt is complete.
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*
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* @return This routine does not return any value.
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*
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* @since XT 1.0
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*/
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XTAPI
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VOID
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HL::Pic::SendEoi(VOID)
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{
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/* Send APIC EOI */
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WriteApicRegister(APIC_EOI, 0);
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}
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/**
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* Sends an IPI (Inter-Processor Interrupt) to the specified CPU.
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*
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* @param ApicId
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* Supplies a CPU APIC ID to send an IPI to.
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*
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* @param Vector
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* Supplies the IPI vector to send.
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*
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* @return This routine does not return any value.
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*
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* @since XT 1.0
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*/
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XTAPI
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VOID
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HL::Pic::SendIpi(ULONG ApicId,
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ULONG Vector)
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{
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/* Check current APIC mode */
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if(ApicMode == APIC_MODE_X2APIC)
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{
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/* Send IPI using x2APIC mode */
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WriteApicRegister(APIC_ICR0, ((ULONGLONG)ApicId << 32) | Vector);
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}
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else
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{
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/* Send IPI using xAPIC compatibility mode */
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WriteApicRegister(APIC_ICR1, ApicId << 24);
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WriteApicRegister(APIC_ICR0, Vector);
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}
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}
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/**
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* Writes to the APIC register.
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*
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* @param Register
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* Supplies the APIC register to write to.
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*
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* @param Value
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* Supplies the value to write to the APIC register.
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*
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* @return This routine does not return any value.
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*
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* @since XT 1.0
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*/
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XTFASTCALL
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VOID
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HL::Pic::WriteApicRegister(IN APIC_REGISTER Register,
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IN ULONGLONG Value)
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{
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if(ApicMode == APIC_MODE_X2APIC)
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{
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/* Write to x2APIC MSR */
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AR::CpuFunc::WriteModelSpecificRegister((ULONG)(APIC_X2APIC_MSR_BASE + Register), Value);
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}
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else
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{
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/* Write to xAPIC */
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IoRegister::WriteRegister32((PULONG)(APIC_BASE + (Register << 4)), Value);
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}
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}
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