444 lines
15 KiB
C
444 lines
15 KiB
C
/**
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* PROJECT: ExectOS
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* COPYRIGHT: See COPYING.md in the top level directory
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* FILE: xtoskrnl/ar/amd64/procsup.c
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* DESCRIPTION: AMD64 processor functionality support
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* DEVELOPERS: Rafal Kupiec <belliash@codingworkshop.eu.org>
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*/
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#include "xtos.h"
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/**
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* Initializes AMD64 processor specific structures.
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*
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* @return This routine does not return any value.
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*
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* @since XT 1.0
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*/
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XTAPI
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VOID
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ArInitializeProcessor(VOID)
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{
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KDESCRIPTOR GdtDescriptor, IdtDescriptor;
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PKPROCESSOR_BLOCK ProcessorBlock;
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PKGDTENTRY Gdt;
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PKIDTENTRY Idt;
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PKTSS Tss;
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/* Use initial structures */
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Gdt = ArInitialGdt;
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Idt = ArInitialIdt;
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Tss = &ArInitialTss;
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/* Load processor block */
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ProcessorBlock = CONTAIN_RECORD(&ArInitialProcessorBlock.Prcb, KPROCESSOR_BLOCK, Prcb);
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/* Initialize processor block */
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ArpInitializeProcessorBlock(ProcessorBlock, Gdt, Idt, Tss, (PVOID)KeInitializationBlock->KernelFaultStack);
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/* Initialize GDT, IDT and TSS */
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ArpInitializeGdt(ProcessorBlock);
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ArpInitializeTss(ProcessorBlock);
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ArpInitializeIdt(ProcessorBlock);
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/* Set GDT and IDT descriptors */
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GdtDescriptor.Base = Gdt;
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GdtDescriptor.Limit = (GDT_ENTRIES * sizeof(KGDTENTRY)) - 1;
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IdtDescriptor.Base = Idt;
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IdtDescriptor.Limit = (IDT_ENTRIES * sizeof(KIDTENTRY)) - 1;
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/* Load GDT, IDT and TSS */
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ArLoadGlobalDescriptorTable(&GdtDescriptor.Limit);
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ArLoadInterruptDescriptorTable(&IdtDescriptor.Limit);
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ArLoadTaskRegister((UINT)KGDT_SYS_TSS);
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/* Enter passive IRQ level */
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ProcessorBlock->Irql = PASSIVE_LEVEL;
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ArWriteControlRegister(8, PASSIVE_LEVEL);
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/* Initialize segment registers */
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ArpInitializeSegments();
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/* Set GS base */
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ArWriteModelSpecificRegister(X86_MSR_GSBASE, (ULONGLONG)ProcessorBlock);
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ArWriteModelSpecificRegister(X86_MSR_KERNEL_GSBASE, (ULONGLONG)ProcessorBlock);
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/* Initialize processor registers */
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ArpInitializeProcessorRegisters();
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/* Identify processor */
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ArpIdentifyProcessor();
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}
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XTAPI
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VOID
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ArpIdentifyProcessor(VOID)
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{
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}
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/**
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* Initializes the kernel's Global Descriptor Table (GDT).
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*
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* @param Gdt
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* Supplies a pointer to the GDT to use.
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*
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* @return This routine does not return any value.
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*
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* @since XT 1.0
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*/
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XTAPI
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VOID
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ArpInitializeGdt(IN PKPROCESSOR_BLOCK ProcessorBlock)
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{
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/* Initialize GDT entries */
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ArpSetGdtEntry(ProcessorBlock->GdtBase, KGDT_NULL, 0x0, 0x0, KGDT_TYPE_NONE, KGDT_DPL_SYSTEM, 1);
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ArpSetGdtEntry(ProcessorBlock->GdtBase, KGDT_R0_CODE, 0x0, 0x0, KGDT_TYPE_CODE, KGDT_DPL_SYSTEM, 1);
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ArpSetGdtEntry(ProcessorBlock->GdtBase, KGDT_R0_DATA, 0x0, 0x0, KGDT_TYPE_DATA, KGDT_DPL_SYSTEM, 1);
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ArpSetGdtEntry(ProcessorBlock->GdtBase, KGDT_R3_CMCODE, 0x0, 0xFFFFFFFF, KGDT_TYPE_CODE, KGDT_DPL_USER, 2);
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ArpSetGdtEntry(ProcessorBlock->GdtBase, KGDT_R3_DATA, 0x0, 0xFFFFFFFF, KGDT_TYPE_DATA, KGDT_DPL_USER, 2);
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ArpSetGdtEntry(ProcessorBlock->GdtBase, KGDT_R3_CODE, 0x0, 0x0, KGDT_TYPE_CODE, KGDT_DPL_USER, 1);
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ArpSetGdtEntry(ProcessorBlock->GdtBase, KGDT_SYS_TSS, (ULONG_PTR)ProcessorBlock->TssBase, sizeof(KTSS), AMD64_TSS, KGDT_DPL_SYSTEM, 0);
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ArpSetGdtEntry(ProcessorBlock->GdtBase, KGDT_R3_CMTEB, 0x0, 0x0FFF, KGDT_TYPE_DATA, KGDT_DPL_USER, 2);
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ArpSetGdtEntry(ProcessorBlock->GdtBase, KGDT_R0_LDT, 0x0, 0xFFFFFFFF, KGDT_TYPE_CODE, KGDT_DPL_SYSTEM, 0);
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ArpSetGdtEntry(ProcessorBlock->GdtBase, KGDT_ALIAS, (ULONG_PTR)ProcessorBlock->GdtBase, (GDT_ENTRIES * sizeof(KGDTENTRY)) - 1, KGDT_TYPE_DATA, KGDT_DPL_SYSTEM, 0);
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}
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/**
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* Initializes the kernel's Interrupt Descriptor Table (IDT).
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*
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* @param ProcessorBlock
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* Supplies a pointer to the processor block to use.
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*
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* @return This routine does not return any value.
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*
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* @since XT 1.0
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*/
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XTAPI
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VOID
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ArpInitializeIdt(IN PKPROCESSOR_BLOCK ProcessorBlock)
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{
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UINT Vector;
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/* Fill in all vectors */
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for(Vector = 0; Vector < IDT_ENTRIES; Vector++)
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{
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/* Set the IDT to handle unexpected interrupts */
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ArpSetIdtGate(ProcessorBlock->IdtBase, Vector, ArpHandleTrapFF, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0);
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}
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/* Setup IDT handlers for known interrupts and traps */
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ArpSetIdtGate(ProcessorBlock->IdtBase, 0x00, ArpHandleTrap00, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0);
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ArpSetIdtGate(ProcessorBlock->IdtBase, 0x01, ArpHandleTrap01, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0);
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ArpSetIdtGate(ProcessorBlock->IdtBase, 0x02, ArpHandleTrap02, KGDT_R0_CODE, KIDT_IST_PANIC, KIDT_ACCESS_RING0);
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ArpSetIdtGate(ProcessorBlock->IdtBase, 0x03, ArpHandleTrap03, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING3);
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ArpSetIdtGate(ProcessorBlock->IdtBase, 0x04, ArpHandleTrap04, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING3);
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ArpSetIdtGate(ProcessorBlock->IdtBase, 0x05, ArpHandleTrap05, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0);
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ArpSetIdtGate(ProcessorBlock->IdtBase, 0x06, ArpHandleTrap06, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0);
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ArpSetIdtGate(ProcessorBlock->IdtBase, 0x07, ArpHandleTrap07, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0);
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ArpSetIdtGate(ProcessorBlock->IdtBase, 0x08, ArpHandleTrap08, KGDT_R0_CODE, KIDT_IST_PANIC, KIDT_ACCESS_RING0);
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ArpSetIdtGate(ProcessorBlock->IdtBase, 0x09, ArpHandleTrap09, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0);
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ArpSetIdtGate(ProcessorBlock->IdtBase, 0x0A, ArpHandleTrap0A, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0);
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ArpSetIdtGate(ProcessorBlock->IdtBase, 0x0B, ArpHandleTrap0B, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0);
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ArpSetIdtGate(ProcessorBlock->IdtBase, 0x0C, ArpHandleTrap0C, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0);
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ArpSetIdtGate(ProcessorBlock->IdtBase, 0x0D, ArpHandleTrap0D, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0);
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ArpSetIdtGate(ProcessorBlock->IdtBase, 0x0E, ArpHandleTrap0E, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0);
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ArpSetIdtGate(ProcessorBlock->IdtBase, 0x10, ArpHandleTrap10, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0);
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ArpSetIdtGate(ProcessorBlock->IdtBase, 0x11, ArpHandleTrap11, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0);
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ArpSetIdtGate(ProcessorBlock->IdtBase, 0x12, ArpHandleTrap12, KGDT_R0_CODE, KIDT_IST_MCA, KIDT_ACCESS_RING0);
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ArpSetIdtGate(ProcessorBlock->IdtBase, 0x13, ArpHandleTrap13, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0);
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ArpSetIdtGate(ProcessorBlock->IdtBase, 0x2C, ArpHandleTrap2C, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING3);
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ArpSetIdtGate(ProcessorBlock->IdtBase, 0x2D, ArpHandleTrap2D, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING3);
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}
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/**
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* Initializes processor block.
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*
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* @param ProcessorBlock
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* Supplies a pointer to the processor block to initialize.
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*
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* @param Gdt
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* Supplies a pointer to the GDT for this processor block.
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*
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* @param Idt
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* Supplies a pointer to the IDT for this processor block.
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*
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* @param Tss
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* Supplies a pointer to the TSS for this processor block.
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*
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* @return This routine does not return any value.
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*
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* @since XT 1.0
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*/
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XTAPI
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VOID
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ArpInitializeProcessorBlock(OUT PKPROCESSOR_BLOCK ProcessorBlock,
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IN PKGDTENTRY Gdt,
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IN PKIDTENTRY Idt,
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IN PKTSS Tss,
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IN PVOID DpcStack)
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{
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/* Fill processor block with zeroes */
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RtlZeroMemory(ProcessorBlock, sizeof(KPROCESSOR_BLOCK));
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/* Set processor block and processor control block */
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ProcessorBlock->Self = ProcessorBlock;
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ProcessorBlock->CurrentPrcb = &ProcessorBlock->Prcb;
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/* Set GDT, IDT and TSS descriptors */
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ProcessorBlock->GdtBase = (PVOID)Gdt;
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ProcessorBlock->IdtBase = Idt;
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ProcessorBlock->TssBase = Tss;
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ProcessorBlock->Prcb.RspBase = Tss->Rsp0;
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/* Setup DPC stack */
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ProcessorBlock->Prcb.DpcStack = DpcStack;
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/* Setup processor control block */
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ProcessorBlock->Prcb.Number = 0;
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ProcessorBlock->Prcb.SetMember = 1ULL;
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ProcessorBlock->Prcb.MultiThreadProcessorSet = 1ULL;
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/* Clear DR6 and DR7 registers */
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ProcessorBlock->Prcb.ProcessorState.SpecialRegisters.KernelDr6 = 0;
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ProcessorBlock->Prcb.ProcessorState.SpecialRegisters.KernelDr7 = 0;
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/* Set initial MXCSR register value */
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ProcessorBlock->Prcb.MxCsr = INITIAL_MXCSR;
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}
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/**
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* Initializes processor registers and other boot structures.
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*
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* @return This routine does not return any value.
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*
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* @since XT 1.0
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*/
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XTAPI
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VOID
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ArpInitializeProcessorRegisters(VOID)
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{
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ULONGLONG PatAttributes;
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/* Enable FXSAVE restore */
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ArWriteControlRegister(4, ArReadControlRegister(4) | CR4_FXSR);
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/* Enable XMMI exceptions */
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ArWriteControlRegister(4, ArReadControlRegister(4) | CR4_XMMEXCPT);
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/* Set debugger extension */
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ArWriteControlRegister(4, ArReadControlRegister(4) | CR4_DE);
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/* Enable global paging support */
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ArWriteControlRegister(4, ArReadControlRegister(4) | CR4_PGE);
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/* Enable large pages */
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ArWriteControlRegister(4, ArReadControlRegister(4) | CR4_PSE);
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/* Enable write-protection */
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ArWriteControlRegister(0, ArReadControlRegister(0) | CR0_WP);
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/* Set alignment mask */
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ArWriteControlRegister(0, ArReadControlRegister(0) | CR0_AM);
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/* Disable FPU monitoring */
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ArWriteControlRegister(0, ArReadControlRegister(0) & ~CR0_MP);
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/* Disable x87 FPU exceptions */
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ArWriteControlRegister(0, ArReadControlRegister(0) & ~CR0_NE);
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/* Initialize system calls MSR */
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ArWriteModelSpecificRegister(X86_MSR_STAR, (((ULONG64)KGDT_R3_CMCODE | RPL_MASK) << 48) | ((ULONG64)KGDT_R0_CODE << 32));
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ArWriteModelSpecificRegister(X86_MSR_CSTAR, (ULONG64)&ArpHandleSystemCall32);
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ArWriteModelSpecificRegister(X86_MSR_LSTAR, (ULONG64)&ArpHandleSystemCall64);
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ArWriteModelSpecificRegister(X86_MSR_FMASK, X86_EFLAGS_IF_MASK | X86_EFLAGS_TF_MASK);
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/* Enable system call extensions (SCE) in EFER MSR */
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ArWriteModelSpecificRegister(X86_MSR_EFER, ArReadModelSpecificRegister(X86_MSR_EFER) | X86_MSR_EFER_SCE);
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/* Enable No-Execute (NXE) in EFER MSR */
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ArWriteModelSpecificRegister(X86_MSR_EFER, ArReadModelSpecificRegister(X86_MSR_EFER) | X86_MSR_EFER_NXE);
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/* Initialize Page Attribute Table */
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PatAttributes = (PAT_TYPE_WB << 0) | (PAT_TYPE_USWC << 8) | (PAT_TYPE_WEAK_UC << 16) | (PAT_TYPE_STRONG_UC << 24) |
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(PAT_TYPE_WB << 32) | (PAT_TYPE_USWC << 40) | (PAT_TYPE_WEAK_UC << 48) | (PAT_TYPE_STRONG_UC << 56);
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ArWriteModelSpecificRegister(X86_MSR_PAT, PatAttributes);
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/* Initialize MXCSR register */
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ArLoadMxcsrRegister(INITIAL_MXCSR);
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}
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/**
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* Initializes segment registers.
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*
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* @return This routine does not return any value.
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*
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* @since XT 1.0
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*/
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XTAPI
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VOID
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ArpInitializeSegments(VOID)
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{
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asm volatile("mov %0, %%ax\n"
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"mov %%ax, %%fs\n"
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"mov %1, %%ax\n"
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"mov %%ax, %%ds\n"
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"mov %%ax, %%es\n"
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"mov %%ax, %%gs\n"
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"swapgs\n"
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"mov %%ax, %%gs\n"
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:
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: "i" (KGDT_R3_CMTEB | RPL_MASK),
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"i" (KGDT_R3_DATA | RPL_MASK));
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}
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/**
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* Initializes the kernel's Task State Segment (TSS).
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*
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* @param Tss
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* Supplies a pointer to the TSS to use.
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*
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* @param Gdt
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* Supplies a pointer to the GDT to use.
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*
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* @return This routine does not return any value.
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*
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* @since XT 1.0
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*/
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XTAPI
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VOID
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ArpInitializeTss(IN PKPROCESSOR_BLOCK ProcessorBlock)
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{
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/* Fill TSS with zeroes */
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RtlZeroMemory(ProcessorBlock->TssBase, sizeof(KTSS));
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/* Setup I/O map and stacks for ring0 & traps */
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ProcessorBlock->TssBase->IoMapBase = sizeof(KTSS);
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ProcessorBlock->TssBase->Rsp0 = KeInitializationBlock->KernelBootStack;
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ProcessorBlock->TssBase->Ist[KIDT_IST_PANIC] = KeInitializationBlock->KernelFaultStack;
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ProcessorBlock->TssBase->Ist[KIDT_IST_MCA] = KeInitializationBlock->KernelFaultStack;
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}
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/**
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* Fills in an AMD64 GDT entry.
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*
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* @param Gdt
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* Supplies a pointer to the GDT.
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*
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* @param Selector
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* Specifies a segment selector of the GDT entry.
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*
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* @param Base
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* Specifies a base address value of the descriptor.
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*
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* @param Limit
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* Specifies a descriptor limit.
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*
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* @param Type
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* Specifies a type of the descriptor.
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*
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* @param Dpl
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* Specifies the descriptor privilege level.
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*
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* @param SegmentMode
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* Specifies a segment mode of the descriptor.
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*
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* @return This routine does not return any value
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*
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* @since XT 1.0
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*/
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XTAPI
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VOID
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ArpSetGdtEntry(IN PKGDTENTRY Gdt,
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IN USHORT Selector,
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IN ULONG_PTR Base,
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IN ULONG Limit,
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IN UCHAR Type,
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IN UCHAR Dpl,
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IN UCHAR SegmentMode)
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{
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PKGDTENTRY GdtEntry;
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UCHAR Granularity;
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/* Set the granularity flag depending on descriptor limit */
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if(Limit < 0x100000)
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{
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/* Limit is in 1B blocks */
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Granularity = 0;
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}
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else
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{
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/* Limit is in 4KB blocks */
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Granularity = 1;
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Limit >>= 12;
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}
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/* Get GDT entry */
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GdtEntry = (PKGDTENTRY)((ULONG_PTR)Gdt + (Selector & ~RPL_MASK));
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/* Set GDT descriptor base */
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GdtEntry->BaseLow = Base & 0xFFFF;
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GdtEntry->Bytes.BaseMiddle = (Base >> 16) & 0xFF;
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GdtEntry->Bytes.BaseHigh = (Base >> 24) & 0xFF;
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GdtEntry->BaseUpper = Base >> 32;
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/* Set descriptor limit */
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GdtEntry->LimitLow = Limit & 0xFFFF;
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GdtEntry->Bits.LimitHigh = (Limit >> 16) & 0xF;
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/* Initialize GDT entry */
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GdtEntry->Bits.DefaultBig = !!(SegmentMode & 2);
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GdtEntry->Bits.Dpl = (Dpl & 0x3);
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GdtEntry->Bits.Granularity = Granularity;
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GdtEntry->Bits.LongMode = !!(SegmentMode & 1);
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GdtEntry->Bits.Present = (Type != 0);
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GdtEntry->Bits.System = 0;
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GdtEntry->Bits.Type = (Type & 0x1F);
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GdtEntry->MustBeZero = 0;
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}
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/**
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* Fills in a call, interrupt, task or trap gate entry.
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*
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* @param Idt
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* Supplies a pointer to IDT structure, where gate is located.
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*
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* @param Vector
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* Supplies a gate vector pointing to the interrupt gate in the IDT
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*
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* @param Handler
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* Supplies a pointer to the interrupt handler of the specified gate.
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*
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* @param Selector
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* Supplies the code selector the gate should run in.
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*
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* @param Ist
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* Supplies the interrupt stack table entry the gate should run in.
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*
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* @param Access
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* Supplies the gate access rights.
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*
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* @return This routine does not return any value.
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*
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* @since XT 1.0
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*/
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XTAPI
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VOID
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ArpSetIdtGate(IN PKIDTENTRY Idt,
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IN USHORT Vector,
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IN PVOID Handler,
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IN USHORT Selector,
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IN USHORT Ist,
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IN USHORT Access)
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{
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/* Setup the gate */
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Idt[Vector].OffsetLow = (ULONG_PTR)Handler;
|
|
Idt[Vector].OffsetMiddle = ((ULONG_PTR)Handler >> 16);
|
|
Idt[Vector].OffsetHigh = (ULONG_PTR)Handler >> 32;
|
|
Idt[Vector].Dpl = Access;
|
|
Idt[Vector].IstIndex = Ist;
|
|
Idt[Vector].Present = 1;
|
|
Idt[Vector].Selector = Selector;
|
|
Idt[Vector].Type = 0xE;
|
|
}
|