513 lines
12 KiB
C
513 lines
12 KiB
C
/**
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* PROJECT: ExectOS
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* COPYRIGHT: See COPYING.md in the top level directory
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* FILE: xtoskrnl/ar/i686/cpufunc.c
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* DESCRIPTION: Routines to provide access to special i686 CPU instructions
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* DEVELOPERS: Rafal Kupiec <belliash@codingworkshop.eu.org>
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*/
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#include "xtkmapi.h"
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/**
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* Instructs the processor to clear the interrupt flag.
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*
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* @return This routine does not return any value.
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*
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* @since XT 1.0
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*/
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XTCDECL
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VOID
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ArClearInterruptFlag()
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{
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asm volatile("cli");
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}
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/**
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* Retrieves a various amount of information about the CPU.
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*
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* @param Registers
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* Supplies a pointer to the structure containing all the necessary registers and leafs for CPUID.
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*
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* @return TRUE if CPUID function could be executed, FALSE otherwise.
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*
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* @since XT 1.0
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*/
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XTCDECL
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BOOLEAN
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ArCpuId(IN OUT PCPUID_REGISTERS Registers)
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{
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UINT32 MaxLeaf;
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/* Get highest function ID available */
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asm volatile("cpuid"
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: "=a" (MaxLeaf)
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: "a" (Registers->Leaf & 0x80000000)
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: "rbx",
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"rcx",
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"rdx");
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/* Check if CPU supports this command */
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if(Registers->Leaf > MaxLeaf)
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{
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/* Cannot call it, return FALSE */
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return FALSE;
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}
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/* Execute CPUID function */
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asm volatile("cpuid"
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: "=a" (Registers->Eax),
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"=b" (Registers->Ebx),
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"=c" (Registers->Ecx),
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"=d" (Registers->Edx)
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: "a" (Registers->Leaf),
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"c" (Registers->SubLeaf));
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/* Return TRUE */
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return TRUE;
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}
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/**
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* Halts the central processing unit (CPU).
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*
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* @return This routine does not return any value.
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*
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* @since XT 1.0
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*/
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XTCDECL
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VOID
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ArHalt()
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{
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asm volatile("hlt");
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}
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/**
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* Invalidates the TLB (Translation Lookaside Buffer) for specified virtual address.
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*
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* @param Address
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* Suuplies a virtual address whose associated TLB entry will be invalidated.
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*
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* @return This routine does not return any value.
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*
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* @since XT 1.0
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*/
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XTCDECL
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VOID
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ArInvalidateTlbEntry(PVOID Address)
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{
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asm volatile("invlpg (%0)"
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:
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: "b" (Address)
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: "memory");
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}
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/**
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* Loads the values in the source operand into the global descriptor table register (GDTR).
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*
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* @param Source
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* Specifies a memory location that contains the base address of GDT.
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*
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* @return This routine does not return any value.
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*
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* @since XT 1.0
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*/
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XTCDECL
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VOID
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ArLoadGlobalDescriptorTable(IN PVOID Source)
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{
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asm volatile("lgdt %0"
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:
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: "m" (*(PSHORT)Source)
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: "memory");
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}
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/**
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* Loads the values in the source operand into the interrupt descriptor table register (IDTR).
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*
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* @param Source
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* Specifies a memory location that contains the base address of IDT.
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*
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* @return This routine does not return any value.
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*
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* @since XT 1.0
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*/
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XTCDECL
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VOID
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ArLoadInterruptDescriptorTable(IN PVOID Source)
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{
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asm volatile("lidt %0"
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:
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: "m" (*(PSHORT)Source)
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: "memory");
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}
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/**
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* Loads source data into specified segment.
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*
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* @param Segment
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* Supplies a segment identification.
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*
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* @param Source
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* Supplies a pointer to the memory area containing data that will be loaded into specified segment.
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*
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* @return This routine does not return any value.
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*
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* @since XT 1.0
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*/
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XTCDECL
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VOID
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ArLoadSegment(IN USHORT Segment,
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IN ULONG Source)
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{
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switch(Segment)
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{
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case SEGMENT_CS:
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asm volatile("movl %0, %%cs"
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:
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: "r" (Source));
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break;
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case SEGMENT_DS:
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asm volatile("movl %0, %%ds"
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:
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: "r" (Source));
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break;
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case SEGMENT_ES:
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asm volatile("movl %0, %%es"
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:
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: "r" (Source));
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break;
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case SEGMENT_FS:
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asm volatile("movl %0, %%fs"
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:
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: "r" (Source));
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break;
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case SEGMENT_GS:
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asm volatile("movl %0, %%gs"
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:
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: "r" (Source));
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break;
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case SEGMENT_SS:
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asm volatile("movl %0, %%ss"
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:
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: "r" (Source));
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break;
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}
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}
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/**
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* Loads Task Register (TR) with a segment selector that points to TSS.
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*
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* @param Source
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* Supplies the segment selector in the GDT describing the TSS.
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*
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* @return This routine does not return any value.
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*
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* @since XT 1.0
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*/
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XTCDECL
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VOID
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ArLoadTaskRegister(USHORT Source)
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{
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asm volatile("ltr %0"
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:
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: "rm" (Source));
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}
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/**
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* Reads the specified CPU control register and returns its value.
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*
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* @param ControlRegister
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* Supplies a number of a control register which controls the general behavior of a CPU.
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*
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* @return The value stored in the control register.
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*
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* @since XT 1.0
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*/
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XTCDECL
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ULONG_PTR
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ArReadControlRegister(IN USHORT ControlRegister)
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{
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ULONG_PTR Value;
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/* Read a value from specified CR register */
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switch(ControlRegister)
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{
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case 0:
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/* Read value from CR0 */
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asm volatile("mov %%cr0, %0"
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: "=r" (Value)
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:
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: "memory");
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break;
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case 2:
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/* Read value from CR2 */
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asm volatile("mov %%cr2, %0"
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: "=r" (Value)
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:
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: "memory");
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break;
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case 3:
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/* Read value from CR3 */
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asm volatile("mov %%cr3, %0"
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: "=r" (Value)
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:
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: "memory");
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break;
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case 4:
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/* Read value from CR4 */
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asm volatile("mov %%cr4, %0"
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: "=r" (Value)
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:
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: "memory");
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break;
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default:
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/* Invalid control register set */
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Value = 0;
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break;
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}
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/* Return value read from given CR register */
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return Value;
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}
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/**
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* Reads a 64-bit value from the requested Model Specific Register (MSR).
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*
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* @param Register
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* Supplies the MSR to read.
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*
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* @return This routine returns the 64-bit MSR value.
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*
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* @since XT 1.0
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*/
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XTCDECL
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ULONGLONG
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ArReadModelSpecificRegister(IN ULONG Register)
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{
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ULONGLONG Value;
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asm volatile("rdmsr"
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: "=A" (Value)
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: "c" (Register));
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return Value;
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}
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/**
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* Reads the current value of the CPU's time-stamp counter.
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*
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* @return This routine returns the current instruction cycle count since the processor was started.
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*
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* @since XT 1.0
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*/
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XTCDECL
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ULONGLONG
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ArReadTimeStampCounter()
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{
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ULONGLONG Value;
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asm volatile("rdtsc"
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: "=A" (Value));
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return Value;
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}
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/**
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* Instructs the processor to set the interrupt flag.
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*
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* @return This routine does not return any value.
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*
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* @since XT 1.0
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*/
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XTCDECL
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VOID
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ArSetInterruptFlag()
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{
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asm volatile("sti");
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}
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/**
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* Stores GDT register into the given memory area.
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*
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* @param Destination
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* Supplies a pointer to the memory area where GDT will be stored.
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*
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* @return This routine does not return any value.
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*
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* @since XT 1.0
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*/
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XTCDECL
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VOID
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ArStoreGlobalDescriptorTable(OUT PVOID Destination)
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{
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asm volatile("sgdt %0"
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:
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: "m" (*(PSHORT)Destination)
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: "memory");
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}
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/**
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* Stores IDT register into the given memory area.
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*
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* @param Destination
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* Supplies a pointer to the memory area where IDT will be stored.
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*
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* @return This routine does not return any value.
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*
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* @since XT 1.0
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*/
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XTCDECL
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VOID
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ArStoreInterruptDescriptorTable(OUT PVOID Destination)
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{
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asm volatile("sidt %0"
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:
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: "m" (*(PSHORT)Destination)
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: "memory");
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}
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/**
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* Stores specified segment into the given memory area.
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*
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* @param Segment
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* Supplies a segment identification.
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*
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* @param Destination
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* Supplies a pointer to the memory area where segment data will be stored.
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*
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* @return This routine does not return any value.
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*
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* @since XT 1.0
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*/
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XTCDECL
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VOID
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ArStoreSegment(IN USHORT Segment,
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OUT PVOID Destination)
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{
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switch(Segment)
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{
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case SEGMENT_CS:
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asm volatile("movl %%cs, %0"
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: "=r" (*(PUINT)Destination));
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break;
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case SEGMENT_DS:
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asm volatile("movl %%ds, %0"
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: "=r" (*(PUINT)Destination));
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break;
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case SEGMENT_ES:
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asm volatile("movl %%es, %0"
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: "=r" (*(PUINT)Destination));
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break;
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case SEGMENT_FS:
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asm volatile("movl %%fs, %0"
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: "=r" (*(PUINT)Destination));
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break;
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case SEGMENT_GS:
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asm volatile("movl %%gs, %0"
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: "=r" (*(PUINT)Destination));
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break;
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case SEGMENT_SS:
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asm volatile("movl %%ss, %0"
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: "=r" (*(PUINT)Destination));
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break;
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default:
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Destination = NULL;
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break;
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}
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}
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/**
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* Stores TR into the given memory area.
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*
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* @param Destination
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* Supplies a pointer to the memory area where TR will be stores.
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*
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* @return This routine does not return any value.
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*
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* @since XT 1.0
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*/
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XTCDECL
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VOID
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ArStoreTaskRegister(OUT PVOID Destination)
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{
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asm volatile("str %0"
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:
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: "m" (*(PULONG)Destination)
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: "memory");
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}
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/**
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* Writes a value to the specified CPU control register.
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*
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* @param ControlRegister
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* Supplies a number of a control register which controls the general behavior of a CPU.
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*
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* @param Value
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* Suplies a value to write to the CR register.
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*
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* @return This routine does not return any value.
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*
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* @since XT 1.0
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*/
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XTCDECL
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VOID
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ArWriteControlRegister(IN USHORT ControlRegister,
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IN UINT_PTR Value)
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{
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/* Write a value into specified control register */
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switch(ControlRegister)
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{
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case 0:
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/* Write value to CR0 */
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asm volatile("mov %0, %%cr0"
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:
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: "r" (Value)
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: "memory");
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break;
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case 2:
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/* Write value to CR2 */
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asm volatile("mov %0, %%cr2"
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:
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: "r" (Value)
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: "memory");
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break;
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case 3:
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/* Write value to CR3 */
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asm volatile("mov %0, %%cr3"
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:
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: "r" (Value)
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: "memory");
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break;
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case 4:
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/* Write value to CR4 */
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asm volatile("mov %0, %%cr4"
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:
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: "r" (Value)
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: "memory");
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break;
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}
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}
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/**
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* Writes a 64-bit value to the requested Model Specific Register (MSR).
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*
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* @param Register
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* Supplies the MSR register to write.
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*
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* @param Value
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* Supplies the 64-bit value to write.
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*
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* @return This routine does not return any value.
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*
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* @since XT 1.0
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*/
|
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XTCDECL
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VOID
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ArWriteModelSpecificRegister(IN ULONG Register,
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IN ULONGLONG Value)
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{
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asm volatile("wrmsr"
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:
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: "c" (Register),
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"A" (Value));
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}
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