241 lines
6.0 KiB
C
241 lines
6.0 KiB
C
/**
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* PROJECT: ExectOS
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* COPYRIGHT: See COPYING.md in the top level directory
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* FILE: xtoskrnl/hl/x86/pic.c
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* DESCRIPTION: Programmable Interrupt Controller (PIC) for x86 (i686/AMD64) support
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* DEVELOPERS: Rafal Kupiec <belliash@codingworkshop.eu.org>
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* Jozef Nagy <schkwve@gmail.com>
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*/
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#include <xtos.h>
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/**
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* Disables the legacy 8259 Programmable Interrupt Controller (PIC).
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*
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* @return This routine does not return any value.
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*
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* @since XT 1.0
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*/
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XTCDECL
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VOID
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HlDisablePic(VOID)
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{
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HlIoPortOutByte(PIC1_DATA_PORT, 0xFF);
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HlIoPortOutByte(PIC2_DATA_PORT, 0xFF);
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}
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/**
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* Reads from the APIC register.
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*
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* @param Register
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* Supplies the APIC register to read from.
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*
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* @return This routine returns the value read from the APIC register.
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*
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* @since XT 1.0
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*/
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XTFASTCALL
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ULONG
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HlReadApicRegister(IN APIC_REGISTER Register)
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{
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if(HlpApicMode == APIC_MODE_X2APIC)
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{
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/* Read from x2APIC MSR */
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return ArReadModelSpecificRegister((ULONG)(APIC_X2APIC_MSR_BASE + Register));
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}
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else
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{
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/* Read from xAPIC */
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return RtlReadRegisterLong((PULONG)(APIC_BASE + (Register << 4)));
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}
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}
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/**
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* Writes to the APIC register.
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*
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* @param Register
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* Supplies the APIC register to write to.
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*
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* @param Value
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* Supplies the value to write to the APIC register.
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*
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* @return This routine does not return any value.
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*
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* @since XT 1.0
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*/
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XTFASTCALL
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VOID
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HlWriteApicRegister(IN APIC_REGISTER Register,
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IN ULONG Value)
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{
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if(HlpApicMode == APIC_MODE_X2APIC)
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{
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/* Write to x2APIC MSR */
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ArWriteModelSpecificRegister((ULONG)(APIC_X2APIC_MSR_BASE + Register), Value);
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}
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else
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{
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/* Write to xAPIC */
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RtlWriteRegisterLong((PULONG)(APIC_BASE + (Register << 4)), Value);
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}
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}
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/**
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* Checks whether the x2APIC extension is supported by the processor.
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*
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* @return This routine returns TRUE if x2APIC is supported, or FALSE otherwise.
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*
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* @since XT 1.0
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*
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* @todo Check if bits 0 and 1 of DMAR ACPI table flags are set after implementing ACPI support.
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* Intel VT-d spec says x2apic should not be enabled if they are.
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*/
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XTAPI
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BOOLEAN
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HlpCheckX2ApicSupport(VOID)
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{
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CPUID_REGISTERS CpuRegisters;
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/* Prepare CPUID registers */
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CpuRegisters.Leaf = CPUID_GET_CPU_FEATURES;
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CpuRegisters.SubLeaf = 0;
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CpuRegisters.Eax = 0;
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CpuRegisters.Ebx = 0;
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CpuRegisters.Ecx = 0;
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CpuRegisters.Edx = 0;
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/* Get CPUID */
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ArCpuId(&CpuRegisters);
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/* Check x2APIC status from the CPUID results */
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if(!(CpuRegisters.Ecx & CPUID_FEATURES_ECX_X2APIC))
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{
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/* x2APIC is not supported */
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return FALSE;
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}
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/* x2APIC is supported */
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return TRUE;
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}
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/**
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* Allows an APIC spurious interrupts to end up.
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*
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* @return This routine does not return any value.
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*
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* @since XT 1.0
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*/
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XTCDECL
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VOID
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HlpHandleApicSpuriousService()
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{
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}
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/**
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* Allows a PIC spurious interrupts to end up.
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*
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* @return This routine does not return any value.
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*
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* @since XT 1.0
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*/
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XTCDECL
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VOID
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HlpHandlePicSpuriousService()
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{
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}
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/**
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* Initializes the APIC interrupt controller.
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*
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* @return This routine does not return any value.
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*
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* @since XT 1.0
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*
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* @todo Register interrupt handlers for spurious vectors.
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*/
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XTAPI
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VOID
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HlpInitializeApic(VOID)
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{
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APIC_BASE_REGISTER BaseRegister;
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APIC_LVT_REGISTER LvtRegister;
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APIC_SPURIOUS_REGISTER SpuriousRegister;
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ULONG CpuNumber = 0;
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/* Check if this is an x2APIC compatible machine */
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if(HlpCheckX2ApicSupport())
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{
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/* Enable x2APIC */
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HlpApicMode = APIC_MODE_X2APIC;
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}
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else
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{
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/* Use xAPIC compatibility mode */
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HlpApicMode = APIC_MODE_COMPAT;
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}
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/* Enable the APIC */
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BaseRegister.LongLong = ArReadModelSpecificRegister(APIC_LAPIC_MSR_BASE);
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BaseRegister.Enable = 1;
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BaseRegister.ExtendedMode = (HlpApicMode == APIC_MODE_X2APIC);
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BaseRegister.BootStrapProcessor = 1;
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ArWriteModelSpecificRegister(APIC_LAPIC_MSR_BASE, BaseRegister.LongLong);
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/* xAPIC compatibility mode specific initialization */
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if(HlpApicMode == APIC_MODE_COMPAT)
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{
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/* Initialize Destination Format Register with flat model */
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HlWriteApicRegister(APIC_DFR, APIC_DF_FLAT);
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/* Set the logical APIC ID */
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HlWriteApicRegister(APIC_LDR, (1UL << CpuNumber) << 24);
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}
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/* Set the spurious interrupt vector */
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SpuriousRegister.Long = HlReadApicRegister(APIC_SIVR);
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SpuriousRegister.Vector = APIC_VECTOR_SPURIOUS;
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SpuriousRegister.SoftwareEnable = 1;
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SpuriousRegister.CoreChecking = 0;
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HlWriteApicRegister(APIC_SIVR, SpuriousRegister.Long);
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/* Initialize Logical Vector Table */
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LvtRegister.Long = 0;
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LvtRegister.Vector = APIC_VECTOR_NMI;
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LvtRegister.MessageType = APIC_DM_FIXED;
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LvtRegister.DeliveryStatus = 0;
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LvtRegister.RemoteIRR = 0;
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LvtRegister.TriggerMode = APIC_TGM_EDGE;
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LvtRegister.Mask = 0;
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LvtRegister.TimerMode = 0;
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/* Mask LVT tables */
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HlWriteApicRegister(APIC_TMRLVTR, LvtRegister.Long);
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HlWriteApicRegister(APIC_THRMLVTR, LvtRegister.Long);
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HlWriteApicRegister(APIC_PCLVTR, LvtRegister.Long);
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/* Mask LINT0 */
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LvtRegister.Vector = APIC_VECTOR_SPURIOUS;
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LvtRegister.MessageType = APIC_DM_EXTINT;
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HlWriteApicRegister(APIC_LINT0, LvtRegister.Long);
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/* Mask LINT1 */
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LvtRegister.Mask = 0;
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LvtRegister.Vector = APIC_VECTOR_NMI;
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LvtRegister.MessageType = APIC_DM_NMI;
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LvtRegister.TriggerMode = APIC_TGM_LEVEL;
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HlWriteApicRegister(APIC_LINT1, LvtRegister.Long);
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/* Mask LVTR_ERROR */
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LvtRegister.Vector = APIC_VECTOR_ERROR;
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LvtRegister.MessageType = APIC_DM_FIXED;
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HlWriteApicRegister(APIC_ERRLVTR, LvtRegister.Long);
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/* Clear errors after enabling vectors */
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HlWriteApicRegister(APIC_ESR, 0);
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/* Register interrupt handlers once the APIC initialization is done */
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KeSetInterruptHandler(APIC_VECTOR_SPURIOUS, HlpHandleApicSpuriousService);
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KeSetInterruptHandler(PIC1_VECTOR_SPURIOUS, HlpHandlePicSpuriousService);
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}
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