662 lines
22 KiB
C++
662 lines
22 KiB
C++
/**
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* PROJECT: ExectOS
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* COPYRIGHT: See COPYING.md in the top level directory
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* FILE: xtoskrnl/ar/amd64/procsup.cc
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* DESCRIPTION: AMD64 processor functionality support
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* DEVELOPERS: Rafal Kupiec <belliash@codingworkshop.eu.org>
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*/
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#include <xtos.hh>
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/**
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* Gets the base address of the kernel boot stack.
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*
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* @return This routine returns a pointer to the kernel boot stack.
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*
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* @since XT 1.0
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*/
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XTAPI
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PVOID
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AR::ProcSup::GetBootStack(VOID)
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{
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return (PVOID)BootStack;
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}
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XTAPI
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VOID
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AR::ProcSup::GetTrampolineInformation(IN TRAMPOLINE_TYPE TrampolineType,
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OUT PVOID *TrampolineCode,
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OUT PULONG_PTR TrampolineSize)
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{
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switch(TrampolineType)
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{
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case TrampolineApStartup:
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*TrampolineCode = (PVOID)ArStartApplicationProcessor;
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*TrampolineSize = (ULONG_PTR)ArStartApplicationProcessorEnd -
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(ULONG_PTR)ArStartApplicationProcessor;
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break;
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case TrampolineEnableXpa:
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*TrampolineCode = (PVOID)ArEnableExtendedPhysicalAddressing;
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*TrampolineSize = (ULONG_PTR)ArEnableExtendedPhysicalAddressingEnd -
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(ULONG_PTR)ArEnableExtendedPhysicalAddressing;
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break;
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default:
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*TrampolineCode = NULLPTR;
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*TrampolineSize = 0;
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break;
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}
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}
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/**
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* Identifies processor type (vendor, model, stepping) as well as looks for available CPU features and stores them
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* in Processor Control Block (PRCB).
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*
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* @return This routine does not return any value.
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*
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* @since XT 1.0
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*/
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XTAPI
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VOID
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AR::ProcSup::IdentifyProcessor(VOID)
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{
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PKPROCESSOR_CONTROL_BLOCK Prcb;
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CPUID_REGISTERS CpuRegisters;
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CPUID_SIGNATURE CpuSignature;
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/* Not fully implemented yet */
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UNIMPLEMENTED;
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/* Get current processor control block */
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Prcb = KE::Processor::GetCurrentProcessorControlBlock();
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/* Get CPU vendor by issueing CPUID instruction */
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RtlZeroMemory(&CpuRegisters, sizeof(CPUID_REGISTERS));
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CpuRegisters.Leaf = CPUID_GET_VENDOR_STRING;
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CpuFunc::CpuId(&CpuRegisters);
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/* Store CPU vendor in processor control block */
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Prcb->CpuId.Vendor = (CPU_VENDOR)CpuRegisters.Ebx;
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*(PULONG)&Prcb->CpuId.VendorName[0] = CpuRegisters.Ebx;
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*(PULONG)&Prcb->CpuId.VendorName[4] = CpuRegisters.Edx;
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*(PULONG)&Prcb->CpuId.VendorName[8] = CpuRegisters.Ecx;
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Prcb->CpuId.VendorName[12] = '\0';
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/* Get CPU standard features */
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RtlZeroMemory(&CpuRegisters, sizeof(CPUID_REGISTERS));
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CpuRegisters.Leaf = CPUID_GET_STANDARD1_FEATURES;
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CpuFunc::CpuId(&CpuRegisters);
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/* Store CPU signature in processor control block */
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CpuSignature = *(PCPUID_SIGNATURE)&CpuRegisters.Eax;
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Prcb->CpuId.Family = CpuSignature.Family;
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Prcb->CpuId.Model = CpuSignature.Model;
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Prcb->CpuId.Stepping = CpuSignature.Stepping;
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/* CPU vendor specific quirks */
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if(Prcb->CpuId.Vendor == CPU_VENDOR_AMD)
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{
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/* AMD CPU */
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if(Prcb->CpuId.Family >= 0xF)
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{
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Prcb->CpuId.Family = Prcb->CpuId.Family + CpuSignature.ExtendedFamily;
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Prcb->CpuId.Model = Prcb->CpuId.Model + (CpuSignature.ExtendedModel << 4);
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}
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}
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else if(Prcb->CpuId.Vendor == CPU_VENDOR_INTEL)
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{
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/* Intel CPU */
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if(Prcb->CpuId.Family == 0xF)
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{
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Prcb->CpuId.Family = Prcb->CpuId.Family + CpuSignature.ExtendedFamily;
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}
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if((Prcb->CpuId.Family == 0x6) || (Prcb->CpuId.Family == 0xF))
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{
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Prcb->CpuId.Model = Prcb->CpuId.Model + (CpuSignature.ExtendedModel << 4);
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}
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}
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else
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{
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/* Unknown CPU vendor */
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Prcb->CpuId.Vendor = CPU_VENDOR_UNKNOWN;
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}
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/* TODO: Store a list of CPU features in processor control block */
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}
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/**
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* Initializes AMD64 processor specific structures.
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*
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* @return This routine does not return any value.
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*
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* @since XT 1.0
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*/
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XTAPI
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VOID
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AR::ProcSup::InitializeProcessor(IN PVOID ProcessorStructures)
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{
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KDESCRIPTOR GdtDescriptor, IdtDescriptor;
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PVOID KernelBootStack, KernelFaultStack;
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PKPROCESSOR_BLOCK ProcessorBlock;
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PKGDTENTRY Gdt;
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PKIDTENTRY Idt;
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PKTSS Tss;
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/* Check if processor structures buffer provided */
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if(ProcessorStructures)
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{
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/* Assign CPU structures from provided buffer */
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InitializeProcessorStructures(ProcessorStructures, &Gdt, &Tss, &ProcessorBlock,
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&KernelBootStack, &KernelFaultStack);
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/* Use global IDT */
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Idt = InitialIdt;
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}
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else
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{
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/* Use initial structures */
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Gdt = InitialGdt;
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Idt = InitialIdt;
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Tss = &InitialTss;
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KernelBootStack = &BootStack;
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KernelFaultStack = &FaultStack;
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ProcessorBlock = &InitialProcessorBlock;
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}
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/* Initialize processor block */
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InitializeProcessorBlock(ProcessorBlock, Gdt, Idt, Tss, KernelFaultStack);
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/* Initialize GDT, IDT and TSS */
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InitializeGdt(ProcessorBlock);
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InitializeIdt(ProcessorBlock);
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InitializeTss(ProcessorBlock, KernelBootStack, KernelFaultStack);
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/* Set GDT and IDT descriptors */
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GdtDescriptor.Base = Gdt;
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GdtDescriptor.Limit = (GDT_ENTRIES * sizeof(KGDTENTRY)) - 1;
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IdtDescriptor.Base = Idt;
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IdtDescriptor.Limit = (IDT_ENTRIES * sizeof(KIDTENTRY)) - 1;
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/* Load GDT, IDT and TSS */
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CpuFunc::LoadGlobalDescriptorTable(&GdtDescriptor.Limit);
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CpuFunc::LoadInterruptDescriptorTable(&IdtDescriptor.Limit);
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CpuFunc::LoadTaskRegister((UINT)KGDT_SYS_TSS);
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/* Enter passive IRQ level */
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HL::RunLevel::SetRunLevel(PASSIVE_LEVEL);
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/* Initialize segment registers */
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InitializeSegments();
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/* Set GS base */
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CpuFunc::WriteModelSpecificRegister(X86_MSR_GSBASE, (ULONGLONG)ProcessorBlock);
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CpuFunc::WriteModelSpecificRegister(X86_MSR_KERNEL_GSBASE, (ULONGLONG)ProcessorBlock);
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/* Initialize processor registers */
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InitializeProcessorRegisters();
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/* Identify processor */
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IdentifyProcessor();
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}
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/**
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* Initializes the kernel's Global Descriptor Table (GDT).
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*
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* @param Gdt
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* Supplies a pointer to the GDT to use.
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*
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* @return This routine does not return any value.
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*
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* @since XT 1.0
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*/
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XTAPI
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VOID
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AR::ProcSup::InitializeGdt(IN PKPROCESSOR_BLOCK ProcessorBlock)
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{
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/* Initialize GDT entries */
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SetGdtEntry(ProcessorBlock->GdtBase, KGDT_NULL, 0x0, 0x0, KGDT_TYPE_NONE, KGDT_DPL_SYSTEM, 1);
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SetGdtEntry(ProcessorBlock->GdtBase, KGDT_R0_CODE, 0x0, 0x0, KGDT_TYPE_CODE, KGDT_DPL_SYSTEM, 1);
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SetGdtEntry(ProcessorBlock->GdtBase, KGDT_R0_DATA, 0x0, 0x0, KGDT_TYPE_DATA, KGDT_DPL_SYSTEM, 1);
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SetGdtEntry(ProcessorBlock->GdtBase, KGDT_R3_CMCODE, 0x0, 0xFFFFFFFF, KGDT_TYPE_CODE, KGDT_DPL_USER, 2);
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SetGdtEntry(ProcessorBlock->GdtBase, KGDT_R3_DATA, 0x0, 0xFFFFFFFF, KGDT_TYPE_DATA, KGDT_DPL_USER, 2);
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SetGdtEntry(ProcessorBlock->GdtBase, KGDT_R3_CODE, 0x0, 0x0, KGDT_TYPE_CODE, KGDT_DPL_USER, 1);
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SetGdtEntry(ProcessorBlock->GdtBase, KGDT_SYS_TSS, (ULONG_PTR)ProcessorBlock->TssBase,
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sizeof(KTSS) - 1, AMD64_TSS, KGDT_DPL_SYSTEM, 0);
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SetGdtEntry(ProcessorBlock->GdtBase, KGDT_R3_CMTEB, 0x0, 0x0FFF, KGDT_TYPE_DATA, KGDT_DPL_USER, 2);
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SetGdtEntry(ProcessorBlock->GdtBase, KGDT_R0_LDT, 0x0, 0xFFFFFFFF, KGDT_TYPE_CODE, KGDT_DPL_SYSTEM, 0);
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SetGdtEntry(ProcessorBlock->GdtBase, KGDT_ALIAS, (ULONG_PTR)ProcessorBlock->GdtBase,
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(GDT_ENTRIES * sizeof(KGDTENTRY)) - 1, KGDT_TYPE_DATA, KGDT_DPL_SYSTEM, 0);
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}
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/**
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* Initializes the kernel's Interrupt Descriptor Table (IDT).
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*
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* @param ProcessorBlock
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* Supplies a pointer to the processor block to use.
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*
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* @return This routine does not return any value.
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*
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* @since XT 1.0
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*/
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XTAPI
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VOID
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AR::ProcSup::InitializeIdt(IN PKPROCESSOR_BLOCK ProcessorBlock)
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{
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UINT Vector;
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/* Fill in all vectors */
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for(Vector = 0; Vector < IDT_ENTRIES; Vector++)
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{
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/* Set the IDT to handle unexpected interrupts */
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SetIdtGate(ProcessorBlock->IdtBase, Vector, (PVOID)ArTrap0xFF, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0);
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}
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/* Setup IDT handlers for known interrupts and traps */
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SetIdtGate(ProcessorBlock->IdtBase, 0x00, (PVOID)ArTrap0x00, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0);
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SetIdtGate(ProcessorBlock->IdtBase, 0x01, (PVOID)ArTrap0x01, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0);
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SetIdtGate(ProcessorBlock->IdtBase, 0x02, (PVOID)ArTrap0x02, KGDT_R0_CODE, KIDT_IST_PANIC, KIDT_ACCESS_RING0);
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SetIdtGate(ProcessorBlock->IdtBase, 0x03, (PVOID)ArTrap0x03, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING3);
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SetIdtGate(ProcessorBlock->IdtBase, 0x04, (PVOID)ArTrap0x04, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING3);
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SetIdtGate(ProcessorBlock->IdtBase, 0x05, (PVOID)ArTrap0x05, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0);
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SetIdtGate(ProcessorBlock->IdtBase, 0x06, (PVOID)ArTrap0x06, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0);
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SetIdtGate(ProcessorBlock->IdtBase, 0x07, (PVOID)ArTrap0x07, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0);
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SetIdtGate(ProcessorBlock->IdtBase, 0x08, (PVOID)ArTrap0x08, KGDT_R0_CODE, KIDT_IST_PANIC, KIDT_ACCESS_RING0);
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SetIdtGate(ProcessorBlock->IdtBase, 0x09, (PVOID)ArTrap0x09, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0);
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SetIdtGate(ProcessorBlock->IdtBase, 0x0A, (PVOID)ArTrap0x0A, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0);
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SetIdtGate(ProcessorBlock->IdtBase, 0x0B, (PVOID)ArTrap0x0B, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0);
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SetIdtGate(ProcessorBlock->IdtBase, 0x0C, (PVOID)ArTrap0x0C, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0);
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SetIdtGate(ProcessorBlock->IdtBase, 0x0D, (PVOID)ArTrap0x0D, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0);
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SetIdtGate(ProcessorBlock->IdtBase, 0x0E, (PVOID)ArTrap0x0E, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0);
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SetIdtGate(ProcessorBlock->IdtBase, 0x10, (PVOID)ArTrap0x10, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0);
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SetIdtGate(ProcessorBlock->IdtBase, 0x11, (PVOID)ArTrap0x11, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0);
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SetIdtGate(ProcessorBlock->IdtBase, 0x12, (PVOID)ArTrap0x12, KGDT_R0_CODE, KIDT_IST_MCA, KIDT_ACCESS_RING0);
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SetIdtGate(ProcessorBlock->IdtBase, 0x13, (PVOID)ArTrap0x13, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0);
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SetIdtGate(ProcessorBlock->IdtBase, 0x1F, (PVOID)ArTrap0x1F, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0);
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SetIdtGate(ProcessorBlock->IdtBase, 0x2C, (PVOID)ArTrap0x2C, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING3);
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SetIdtGate(ProcessorBlock->IdtBase, 0x2D, (PVOID)ArTrap0x2D, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING3);
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SetIdtGate(ProcessorBlock->IdtBase, 0x2F, (PVOID)ArTrap0x2F, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0);
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SetIdtGate(ProcessorBlock->IdtBase, 0xE1, (PVOID)ArTrap0xE1, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0);
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}
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/**
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* Initializes processor block.
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*
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* @param ProcessorBlock
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* Supplies a pointer to the processor block to initialize.
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*
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* @param Gdt
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* Supplies a pointer to the GDT for this processor block.
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*
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* @param Idt
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* Supplies a pointer to the IDT for this processor block.
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*
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* @param Tss
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* Supplies a pointer to the TSS for this processor block.
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*
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* @return This routine does not return any value.
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*
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* @since XT 1.0
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*/
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XTAPI
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VOID
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AR::ProcSup::InitializeProcessorBlock(OUT PKPROCESSOR_BLOCK ProcessorBlock,
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IN PKGDTENTRY Gdt,
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IN PKIDTENTRY Idt,
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IN PKTSS Tss,
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IN PVOID DpcStack)
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{
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/* Set processor block and processor control block */
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ProcessorBlock->Self = ProcessorBlock;
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ProcessorBlock->CurrentPrcb = &ProcessorBlock->Prcb;
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/* Set GDT, IDT and TSS descriptors */
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ProcessorBlock->GdtBase = (PKGDTENTRY)(PVOID)Gdt;
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ProcessorBlock->IdtBase = Idt;
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ProcessorBlock->TssBase = Tss;
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ProcessorBlock->Prcb.RspBase = Tss->Rsp0;
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/* Setup DPC stack */
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ProcessorBlock->Prcb.DpcStack = DpcStack;
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/* Setup processor control block */
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ProcessorBlock->Prcb.CpuNumber = ProcessorBlock->CpuNumber;
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ProcessorBlock->Prcb.SetMember = 1ULL << ProcessorBlock->CpuNumber;
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ProcessorBlock->Prcb.MultiThreadProcessorSet = 1ULL << ProcessorBlock->CpuNumber;
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/* Clear DR6 and DR7 registers */
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ProcessorBlock->Prcb.ProcessorState.SpecialRegisters.KernelDr6 = 0;
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ProcessorBlock->Prcb.ProcessorState.SpecialRegisters.KernelDr7 = 0;
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/* Set process and thread information */
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ProcessorBlock->Prcb.CurrentThread = &(KE::KThread::GetInitialThread())->ThreadControlBlock;
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ProcessorBlock->Prcb.CurrentThread->ApcState.Process = &(KE::KProcess::GetInitialProcess())->ProcessControlBlock;
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ProcessorBlock->Prcb.IdleThread = &(KE::KThread::GetInitialThread())->ThreadControlBlock;
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ProcessorBlock->Prcb.NextThread = NULLPTR;
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/* Set initial MXCSR register value */
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ProcessorBlock->Prcb.MxCsr = INITIAL_MXCSR;
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/* Set initial runlevel */
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ProcessorBlock->RunLevel = PASSIVE_LEVEL;
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}
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/**
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* Initializes processor registers and other boot structures.
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*
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* @return This routine does not return any value.
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*
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* @since XT 1.0
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*/
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XTAPI
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VOID
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AR::ProcSup::InitializeProcessorRegisters(VOID)
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{
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ULONGLONG PatAttributes;
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/* Enable FXSAVE restore */
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CpuFunc::WriteControlRegister(4, CpuFunc::ReadControlRegister(4) | CR4_FXSR);
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/* Enable XMMI exceptions */
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CpuFunc::WriteControlRegister(4, CpuFunc::ReadControlRegister(4) | CR4_XMMEXCPT);
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/* Set debugger extension */
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CpuFunc::WriteControlRegister(4, CpuFunc::ReadControlRegister(4) | CR4_DE);
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/* Enable large pages */
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CpuFunc::WriteControlRegister(4, CpuFunc::ReadControlRegister(4) | CR4_PSE);
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/* Enable write-protection */
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CpuFunc::WriteControlRegister(0, CpuFunc::ReadControlRegister(0) | CR0_WP);
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/* Set alignment mask */
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CpuFunc::WriteControlRegister(0, CpuFunc::ReadControlRegister(0) | CR0_AM);
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/* Disable FPU monitoring */
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CpuFunc::WriteControlRegister(0, CpuFunc::ReadControlRegister(0) & ~CR0_MP);
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/* Disable x87 FPU exceptions */
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CpuFunc::WriteControlRegister(0, CpuFunc::ReadControlRegister(0) & ~CR0_NE);
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/* Flush the TLB */
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CpuFunc::FlushTlb();
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/* Initialize system call MSRs */
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Traps::InitializeSystemCallMsrs();
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/* Enable No-Execute (NXE) in EFER MSR */
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CpuFunc::WriteModelSpecificRegister(X86_MSR_EFER, CpuFunc::ReadModelSpecificRegister(X86_MSR_EFER) | X86_MSR_EFER_NXE);
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/* Initialize Page Attribute Table */
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PatAttributes = (PAT_TYPE_WB << 0) | (PAT_TYPE_USWC << 8) | (PAT_TYPE_WEAK_UC << 16) | (PAT_TYPE_STRONG_UC << 24) |
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(PAT_TYPE_WB << 32) | (PAT_TYPE_USWC << 40) | (PAT_TYPE_WEAK_UC << 48) | (PAT_TYPE_STRONG_UC << 56);
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CpuFunc::WriteModelSpecificRegister(X86_MSR_PAT, PatAttributes);
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/* Initialize MXCSR register */
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CpuFunc::LoadMxcsrRegister(INITIAL_MXCSR);
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}
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/**
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* Initializes i686 processor specific structures with provided memory buffer.
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*
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* @param ProcessorStructures
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* Supplies a pointer to the allocated buffer with processor structures.
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*
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* @param Gdt
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* Supplies a pointer to the GDT.
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*
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* @param Tss
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* Supplies a pointer to the TSS.
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*
|
|
* @param ProcessorBlock
|
|
* Supplies a pointer to the processor block.
|
|
*
|
|
* @param KernelBootStack
|
|
* Supplies a pointer to the kernel boot stack.
|
|
*
|
|
* @param KernelFaultStack
|
|
* Supplies a pointer to the kernel fault stack.
|
|
*
|
|
* @return This routine does not return any value.
|
|
*
|
|
* @since XT 1.0
|
|
*/
|
|
XTAPI
|
|
VOID
|
|
AR::ProcSup::InitializeProcessorStructures(IN PVOID ProcessorStructures,
|
|
OUT PKGDTENTRY *Gdt,
|
|
OUT PKTSS *Tss,
|
|
OUT PKPROCESSOR_BLOCK *ProcessorBlock,
|
|
OUT PVOID *KernelBootStack,
|
|
OUT PVOID *KernelFaultStack)
|
|
{
|
|
UINT_PTR Address;
|
|
|
|
/* Align address to page size boundary and move to kernel boot stack */
|
|
Address = ROUND_UP((UINT_PTR)ProcessorStructures, MM_PAGE_SIZE) + KERNEL_STACK_SIZE;
|
|
|
|
/* Assign a space for kernel boot stack and advance */
|
|
*KernelBootStack = (PVOID)Address;
|
|
Address += KERNEL_STACK_SIZE;
|
|
|
|
/* Assign a space for kernel fault stack, no advance needed as stack grows down */
|
|
*KernelFaultStack = (PVOID)Address;
|
|
|
|
/* Assign a space for GDT and advance */
|
|
*Gdt = (PKGDTENTRY)(PVOID)Address;
|
|
Address += sizeof(InitialGdt);
|
|
|
|
/* Assign a space for Processor Block and advance */
|
|
*ProcessorBlock = (PKPROCESSOR_BLOCK)(PVOID)Address;
|
|
Address += sizeof(InitialProcessorBlock);
|
|
|
|
/* Assign a space for TSS */
|
|
*Tss = (PKTSS)(PVOID)Address;
|
|
}
|
|
|
|
/**
|
|
* Initializes segment registers.
|
|
*
|
|
* @return This routine does not return any value.
|
|
*
|
|
* @since XT 1.0
|
|
*/
|
|
XTAPI
|
|
VOID
|
|
AR::ProcSup::InitializeSegments(VOID)
|
|
{
|
|
/* Initialize segments */
|
|
CpuFunc::LoadSegment(SEGMENT_CS, KGDT_R0_CODE);
|
|
CpuFunc::LoadSegment(SEGMENT_DS, KGDT_R3_DATA | RPL_MASK);
|
|
CpuFunc::LoadSegment(SEGMENT_ES, KGDT_R3_DATA | RPL_MASK);
|
|
CpuFunc::LoadSegment(SEGMENT_FS, KGDT_R3_CMTEB | RPL_MASK);
|
|
CpuFunc::LoadSegment(SEGMENT_GS, KGDT_R3_DATA | RPL_MASK);
|
|
CpuFunc::LoadSegment(SEGMENT_SS, KGDT_R0_DATA);
|
|
}
|
|
|
|
/**
|
|
* Initializes the kernel's Task State Segment (TSS).
|
|
*
|
|
* @param Tss
|
|
* Supplies a pointer to the TSS to use.
|
|
*
|
|
* @param Gdt
|
|
* Supplies a pointer to the GDT to use.
|
|
*
|
|
* @return This routine does not return any value.
|
|
*
|
|
* @since XT 1.0
|
|
*/
|
|
XTAPI
|
|
VOID
|
|
AR::ProcSup::InitializeTss(IN PKPROCESSOR_BLOCK ProcessorBlock,
|
|
IN PVOID KernelBootStack,
|
|
IN PVOID KernelFaultStack)
|
|
{
|
|
/* Fill TSS with zeroes */
|
|
RtlZeroMemory(ProcessorBlock->TssBase, sizeof(KTSS));
|
|
|
|
/* Setup I/O map and stacks for ring0 & traps */
|
|
ProcessorBlock->TssBase->IoMapBase = sizeof(KTSS);
|
|
ProcessorBlock->TssBase->Rsp0 = (ULONG_PTR)KernelBootStack;
|
|
ProcessorBlock->TssBase->Ist[KIDT_IST_PANIC] = (ULONG_PTR)KernelFaultStack;
|
|
ProcessorBlock->TssBase->Ist[KIDT_IST_MCA] = (ULONG_PTR)KernelFaultStack;
|
|
}
|
|
|
|
/**
|
|
* Fills in an AMD64 GDT entry.
|
|
*
|
|
* @param Gdt
|
|
* Supplies a pointer to the GDT.
|
|
*
|
|
* @param Selector
|
|
* Specifies a segment selector of the GDT entry.
|
|
*
|
|
* @param Base
|
|
* Specifies a base address value of the descriptor.
|
|
*
|
|
* @param Limit
|
|
* Specifies a descriptor limit.
|
|
*
|
|
* @param Type
|
|
* Specifies a type of the descriptor.
|
|
*
|
|
* @param Dpl
|
|
* Specifies the descriptor privilege level.
|
|
*
|
|
* @param SegmentMode
|
|
* Specifies a segment mode of the descriptor.
|
|
*
|
|
* @return This routine does not return any value
|
|
*
|
|
* @since XT 1.0
|
|
*/
|
|
XTAPI
|
|
VOID
|
|
AR::ProcSup::SetGdtEntry(IN PKGDTENTRY Gdt,
|
|
IN USHORT Selector,
|
|
IN ULONG_PTR Base,
|
|
IN ULONG Limit,
|
|
IN UCHAR Type,
|
|
IN UCHAR Dpl,
|
|
IN UCHAR SegmentMode)
|
|
{
|
|
PKGDTENTRY GdtEntry;
|
|
UCHAR Granularity;
|
|
|
|
/* Set the granularity flag depending on descriptor limit */
|
|
if(Limit < 0x100000)
|
|
{
|
|
/* Limit is in 1B blocks */
|
|
Granularity = 0;
|
|
}
|
|
else
|
|
{
|
|
/* Limit is in 4KB blocks */
|
|
Granularity = 1;
|
|
Limit >>= 12;
|
|
}
|
|
|
|
/* Get GDT entry */
|
|
GdtEntry = (PKGDTENTRY)((ULONG_PTR)Gdt + (Selector & ~RPL_MASK));
|
|
|
|
/* Set GDT descriptor base */
|
|
GdtEntry->BaseLow = (Base & 0xFFFF);
|
|
GdtEntry->Bytes.BaseMiddle = ((Base >> 16) & 0xFF);
|
|
GdtEntry->Bytes.BaseHigh = ((Base >> 24) & 0xFF);
|
|
GdtEntry->BaseUpper = (Base >> 32);
|
|
|
|
/* Set descriptor limit */
|
|
GdtEntry->LimitLow = (Limit & 0xFFFF);
|
|
GdtEntry->Bits.LimitHigh = ((Limit >> 16) & 0xF);
|
|
|
|
/* Initialize GDT entry */
|
|
GdtEntry->Bits.DefaultBig = !!(SegmentMode & 2);
|
|
GdtEntry->Bits.Dpl = (Dpl & 0x3);
|
|
GdtEntry->Bits.Granularity = Granularity;
|
|
GdtEntry->Bits.LongMode = !!(SegmentMode & 1);
|
|
GdtEntry->Bits.Present = (Type != 0);
|
|
GdtEntry->Bits.System = 0;
|
|
GdtEntry->Bits.Type = (Type & 0x1F);
|
|
GdtEntry->MustBeZero = 0;
|
|
}
|
|
|
|
/**
|
|
* Updates an existing AMD64 GDT entry with new base address.
|
|
*
|
|
* @param Gdt
|
|
* Supplies a pointer to the GDT.
|
|
*
|
|
* @param Selector
|
|
* Specifies a segment selector of the GDT entry.
|
|
*
|
|
* @param Base
|
|
* Specifies a base address value of the descriptor.
|
|
*
|
|
* @return This routine does not return any value.
|
|
*
|
|
* @since XT 1.0
|
|
*/
|
|
XTAPI
|
|
VOID
|
|
AR::ProcSup::SetGdtEntryBase(IN PKGDTENTRY Gdt,
|
|
IN USHORT Selector,
|
|
IN ULONG_PTR Base)
|
|
{
|
|
PKGDTENTRY GdtEntry;
|
|
|
|
/* Get GDT entry */
|
|
GdtEntry = (PKGDTENTRY)((ULONG_PTR)Gdt + (Selector & ~RPL_MASK));
|
|
|
|
/* Set new GDT descriptor base */
|
|
GdtEntry->BaseLow = (Base & 0xFFFF);
|
|
GdtEntry->Bytes.BaseMiddle = ((Base >> 16) & 0xFF);
|
|
GdtEntry->Bytes.BaseHigh = ((Base >> 24) & 0xFF);
|
|
GdtEntry->BaseUpper = (Base >> 32);
|
|
}
|
|
|
|
/**
|
|
* Fills in a call, interrupt, task or trap gate entry.
|
|
*
|
|
* @param Idt
|
|
* Supplies a pointer to IDT structure, where gate is located.
|
|
*
|
|
* @param Vector
|
|
* Supplies a gate vector pointing to the interrupt gate in the IDT
|
|
*
|
|
* @param Handler
|
|
* Supplies a pointer to the interrupt handler of the specified gate.
|
|
*
|
|
* @param Selector
|
|
* Supplies the code selector the gate should run in.
|
|
*
|
|
* @param Ist
|
|
* Supplies the interrupt stack table entry the gate should run in.
|
|
*
|
|
* @param Access
|
|
* Supplies the gate access rights.
|
|
*
|
|
* @return This routine does not return any value.
|
|
*
|
|
* @since XT 1.0
|
|
*/
|
|
XTAPI
|
|
VOID
|
|
AR::ProcSup::SetIdtGate(IN PKIDTENTRY Idt,
|
|
IN USHORT Vector,
|
|
IN PVOID Handler,
|
|
IN USHORT Selector,
|
|
IN USHORT Ist,
|
|
IN USHORT Access)
|
|
{
|
|
/* Setup the gate */
|
|
Idt[Vector].OffsetLow = ((ULONG_PTR)Handler & 0xFFFF);
|
|
Idt[Vector].OffsetMiddle = (((ULONG_PTR)Handler >> 16) & 0xFFFF);
|
|
Idt[Vector].OffsetHigh = (ULONG_PTR)Handler >> 32;
|
|
Idt[Vector].Dpl = Access;
|
|
Idt[Vector].IstIndex = Ist;
|
|
Idt[Vector].Present = 1;
|
|
Idt[Vector].Selector = Selector;
|
|
Idt[Vector].Type = 0xE;
|
|
}
|