940 lines
22 KiB
C++
940 lines
22 KiB
C++
/**
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* PROJECT: ExectOS
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* COPYRIGHT: See COPYING.md in the top level directory
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* FILE: xtoskrnl/ar/amd64/cpufunc.cc
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* DESCRIPTION: Routines to provide access to special AMD64 CPU instructions
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* DEVELOPERS: Rafal Kupiec <belliash@codingworkshop.eu.org>
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*/
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#include <xtos.hh>
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/**
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* Instructs the processor to clear the interrupt flag.
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*
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* @return This routine does not return any value.
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*
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* @since XT 1.0
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*/
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XTCDECL
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VOID
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AR::CpuFunc::ClearInterruptFlag(VOID)
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{
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__asm__ volatile("cli");
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}
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/**
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* Retrieves a various amount of information about the CPU.
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*
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* @param Registers
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* Supplies a pointer to the structure containing all the necessary registers and leafs for CPUID.
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*
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* @return TRUE if CPUID function could be executed, FALSE otherwise.
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*
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* @since XT 1.0
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*/
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XTCDECL
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BOOLEAN
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AR::CpuFunc::CpuId(IN OUT PCPUID_REGISTERS Registers)
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{
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UINT32 MaxLeaf;
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/* Get highest function ID available */
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__asm__ volatile("cpuid"
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: "=a" (MaxLeaf)
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: "a" (Registers->Leaf & 0x80000000)
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: "rbx",
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"rcx",
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"rdx");
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/* Check if CPU supports this command */
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if(Registers->Leaf > MaxLeaf)
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{
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/* Cannot call it, return FALSE */
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return FALSE;
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}
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/* Execute CPUID function */
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__asm__ volatile("cpuid"
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: "=a" (Registers->Eax),
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"=b" (Registers->Ebx),
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"=c" (Registers->Ecx),
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"=d" (Registers->Edx)
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: "a" (Registers->Leaf),
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"c" (Registers->SubLeaf));
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/* Return TRUE */
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return TRUE;
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}
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/**
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* Partially flushes the Translation Lookaside Buffer (TLB)
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*
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* @return This routine does not return any value.
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*
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* @since XT 1.0
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*/
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XTCDECL
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VOID
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AR::CpuFunc::FlushTlb(VOID)
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{
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/* Flush the TLB by resetting the CR3 */
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WriteControlRegister(3, ReadControlRegister(3));
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}
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/**
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* Gets the RFLAGS register.
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*
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* @return This routine returns the RFLAGS register.
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*
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* @since XT 1.0
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*/
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XTCDECL
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ULONG
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AR::CpuFunc::GetCpuFlags(VOID)
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{
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ULONG_PTR Flags;
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/* Get RFLAGS register */
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__asm__ volatile("pushf\n"
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"pop %0\n"
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: "=rm" (Flags)
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:
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: "memory");
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/* Return flags */
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return Flags;
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}
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/**
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* Gets the address of the current stack register.
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*
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* @return This routine returns the current stack pointer.
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*
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* @since XT 1.0
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*/
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XTASSEMBLY
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XTCDECL
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ULONG_PTR
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AR::CpuFunc::GetStackPointer(VOID)
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{
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/* Get current stack pointer */
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__asm__ volatile("movq %%rsp, %%rax\n"
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"retq\n"
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:
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:
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:);
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}
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/**
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* Halts the central processing unit (CPU).
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*
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* @return This routine does not return any value.
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*
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* @since XT 1.0
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*/
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XTCDECL
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VOID
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AR::CpuFunc::Halt(VOID)
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{
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__asm__ volatile("hlt");
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}
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/**
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* Checks whether interrupts are enabled or not.
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*
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* @return This routine returns TRUE if interrupts are enabled, or FALSE otherwise.
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*
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* @since XT 1.0
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*/
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XTCDECL
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BOOLEAN
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AR::CpuFunc::InterruptsEnabled(VOID)
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{
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ULONG_PTR Flags;
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/* Get RFLAGS register */
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Flags = GetCpuFlags();
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/* Check if interrupts are enabled and return result */
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return (Flags & X86_EFLAGS_IF_MASK) ? TRUE : FALSE;
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}
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/**
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* Invalidates the TLB (Translation Lookaside Buffer) for specified virtual address.
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*
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* @param Address
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* Suuplies a virtual address whose associated TLB entry will be invalidated.
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*
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* @return This routine does not return any value.
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*
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* @since XT 1.0
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*/
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XTCDECL
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VOID
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AR::CpuFunc::InvalidateTlbEntry(IN PVOID Address)
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{
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__asm__ volatile("invlpg (%0)"
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:
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: "b" (Address)
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: "memory");
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}
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/**
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* Loads the value in the source operand into the global descriptor table register (GDTR).
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*
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* @param Source
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* Specifies a memory location that contains the base address of GDT.
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*
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* @return This routine does not return any value.
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*
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* @since XT 1.0
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*/
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XTCDECL
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VOID
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AR::CpuFunc::LoadGlobalDescriptorTable(IN PVOID Source)
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{
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__asm__ volatile("lgdt %0"
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:
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: "m" (*(PSHORT)Source)
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: "memory");
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}
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/**
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* Loads the value in the source operand into the interrupt descriptor table register (IDTR).
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*
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* @param Source
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* Specifies a memory location that contains the base address of IDT.
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*
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* @return This routine does not return any value.
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*
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* @since XT 1.0
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*/
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XTCDECL
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VOID
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AR::CpuFunc::LoadInterruptDescriptorTable(IN PVOID Source)
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{
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__asm__ volatile("lidt %0"
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:
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: "m" (*(PSHORT)Source)
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: "memory");
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}
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/**
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* Loads the value in the source operand into the local descriptor table register (LDTR).
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*
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* @param Source
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* Specifies a selector value.
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*
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* @return This routine does not return any value.
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*
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* @since XT 1.0
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*/
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XTCDECL
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VOID
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AR::CpuFunc::LoadLocalDescriptorTable(IN USHORT Source)
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{
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__asm__ volatile("lldtw %0"
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:
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: "g" (Source));
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}
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/**
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* Loads the value in the source operand into the MXCSR register
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*
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* @param Source
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* Supplies a source value to be loaded into the MXCSR register.
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*
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* @return This routine does not return any value.
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*
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* @since XT 1.0
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*/
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XTCDECL
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VOID
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AR::CpuFunc::LoadMxcsrRegister(IN ULONG Source)
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{
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__asm__ volatile("ldmxcsr %0"
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:
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: "m" (Source));
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}
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/**
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* Loads source data into specified segment.
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*
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* @param Segment
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* Supplies a segment identification.
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*
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* @param Source
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* Supplies a pointer to the memory area containing data that will be loaded into specified segment.
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*
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* @return This routine does not return any value.
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*
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* @since XT 1.0
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*/
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XTCDECL
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VOID
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AR::CpuFunc::LoadSegment(IN USHORT Segment,
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IN ULONG Source)
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{
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switch(Segment)
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{
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case SEGMENT_CS:
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/* Load CS Segment */
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__asm__ volatile("mov %0, %%rax\n"
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"push %%rax\n"
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"lea label(%%rip), %%rax\n"
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"push %%rax\n"
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"lretq\n"
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"label:"
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:
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: "ri" ((ULONGLONG)Source)
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: "rax");
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break;
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case SEGMENT_DS:
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/* Load DS Segment */
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__asm__ volatile("movl %0, %%ds"
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:
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: "r" (Source));
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break;
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case SEGMENT_ES:
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/* Load ES Segment */
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__asm__ volatile("movl %0, %%es"
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:
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: "r" (Source));
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break;
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case SEGMENT_FS:
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/* Load FS Segment */
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__asm__ volatile("movl %0, %%fs"
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:
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: "r" (Source));
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break;
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case SEGMENT_GS:
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/* Load GS Segment */
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__asm__ volatile("movl %0, %%gs"
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:
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: "r" (Source));
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break;
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/* Load SS Segment */
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case SEGMENT_SS:
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__asm__ volatile("movl %0, %%ss"
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:
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: "r" (Source));
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break;
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}
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}
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/**
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* Loads Task Register (TR) with a segment selector that points to TSS.
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*
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* @param Source
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* Supplies the segment selector in the GDT describing the TSS.
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*
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* @return This routine does not return any value.
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*
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* @since XT 1.0
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*/
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XTCDECL
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VOID
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AR::CpuFunc::LoadTaskRegister(USHORT Source)
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{
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__asm__ volatile("ltr %0"
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:
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: "rm" (Source));
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}
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/**
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* Orders memory accesses as seen by other processors.
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*
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* @return This routine does not return any value.
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*
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* @since XT 1.0
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*/
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XTCDECL
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VOID
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AR::CpuFunc::MemoryBarrier(VOID)
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{
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LONG Barrier;
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__asm__ volatile("lock; orl $0, %0;"
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:
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: "m"(Barrier));
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}
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/**
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* Reads the specified CPU control register and returns its value.
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*
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* @param ControlRegister
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* Supplies a number of a control register which controls the general behavior of a CPU.
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*
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* @return The value stored in the control register.
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*
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* @since XT 1.0
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*/
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XTCDECL
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ULONG_PTR
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AR::CpuFunc::ReadControlRegister(IN USHORT ControlRegister)
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{
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ULONG_PTR Value;
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/* Read a value from specified CR register */
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switch(ControlRegister)
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{
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case 0:
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/* Read value from CR0 */
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__asm__ volatile("mov %%cr0, %0"
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: "=r" (Value)
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:
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: "memory");
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break;
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case 2:
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/* Read value from CR2 */
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__asm__ volatile("mov %%cr2, %0"
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: "=r" (Value)
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:
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: "memory");
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break;
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case 3:
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/* Read value from CR3 */
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__asm__ volatile("mov %%cr3, %0"
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: "=r" (Value)
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:
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: "memory");
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break;
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case 4:
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/* Read value from CR4 */
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__asm__ volatile("mov %%cr4, %0"
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: "=r" (Value)
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:
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: "memory");
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break;
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case 8:
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/* Read value from CR8 */
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__asm__ volatile("mov %%cr8, %0"
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: "=r" (Value)
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:
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: "memory");
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break;
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default:
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/* Invalid control register set */
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Value = 0;
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break;
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}
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/* Return value read from given CR register */
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return Value;
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}
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/**
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* Reads the specified CPU debug register and returns its value.
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*
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* @param DebugRegister
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* Supplies a number of a debug register to read from.
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*
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* @return The value stored in the specified debug register.
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*
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* @since XT 1.0
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*/
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XTCDECL
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ULONG_PTR
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AR::CpuFunc::ReadDebugRegister(IN USHORT DebugRegister)
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{
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ULONG_PTR Value;
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/* Read a value from specified DR register */
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switch(DebugRegister)
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{
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case 0:
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/* Read value from DR0 */
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__asm__ volatile("mov %%dr0, %0"
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: "=r" (Value));
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break;
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case 1:
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/* Read value from DR1 */
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__asm__ volatile("mov %%dr1, %0"
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: "=r" (Value));
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break;
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case 2:
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/* Read value from DR2 */
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__asm__ volatile("mov %%dr2, %0"
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: "=r" (Value));
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break;
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case 3:
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/* Read value from DR3 */
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__asm__ volatile("mov %%dr3, %0"
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: "=r" (Value));
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break;
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case 4:
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/* Read value from DR4 */
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__asm__ volatile("mov %%dr4, %0"
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: "=r" (Value));
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break;
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case 5:
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/* Read value from DR5 */
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__asm__ volatile("mov %%dr5, %0"
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: "=r" (Value));
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break;
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case 6:
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/* Read value from DR6 */
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__asm__ volatile("mov %%dr6, %0"
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: "=r" (Value));
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break;
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case 7:
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/* Read value from DR7 */
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__asm__ volatile("mov %%dr7, %0"
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: "=r" (Value));
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break;
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default:
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/* Invalid debug register set */
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Value = 0;
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break;
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}
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/* Return value read from given DR register */
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return Value;
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}
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/**
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* Reads quadword from a memory location specified by an offset relative to the beginning of the GS segment.
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*
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* @param Offset
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* Specifies the offset from the beginning of GS segment.
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*
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* @return Returns the value read from the specified memory location relative to GS segment.
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*
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* @since XT 1.0
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*/
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XTCDECL
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ULONGLONG
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AR::CpuFunc::ReadGSQuadWord(ULONG Offset)
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{
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ULONGLONG Value;
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/* Read quadword from GS segment */
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__asm__ volatile("movq %%gs:%a[Offset], %q[Value]"
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: [Value] "=r" (Value)
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: [Offset] "ir" (Offset));
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return Value;
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}
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/**
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* Reads a 64-bit value from the requested Model Specific Register (MSR).
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*
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* @param Register
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* Supplies the MSR to read.
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*
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* @return This routine returns the 64-bit MSR value.
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*
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* @since XT 1.0
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*/
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XTCDECL
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ULONGLONG
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AR::CpuFunc::ReadModelSpecificRegister(IN ULONG Register)
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{
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ULONG Low, High;
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__asm__ volatile("rdmsr"
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: "=a" (Low),
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"=d" (High)
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: "c" (Register));
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return ((ULONGLONG)High << 32) | Low;
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}
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/**
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* Reads the contents of the MXCSR control/status register.
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*
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* @return This routine returns the contents of the MXCSR register as a 32-bit unsigned integer value.
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*
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* @since XT 1.0
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*/
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XTCDECL
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UINT
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AR::CpuFunc::ReadMxCsrRegister(VOID)
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{
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return __builtin_ia32_stmxcsr();
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}
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/**
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* Reads the current value of the CPU's time-stamp counter.
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*
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* @return This routine returns the current instruction cycle count since the processor was started.
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*
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* @since XT 1.0
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*/
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XTCDECL
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ULONGLONG
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AR::CpuFunc::ReadTimeStampCounter(VOID)
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{
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ULONGLONG Low, High;
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__asm__ volatile("rdtsc"
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: "=a" (Low),
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"=d" (High));
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return ((ULONGLONG)High << 32) | Low;
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}
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/**
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* Orders memory accesses as seen by other processors, without fence.
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*
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* @return This routine does not return any value.
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*
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* @since XT 1.0
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*/
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XTCDECL
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VOID
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AR::CpuFunc::ReadWriteBarrier(VOID)
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{
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__asm__ volatile(""
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:
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:
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: "memory");
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}
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/**
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* Instructs the processor to set the interrupt flag.
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*
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* @return This routine does not return any value.
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*
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* @since XT 1.0
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*/
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XTCDECL
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VOID
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AR::CpuFunc::SetInterruptFlag(VOID)
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{
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__asm__ volatile("sti");
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}
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/**
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* Stores GDT register into the given memory area.
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*
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* @param Destination
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* Supplies a pointer to the memory area where GDT will be stored.
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*
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* @return This routine does not return any value.
|
|
*
|
|
* @since XT 1.0
|
|
*/
|
|
XTCDECL
|
|
VOID
|
|
AR::CpuFunc::StoreGlobalDescriptorTable(OUT PVOID Destination)
|
|
{
|
|
__asm__ volatile("sgdt %0"
|
|
: "=m" (*(PSHORT)Destination)
|
|
:
|
|
: "memory");
|
|
}
|
|
|
|
/**
|
|
* Stores IDT register into the given memory area.
|
|
*
|
|
* @param Destination
|
|
* Supplies a pointer to the memory area where IDT will be stored.
|
|
*
|
|
* @return This routine does not return any value.
|
|
*
|
|
* @since XT 1.0
|
|
*/
|
|
XTCDECL
|
|
VOID
|
|
AR::CpuFunc::StoreInterruptDescriptorTable(OUT PVOID Destination)
|
|
{
|
|
__asm__ volatile("sidt %0"
|
|
: "=m" (*(PSHORT)Destination)
|
|
:
|
|
: "memory");
|
|
}
|
|
|
|
/**
|
|
* Stores LDT register into the given memory area.
|
|
*
|
|
* @param Destination
|
|
* Supplies a pointer to the memory area where LDT will be stored.
|
|
*
|
|
* @return This routine does not return any value.
|
|
*
|
|
* @since XT 1.0
|
|
*/
|
|
XTCDECL
|
|
VOID
|
|
AR::CpuFunc::StoreLocalDescriptorTable(OUT PVOID Destination)
|
|
{
|
|
__asm__ volatile("sldt %0"
|
|
: "=m" (*(PSHORT)Destination)
|
|
:
|
|
: "memory");
|
|
}
|
|
|
|
/**
|
|
* Stores specified segment into the given memory area.
|
|
*
|
|
* @param Segment
|
|
* Supplies a segment identification.
|
|
*
|
|
* @param Destination
|
|
* Supplies a pointer to the memory area where segment data will be stored.
|
|
*
|
|
* @return This routine does not return any value.
|
|
*
|
|
* @since XT 1.0
|
|
*/
|
|
XTCDECL
|
|
VOID
|
|
AR::CpuFunc::StoreSegment(IN USHORT Segment,
|
|
OUT PVOID Destination)
|
|
{
|
|
switch(Segment)
|
|
{
|
|
case SEGMENT_CS:
|
|
__asm__ volatile("movl %%cs, %0"
|
|
: "=r" (*(PUINT)Destination));
|
|
break;
|
|
case SEGMENT_DS:
|
|
__asm__ volatile("movl %%ds, %0"
|
|
: "=r" (*(PUINT)Destination));
|
|
break;
|
|
case SEGMENT_ES:
|
|
__asm__ volatile("movl %%es, %0"
|
|
: "=r" (*(PUINT)Destination));
|
|
break;
|
|
case SEGMENT_FS:
|
|
__asm__ volatile("movl %%fs, %0"
|
|
: "=r" (*(PUINT)Destination));
|
|
break;
|
|
case SEGMENT_GS:
|
|
__asm__ volatile("movl %%gs, %0"
|
|
: "=r" (*(PUINT)Destination));
|
|
break;
|
|
case SEGMENT_SS:
|
|
__asm__ volatile("movl %%ss, %0"
|
|
: "=r" (*(PUINT)Destination));
|
|
break;
|
|
default:
|
|
Destination = NULLPTR;
|
|
break;
|
|
}
|
|
}
|
|
|
|
/**
|
|
* Stores TR into the given memory area.
|
|
*
|
|
* @param Destination
|
|
* Supplies a pointer to the memory area where TR will be stores.
|
|
*
|
|
* @return This routine does not return any value.
|
|
*
|
|
* @since XT 1.0
|
|
*/
|
|
XTCDECL
|
|
VOID
|
|
AR::CpuFunc::StoreTaskRegister(OUT PVOID Destination)
|
|
{
|
|
__asm__ volatile("str %0"
|
|
: "=m" (*(PULONG)Destination)
|
|
:
|
|
: "memory");
|
|
}
|
|
|
|
/**
|
|
* Writes a value to the specified CPU control register.
|
|
*
|
|
* @param ControlRegister
|
|
* Supplies a number of a control register which controls the general behavior of a CPU.
|
|
*
|
|
* @param Value
|
|
* Suplies a value to write to the CR register.
|
|
*
|
|
* @return This routine does not return any value.
|
|
*
|
|
* @since XT 1.0
|
|
*/
|
|
XTCDECL
|
|
VOID
|
|
AR::CpuFunc::WriteControlRegister(IN USHORT ControlRegister,
|
|
IN UINT_PTR Value)
|
|
{
|
|
/* Write a value into specified control register */
|
|
switch(ControlRegister)
|
|
{
|
|
case 0:
|
|
/* Write value to CR0 */
|
|
__asm__ volatile("mov %0, %%cr0"
|
|
:
|
|
: "r"(Value)
|
|
: "memory");
|
|
break;
|
|
case 2:
|
|
/* Write value to CR2 */
|
|
__asm__ volatile("mov %0, %%cr2"
|
|
:
|
|
: "r"(Value)
|
|
: "memory");
|
|
break;
|
|
case 3:
|
|
/* Write value to CR3 */
|
|
__asm__ volatile("mov %0, %%cr3"
|
|
:
|
|
: "r"(Value)
|
|
: "memory");
|
|
break;
|
|
case 4:
|
|
/* Write value to CR4 */
|
|
__asm__ volatile("mov %0, %%cr4"
|
|
:
|
|
: "r"(Value)
|
|
: "memory");
|
|
break;
|
|
case 8:
|
|
/* Write value to CR8 */
|
|
__asm__ volatile("mov %0, %%cr8"
|
|
:
|
|
: "r"(Value)
|
|
: "memory");
|
|
break;
|
|
}
|
|
}
|
|
|
|
/**
|
|
* Writes a value to the specified CPU debug register.
|
|
*
|
|
* @param DebugRegister
|
|
* Supplies a number of a debug register for write operation.
|
|
*
|
|
* @param Value
|
|
* Suplies a value to write to the specified DR register.
|
|
*
|
|
* @return This routine does not return any value.
|
|
*
|
|
* @since XT 1.0
|
|
*/
|
|
XTCDECL
|
|
VOID
|
|
AR::CpuFunc::WriteDebugRegister(IN USHORT DebugRegister,
|
|
IN UINT_PTR Value)
|
|
{
|
|
/* Write a value into specified debug register */
|
|
switch(DebugRegister)
|
|
{
|
|
case 0:
|
|
/* Write value to DR0 */
|
|
__asm__ volatile("mov %0, %%dr0"
|
|
:
|
|
: "r" (Value)
|
|
: "memory");
|
|
break;
|
|
case 1:
|
|
/* Write value to DR1 */
|
|
__asm__ volatile("mov %0, %%dr1"
|
|
:
|
|
: "r" (Value)
|
|
: "memory");
|
|
break;
|
|
case 2:
|
|
/* Write value to DR2 */
|
|
__asm__ volatile("mov %0, %%dr2"
|
|
:
|
|
: "r" (Value)
|
|
: "memory");
|
|
break;
|
|
case 3:
|
|
/* Write value to DR3 */
|
|
__asm__ volatile("mov %0, %%dr3"
|
|
:
|
|
: "r" (Value)
|
|
: "memory");
|
|
break;
|
|
case 4:
|
|
/* Write value to DR4 */
|
|
__asm__ volatile("mov %0, %%dr4"
|
|
:
|
|
: "r" (Value)
|
|
: "memory");
|
|
break;
|
|
case 5:
|
|
/* Write value to DR5 */
|
|
__asm__ volatile("mov %0, %%dr5"
|
|
:
|
|
: "r" (Value)
|
|
: "memory");
|
|
break;
|
|
case 6:
|
|
/* Write value to DR6 */
|
|
__asm__ volatile("mov %0, %%dr6"
|
|
:
|
|
: "r" (Value)
|
|
: "memory");
|
|
break;
|
|
case 7:
|
|
/* Write value to DR7 */
|
|
__asm__ volatile("mov %0, %%dr7"
|
|
:
|
|
: "r" (Value)
|
|
: "memory");
|
|
break;
|
|
}
|
|
}
|
|
|
|
/**
|
|
* Writes the specified value to the program status and control (EFLAGS) register.
|
|
*
|
|
* @param Value
|
|
* The value to write to the EFLAGS register.
|
|
*
|
|
* @return This routine does not return any value.
|
|
*
|
|
* @since XT 1.0
|
|
*/
|
|
XTCDECL
|
|
VOID
|
|
AR::CpuFunc::WriteEflagsRegister(IN UINT_PTR Value)
|
|
{
|
|
__asm__ volatile("push %0\n"
|
|
"popf"
|
|
:
|
|
: "rim" (Value));
|
|
}
|
|
|
|
/**
|
|
* Writes a 64-bit value to the requested Model Specific Register (MSR).
|
|
*
|
|
* @param Register
|
|
* Supplies the MSR register to write.
|
|
*
|
|
* @param Value
|
|
* Supplies the 64-bit value to write.
|
|
*
|
|
* @return This routine does not return any value.
|
|
*
|
|
* @since XT 1.0
|
|
*/
|
|
XTCDECL
|
|
VOID
|
|
AR::CpuFunc::WriteModelSpecificRegister(IN ULONG Register,
|
|
IN ULONGLONG Value)
|
|
{
|
|
ULONG Low = Value & 0xFFFFFFFF;
|
|
ULONG High = Value >> 32;
|
|
|
|
__asm__ volatile("wrmsr"
|
|
:
|
|
: "c" (Register),
|
|
"a" (Low),
|
|
"d" (High));
|
|
}
|
|
|
|
/**
|
|
* Yields a current thread running on the processor.
|
|
*
|
|
* @return This routine does not return any value.
|
|
*
|
|
* @since XT 1.0
|
|
*/
|
|
XTCDECL
|
|
VOID
|
|
AR::CpuFunc::YieldProcessor(VOID)
|
|
{
|
|
__asm__ volatile("pause"
|
|
:
|
|
:
|
|
: "memory");
|
|
}
|