PerikiyoXD
a270c08dcf
Add functionality to identify the CPU vendor and features using the CPUID instruction. The CPU vendor information is stored in the Processor Control Block (PRCB), including the vendor name and a corresponding enumeration. CPU features are also retrieved and stored in the PRCB. Previously, the CPU vendor was not properly stored in the PRCB, caused by a missing type cast. Using Rtl functions to copy the CPU vendor name to the PRCB. Details: - Introduced functions `ArpSetCpuVendor` and `ArpSetCpuFeatures` to set CPU vendor and features, respectively. - Modified `ArpIdentifyProcessor` to call the new functions for vendor and features identification. - Added `CPU_FEATURES` structure to `KPROCESSOR_CONTROL_BLOCK` structure to store CPU features. Tests: - Tested x86_64 on QEMU. Verified that the CPU vendor and features are correctly identified and stored in the PRCB.
676 lines
22 KiB
C
676 lines
22 KiB
C
/**
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* PROJECT: ExectOS
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* COPYRIGHT: See COPYING.md in the top level directory
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* FILE: xtoskrnl/ar/i686/procsup.c
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* DESCRIPTION: I686 processor functionality support
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* DEVELOPERS: Rafal Kupiec <belliash@codingworkshop.eu.org>
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*/
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#include <xtos.h>
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/**
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* Initializes i686 processor specific structures.
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*
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* @return This routine does not return any value.
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*
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* @since XT 1.0
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*/
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XTAPI
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VOID
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ArInitializeProcessor(VOID)
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{
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KDESCRIPTOR GdtDescriptor, IdtDescriptor;
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PKPROCESSOR_BLOCK ProcessorBlock;
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PVOID KernelFaultStack;
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PKGDTENTRY Gdt;
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PKIDTENTRY Idt;
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PKTSS Tss;
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/* Use initial structures */
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Gdt = ArInitialGdt;
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Idt = ArInitialIdt;
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Tss = &ArInitialTss;
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KernelFaultStack = &ArKernelFaultStack;
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/* Load processor block */
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ProcessorBlock = CONTAIN_RECORD(&ArInitialProcessorBlock.Prcb, KPROCESSOR_BLOCK, Prcb);
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/* Initialize processor block */
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ArpInitializeProcessorBlock(ProcessorBlock, Gdt, Idt, Tss, KernelFaultStack);
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/* Initialize GDT, IDT and TSS */
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ArpInitializeGdt(ProcessorBlock);
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ArpInitializeTss(ProcessorBlock);
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ArpInitializeIdt(ProcessorBlock);
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/* Set GDT and IDT descriptors */
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GdtDescriptor.Base = Gdt;
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GdtDescriptor.Limit = (GDT_ENTRIES * sizeof(KGDTENTRY)) - 1;
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IdtDescriptor.Base = Idt;
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IdtDescriptor.Limit = (IDT_ENTRIES * sizeof(KIDTENTRY)) - 1;
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/* Load GDT, IDT and TSS */
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ArLoadGlobalDescriptorTable(&GdtDescriptor.Limit);
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ArLoadInterruptDescriptorTable(&IdtDescriptor.Limit);
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ArLoadTaskRegister((UINT)KGDT_SYS_TSS);
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/* Enter passive IRQ level */
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ProcessorBlock->Irql = PASSIVE_LEVEL;
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/* Initialize segment registers */
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ArpInitializeSegments();
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/* Load FS segment */
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ArLoadSegment(SEGMENT_FS, KGDT_R0_PB);
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/* Initialize processor registers */
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ArpInitializeProcessorRegisters();
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/* Identify processor */
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ArpIdentifyProcessor();
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}
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/**
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* Updates an existing i686 GDT entry with new base address.
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*
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* @param Gdt
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* Supplies a pointer to the GDT.
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*
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* @param Selector
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* Specifies a segment selector of the GDT entry.
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*
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* @param Base
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* Specifies a base address value of the descriptor.
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*
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* @return This routine does not return any value.
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*
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* @since XT 1.0
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*/
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XTAPI
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VOID
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ArSetGdtEntryBase(IN PKGDTENTRY Gdt,
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IN USHORT Selector,
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IN ULONG_PTR Base)
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{
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PKGDTENTRY GdtEntry;
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/* Get GDT entry */
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GdtEntry = (PKGDTENTRY)((ULONG_PTR)Gdt + (Selector & ~RPL_MASK));
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/* Set new GDT descriptor base */
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GdtEntry->BaseLow = (Base & 0xFFFF);
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GdtEntry->Bytes.BaseMiddle = ((Base >> 16) & 0xFF);
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GdtEntry->Bytes.BaseHigh = ((Base >> 24) & 0xFF);
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}
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/**
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* Sets the CPU vendor information in the processor control block (PRCB).
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*
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* @return This routine does not return any value.
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*
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* @since XT 1.0
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*/
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XTAPI
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VOID
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ArpSetCpuVendor()
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{
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PKPROCESSOR_CONTROL_BLOCK Prcb;
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CPUID_REGISTERS CpuRegisters;
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UINT32 VendorNameBytes[3];
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/* Get current processor control block */
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Prcb = KeGetCurrentProcessorControlBlock();
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/* Get CPU vendor by issueing CPUID instruction */
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RtlZeroMemory(&CpuRegisters, sizeof(CPUID_REGISTERS));
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CpuRegisters.Leaf = CPUID_GET_VENDOR_STRING;
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ArCpuId(&CpuRegisters);
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/* Fix CPU vendor name bytes order */
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VendorNameBytes[0] = CpuRegisters.Ebx;
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VendorNameBytes[1] = CpuRegisters.Edx;
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VendorNameBytes[2] = CpuRegisters.Ecx;
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/* Copy CPU vendor name to processor control block */
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RtlZeroMemory(&Prcb->CpuId.VendorName[0], 13);
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RtlCopyMemory(&Prcb->CpuId.VendorName[0], &VendorNameBytes[0], 12);
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/* Set CPU vendor on processor control block by comparing known vendor names */
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if (RtlCompareMemory(&Prcb->CpuId.VendorName[0], CPUID_VENDOR_NAME_AMD, 12) == 12)
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{
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Prcb->CpuId.Vendor = CPU_VENDOR_AMD;
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}
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else if (RtlCompareMemory(&Prcb->CpuId.VendorName[0], CPUID_VENDOR_NAME_INTEL, 12) == 12)
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{
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Prcb->CpuId.Vendor = CPU_VENDOR_INTEL;
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}
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else
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{
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Prcb->CpuId.Vendor = CPU_VENDOR_UNKNOWN;
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}
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}
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/**
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* Sets the CPU features information in the processor control block (PRCB).
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*
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* @return This routine does not return any value.
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*
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* @since XT 1.0
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*/
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XTAPI
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VOID
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ArpSetCpuFeatures(VOID)
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{
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PKPROCESSOR_CONTROL_BLOCK Prcb;
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CPUID_REGISTERS CpuRegisters;
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CPUID_SIGNATURE CpuSignature;
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UINT32 FeatureArray[2];
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/* Get current processor control block */
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Prcb = KeGetCurrentProcessorControlBlock();
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/* Get CPU features */
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RtlZeroMemory(&CpuRegisters, sizeof(CPUID_REGISTERS));
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CpuRegisters.Leaf = CPUID_GET_CPU_FEATURES;
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ArCpuId(&CpuRegisters);
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/* Store CPU signature in processor control block */
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CpuSignature = *(PCPUID_SIGNATURE)&CpuRegisters.Eax;
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Prcb->CpuId.Family = CpuSignature.Family;
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Prcb->CpuId.Model = CpuSignature.Model;
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Prcb->CpuId.Stepping = CpuSignature.Stepping;
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/* Prcb->CpuId.Vendor print*/
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DebugPrint(L"CPU Signature: %s\n", Prcb->CpuId.Vendor);
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/* CPU vendor specific quirks */
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if (Prcb->CpuId.Vendor == CPU_VENDOR_AMD)
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{
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/* AMD CPU */
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Prcb->CpuId.Family = Prcb->CpuId.Family + CpuSignature.ExtendedFamily;
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if (Prcb->CpuId.Model == 0xF)
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{
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Prcb->CpuId.Model = Prcb->CpuId.Model + (CpuSignature.ExtendedModel << 4);
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}
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}
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else if (Prcb->CpuId.Vendor == CPU_VENDOR_INTEL)
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{
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/* Intel CPU */
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if (Prcb->CpuId.Family == 0xF)
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{
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Prcb->CpuId.Family = Prcb->CpuId.Family + CpuSignature.ExtendedFamily;
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}
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if ((Prcb->CpuId.Family == 0xF) || (Prcb->CpuId.Family == 0x6))
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{
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Prcb->CpuId.Model = Prcb->CpuId.Model + (CpuSignature.ExtendedModel << 4);
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}
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}
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else
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{
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/* Unknown CPU vendor */
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Prcb->CpuId.Vendor = CPU_VENDOR_UNKNOWN;
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}
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/* Store CPU features in processor control block */
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FeatureArray[0] = CpuRegisters.Edx;
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FeatureArray[1] = CpuRegisters.Ecx;
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RtlCopyMemory(&Prcb->CpuFeatures, &FeatureArray[0], sizeof(UINT64));
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}
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/**
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* Identifies processor type (vendor, model, stepping) as well as looks for available CPU features and stores them
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* in Processor Control Block (PRCB).
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*
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* @return This routine does not return any value.
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*
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* @since XT 1.0
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*/
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XTAPI
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VOID
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ArpIdentifyProcessor(VOID)
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{
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/* Set CPU vendor */
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ArpSetCpuVendor();
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/* Set CPU features */
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ArpSetCpuFeatures();
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}
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/**
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* Initializes the kernel's Global Descriptor Table (GDT).
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*
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* @param ProcessorBlock
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* Supplies a pointer to the processor block to use.
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*
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* @return This routine does not return any value.
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*
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* @since XT 1.0
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*/
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XTAPI
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VOID
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ArpInitializeGdt(IN PKPROCESSOR_BLOCK ProcessorBlock)
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{
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/* Initialize GDT entries */
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ArpSetGdtEntry(ProcessorBlock->GdtBase, KGDT_NULL, 0x0, 0x0, KGDT_TYPE_NONE, KGDT_DPL_SYSTEM, 0);
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ArpSetGdtEntry(ProcessorBlock->GdtBase, KGDT_R0_CODE, 0x0, 0xFFFFFFFF, KGDT_TYPE_CODE, KGDT_DPL_SYSTEM, 2);
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ArpSetGdtEntry(ProcessorBlock->GdtBase, KGDT_R0_DATA, 0x0, 0xFFFFFFFF, KGDT_TYPE_DATA, KGDT_DPL_SYSTEM, 2);
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ArpSetGdtEntry(ProcessorBlock->GdtBase, KGDT_R3_CODE, 0x0, 0xFFFFFFFF, KGDT_TYPE_CODE, KGDT_DPL_USER, 2);
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ArpSetGdtEntry(ProcessorBlock->GdtBase, KGDT_R3_DATA, 0x0, 0xFFFFFFFF, KGDT_TYPE_DATA, KGDT_DPL_USER, 2);
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ArpSetGdtEntry(ProcessorBlock->GdtBase, KGDT_SYS_TSS, (ULONG_PTR)ProcessorBlock->TssBase, sizeof(KTSS) - 1, I686_TSS, KGDT_DPL_SYSTEM, 0);
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ArpSetGdtEntry(ProcessorBlock->GdtBase, KGDT_R0_PB, (ULONG_PTR)ProcessorBlock, sizeof(KPROCESSOR_BLOCK), KGDT_TYPE_DATA, KGDT_DPL_SYSTEM, 2);
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ArpSetGdtEntry(ProcessorBlock->GdtBase, KGDT_R3_TEB, 0x0, 0xFFF, KGDT_TYPE_DATA | KGDT_DESCRIPTOR_ACCESSED, KGDT_DPL_USER, 2);
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ArpSetGdtEntry(ProcessorBlock->GdtBase, KGDT_VDM_TILE, 0x0400, 0xFFFF, KGDT_TYPE_DATA, KGDT_DPL_USER, 0);
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ArpSetGdtEntry(ProcessorBlock->GdtBase, KGDT_R0_LDT, 0x0, 0x0, KGDT_TYPE_NONE, KGDT_DPL_SYSTEM, 0);
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ArpSetGdtEntry(ProcessorBlock->GdtBase, KGDT_DF_TSS, 0x20000, 0xFFFF, I686_TSS, KGDT_DPL_SYSTEM, 0);
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ArpSetGdtEntry(ProcessorBlock->GdtBase, KGDT_NMI_TSS, 0x20000, 0xFFFF, KGDT_TYPE_CODE, KGDT_DPL_SYSTEM, 0);
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ArpSetGdtEntry(ProcessorBlock->GdtBase, KGDT_VDBS, 0xB8000, 0x3FFF, KGDT_TYPE_DATA, KGDT_DPL_SYSTEM, 0);
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ArpSetGdtEntry(ProcessorBlock->GdtBase, KGDT_ALIAS, (ULONG_PTR)ProcessorBlock->GdtBase, (GDT_ENTRIES * sizeof(KGDTENTRY)) - 1, KGDT_TYPE_DATA, KGDT_DPL_SYSTEM, 0);
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}
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/**
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* Initializes the kernel's Interrupt Descriptor Table (IDT).
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*
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* @param ProcessorBlock
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* Supplies a pointer to the processor block to use.
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*
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* @return This routine does not return any value.
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*
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* @since XT 1.0
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*/
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XTAPI
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VOID
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ArpInitializeIdt(IN PKPROCESSOR_BLOCK ProcessorBlock)
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{
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UINT Vector;
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/* Fill in all vectors */
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for(Vector = 0; Vector < IDT_ENTRIES; Vector++)
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{
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/* Set the IDT to handle unexpected interrupts */
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ArpSetIdtGate(ProcessorBlock->IdtBase, Vector, ArpHandleTrapFF, KGDT_R0_CODE, 0, KIDT_INTERRUPT | KIDT_ACCESS_RING0);
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}
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/* Setup IDT handlers for known interrupts and traps */
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ArpSetIdtGate(ProcessorBlock->IdtBase, 0x00, ArpHandleTrap00, KGDT_R0_CODE, 0, KIDT_INTERRUPT | KIDT_ACCESS_RING0);
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ArpSetIdtGate(ProcessorBlock->IdtBase, 0x01, ArpHandleTrap01, KGDT_R0_CODE, 0, KIDT_INTERRUPT | KIDT_ACCESS_RING0);
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ArpSetIdtGate(ProcessorBlock->IdtBase, 0x02, ArpHandleTrap02, KGDT_R0_CODE, 0, KIDT_INTERRUPT | KIDT_ACCESS_RING0);
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ArpSetIdtGate(ProcessorBlock->IdtBase, 0x03, ArpHandleTrap03, KGDT_R0_CODE, 0, KIDT_INTERRUPT | KIDT_ACCESS_RING3);
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ArpSetIdtGate(ProcessorBlock->IdtBase, 0x04, ArpHandleTrap04, KGDT_R0_CODE, 0, KIDT_INTERRUPT | KIDT_ACCESS_RING3);
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ArpSetIdtGate(ProcessorBlock->IdtBase, 0x05, ArpHandleTrap05, KGDT_R0_CODE, 0, KIDT_INTERRUPT | KIDT_ACCESS_RING0);
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ArpSetIdtGate(ProcessorBlock->IdtBase, 0x06, ArpHandleTrap06, KGDT_R0_CODE, 0, KIDT_INTERRUPT | KIDT_ACCESS_RING0);
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ArpSetIdtGate(ProcessorBlock->IdtBase, 0x07, ArpHandleTrap07, KGDT_R0_CODE, 0, KIDT_INTERRUPT | KIDT_ACCESS_RING0);
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ArpSetIdtGate(ProcessorBlock->IdtBase, 0x08, ArpHandleTrap08, KGDT_R0_CODE, 0, KIDT_INTERRUPT | KIDT_ACCESS_RING0);
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ArpSetIdtGate(ProcessorBlock->IdtBase, 0x09, ArpHandleTrap09, KGDT_R0_CODE, 0, KIDT_INTERRUPT | KIDT_ACCESS_RING0);
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ArpSetIdtGate(ProcessorBlock->IdtBase, 0x0A, ArpHandleTrap0A, KGDT_R0_CODE, 0, KIDT_INTERRUPT | KIDT_ACCESS_RING0);
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ArpSetIdtGate(ProcessorBlock->IdtBase, 0x0B, ArpHandleTrap0B, KGDT_R0_CODE, 0, KIDT_INTERRUPT | KIDT_ACCESS_RING0);
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ArpSetIdtGate(ProcessorBlock->IdtBase, 0x0C, ArpHandleTrap0C, KGDT_R0_CODE, 0, KIDT_INTERRUPT | KIDT_ACCESS_RING0);
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ArpSetIdtGate(ProcessorBlock->IdtBase, 0x0D, ArpHandleTrap0D, KGDT_R0_CODE, 0, KIDT_INTERRUPT | KIDT_ACCESS_RING0);
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ArpSetIdtGate(ProcessorBlock->IdtBase, 0x0E, ArpHandleTrap0E, KGDT_R0_CODE, 0, KIDT_INTERRUPT | KIDT_ACCESS_RING0);
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ArpSetIdtGate(ProcessorBlock->IdtBase, 0x10, ArpHandleTrap10, KGDT_R0_CODE, 0, KIDT_INTERRUPT | KIDT_ACCESS_RING0);
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ArpSetIdtGate(ProcessorBlock->IdtBase, 0x11, ArpHandleTrap11, KGDT_R0_CODE, 0, KIDT_INTERRUPT | KIDT_ACCESS_RING0);
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ArpSetIdtGate(ProcessorBlock->IdtBase, 0x12, ArpHandleTrap12, KGDT_R0_CODE, 0, KIDT_INTERRUPT | KIDT_ACCESS_RING0);
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ArpSetIdtGate(ProcessorBlock->IdtBase, 0x13, ArpHandleTrap13, KGDT_R0_CODE, 0, KIDT_INTERRUPT | KIDT_ACCESS_RING0);
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ArpSetIdtGate(ProcessorBlock->IdtBase, 0x2C, ArpHandleTrap2C, KGDT_R0_CODE, 0, KIDT_INTERRUPT | KIDT_ACCESS_RING3);
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ArpSetIdtGate(ProcessorBlock->IdtBase, 0x2D, ArpHandleTrap2D, KGDT_R0_CODE, 0, KIDT_INTERRUPT | KIDT_ACCESS_RING3);
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}
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/**
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* Initializes processor block.
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*
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* @param ProcessorBlock
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* Supplies a pointer to the processor block to initialize.
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*
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* @param Gdt
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* Supplies a pointer to the GDT for this processor block.
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*
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* @param Idt
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* Supplies a pointer to the IDT for this processor block.
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*
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* @param Tss
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* Supplies a pointer to the TSS for this processor block.
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*
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* @return This routine does not return any value.
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*
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* @since XT 1.0
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*/
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XTAPI
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VOID
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ArpInitializeProcessorBlock(OUT PKPROCESSOR_BLOCK ProcessorBlock,
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IN PKGDTENTRY Gdt,
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IN PKIDTENTRY Idt,
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IN PKTSS Tss,
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IN PVOID DpcStack)
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{
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/* Fill processor block with zeroes */
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RtlZeroMemory(ProcessorBlock, sizeof(KPROCESSOR_BLOCK));
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/* Set processor block and processor control block */
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ProcessorBlock->Self = ProcessorBlock;
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ProcessorBlock->CurrentPrcb = &ProcessorBlock->Prcb;
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/* Set GDT, IDT and TSS descriptors */
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ProcessorBlock->GdtBase = Gdt;
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ProcessorBlock->IdtBase = Idt;
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ProcessorBlock->TssBase = Tss;
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/* Setup DPC stack */
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ProcessorBlock->Prcb.DpcStack = DpcStack;
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/* Setup processor control block */
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ProcessorBlock->Prcb.Number = 0;
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ProcessorBlock->Prcb.SetMember = 1;
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ProcessorBlock->Prcb.MultiThreadProcessorSet = 1;
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/* Clear DR6 and DR7 registers */
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ProcessorBlock->Prcb.ProcessorState.SpecialRegisters.KernelDr6 = 0;
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ProcessorBlock->Prcb.ProcessorState.SpecialRegisters.KernelDr7 = 0;
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/* Set process and thread information */
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ProcessorBlock->Prcb.CurrentThread = &KeInitialThread.ThreadControlBlock;
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ProcessorBlock->Prcb.CurrentThread->ApcState.Process = &KeInitialProcess.ProcessControlBlock;
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ProcessorBlock->Prcb.IdleThread = &KeInitialThread.ThreadControlBlock;
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ProcessorBlock->Prcb.NextThread = NULL;
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}
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/**
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* Initializes processor registers and other boot structures.
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*
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* @return This routine does not return any value.
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*
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* @since XT 1.0
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*/
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XTAPI
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VOID
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ArpInitializeProcessorRegisters(VOID)
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{
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/* Clear EFLAGS register */
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ArWriteEflagsRegister(0);
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/* Enable write-protection */
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ArWriteControlRegister(0, ArReadControlRegister(0) | CR0_WP);
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}
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/**
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* Initializes segment registers.
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*
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* @return This routine does not return any value.
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*
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* @since XT 1.0
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*/
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XTAPI
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VOID
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ArpInitializeSegments(VOID)
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{
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ArLoadSegment(SEGMENT_DS, KGDT_R3_DATA | RPL_MASK);
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ArLoadSegment(SEGMENT_ES, KGDT_R3_DATA | RPL_MASK);
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}
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/**
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* Initializes the kernel's Task State Segment (TSS).
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*
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* @param ProcessorBlock
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* Supplies a pointer to the processor block to use.
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*
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* @return This routine does not return any value.
|
|
*
|
|
* @since XT 1.0
|
|
*/
|
|
XTAPI
|
|
VOID
|
|
ArpInitializeTss(IN PKPROCESSOR_BLOCK ProcessorBlock)
|
|
{
|
|
/* Clear I/O map */
|
|
RtlFillMemory(ProcessorBlock->TssBase->IoMaps[0].IoMap, IOPM_FULL_SIZE, 0xFF);
|
|
|
|
/* Fill Interrupt Direction Maps with zeroes */
|
|
RtlZeroMemory(ProcessorBlock->TssBase->IoMaps[0].DirectionMap, IOPM_DIRECTION_MAP_SIZE);
|
|
|
|
/* Enable DPMI support */
|
|
ProcessorBlock->TssBase->IoMaps[0].DirectionMap[0] = 4;
|
|
ProcessorBlock->TssBase->IoMaps[0].DirectionMap[3] = 0x18;
|
|
ProcessorBlock->TssBase->IoMaps[0].DirectionMap[4] = 0x18;
|
|
|
|
/* Fill default Interrupt Direction Map with zeroes */
|
|
RtlZeroMemory(ProcessorBlock->TssBase->IntDirectionMap, IOPM_DIRECTION_MAP_SIZE);
|
|
|
|
/* Enable DPMI support */
|
|
ProcessorBlock->TssBase->IntDirectionMap[0] = 4;
|
|
ProcessorBlock->TssBase->IntDirectionMap[3] = 0x18;
|
|
ProcessorBlock->TssBase->IntDirectionMap[4] = 0x18;
|
|
|
|
/* Set I/O map base and disable traps */
|
|
ProcessorBlock->TssBase->IoMapBase = sizeof(KTSS);
|
|
ProcessorBlock->TssBase->Flags = 0;
|
|
|
|
/* Set LDT and SS */
|
|
ProcessorBlock->TssBase->LDT = KGDT_R0_LDT;
|
|
ProcessorBlock->TssBase->Ss0 = KGDT_R0_DATA;
|
|
|
|
/* Initialize task gates for DoubleFault and NMI traps */
|
|
ArpSetDoubleFaultTssEntry(ProcessorBlock);
|
|
ArpSetNonMaskableInterruptTssEntry(ProcessorBlock);
|
|
}
|
|
|
|
/**
|
|
* Initializes the DoubleFault TSS entry in the Global Descriptor Table.
|
|
*
|
|
* @param ProcessorBlock
|
|
* Supplies a pointer to the processor block to use.
|
|
*
|
|
* @return This routine does not return any value.
|
|
*
|
|
* @since XT 1.0
|
|
*/
|
|
XTAPI
|
|
VOID
|
|
ArpSetDoubleFaultTssEntry(IN PKPROCESSOR_BLOCK ProcessorBlock)
|
|
{
|
|
PKGDTENTRY TaskGateEntry, TssEntry;
|
|
PKTSS Tss;
|
|
|
|
/* Setup task gate for DoubleFault trap */
|
|
TaskGateEntry = (PKGDTENTRY)&ProcessorBlock->IdtBase[8];
|
|
TaskGateEntry->Bits.Dpl = 0;
|
|
TaskGateEntry->Bits.Present = 1;
|
|
TaskGateEntry->Bits.Type = I686_TASK_GATE;
|
|
((PKIDTENTRY)TaskGateEntry)->Selector = KGDT_DF_TSS;
|
|
|
|
/* Initialize DoubleFault TSS and set initial state */
|
|
Tss = (PKTSS)ArpDoubleFaultTss;
|
|
Tss->IoMapBase = sizeof(KTSS);
|
|
Tss->Flags = 0;
|
|
Tss->LDT = KGDT_R0_LDT;
|
|
Tss->CR3 = ArReadControlRegister(3);
|
|
Tss->Esp = (ULONG_PTR)&ArKernelFaultStack;
|
|
Tss->Esp0 = (ULONG_PTR)&ArKernelFaultStack;
|
|
Tss->Eip = PtrToUlong(ArpHandleTrap08);
|
|
Tss->Cs = KGDT_R0_CODE;
|
|
Tss->Ds = KGDT_R3_DATA | RPL_MASK;
|
|
Tss->Es = KGDT_R3_DATA | RPL_MASK;
|
|
Tss->Fs = KGDT_R0_PB;
|
|
Tss->Ss0 = KGDT_R0_DATA;
|
|
ArStoreSegment(SEGMENT_SS, (PVOID)&Tss->Ss);
|
|
|
|
/* Setup DoubleFault TSS entry in Global Descriptor Table */
|
|
TssEntry = (PKGDTENTRY)(&(ProcessorBlock->GdtBase[KGDT_DF_TSS / sizeof(KGDTENTRY)]));
|
|
TssEntry->BaseLow = ((ULONG_PTR)Tss & 0xFFFF);
|
|
TssEntry->Bytes.BaseMiddle = ((ULONG_PTR)Tss >> 16);
|
|
TssEntry->Bytes.BaseHigh = ((ULONG_PTR)Tss >> 24);
|
|
TssEntry->LimitLow = sizeof(KTSS) - 1;
|
|
TssEntry->Bits.LimitHigh = 0;
|
|
TssEntry->Bits.Dpl = 0;
|
|
TssEntry->Bits.Present = 1;
|
|
TssEntry->Bits.Type = I686_TSS;
|
|
}
|
|
|
|
/**
|
|
* Fills in an i686 GDT entry.
|
|
*
|
|
* @param Gdt
|
|
* Supplies a pointer to the GDT.
|
|
*
|
|
* @param Selector
|
|
* Specifies a segment selector of the GDT entry.
|
|
*
|
|
* @param Base
|
|
* Specifies a base address value of the descriptor.
|
|
*
|
|
* @param Limit
|
|
* Specifies a descriptor limit.
|
|
*
|
|
* @param Type
|
|
* Specifies a type of the descriptor.
|
|
*
|
|
* @param Dpl
|
|
* Specifies the descriptor privilege level.
|
|
*
|
|
* @param SegmentMode
|
|
* Specifies a segment mode of the descriptor.
|
|
*
|
|
* @return This routine does not return any value
|
|
*
|
|
* @since XT 1.0
|
|
*/
|
|
XTAPI
|
|
VOID
|
|
ArpSetGdtEntry(IN PKGDTENTRY Gdt,
|
|
IN USHORT Selector,
|
|
IN ULONG_PTR Base,
|
|
IN ULONG Limit,
|
|
IN UCHAR Type,
|
|
IN UCHAR Dpl,
|
|
IN UCHAR SegmentMode)
|
|
{
|
|
PKGDTENTRY GdtEntry;
|
|
UCHAR Granularity;
|
|
|
|
/* Set the granularity flag depending on descriptor limit */
|
|
if(Limit < 0x100000)
|
|
{
|
|
/* Limit is in 1B blocks */
|
|
Granularity = 0;
|
|
}
|
|
else
|
|
{
|
|
/* Limit is in 4KB blocks */
|
|
Granularity = 1;
|
|
Limit >>= 12;
|
|
}
|
|
|
|
/* Get GDT entry */
|
|
GdtEntry = (PKGDTENTRY)((ULONG_PTR)Gdt + (Selector & ~RPL_MASK));
|
|
|
|
/* Set GDT descriptor base */
|
|
GdtEntry->BaseLow = (Base & 0xFFFF);
|
|
GdtEntry->Bytes.BaseMiddle = ((Base >> 16) & 0xFF);
|
|
GdtEntry->Bytes.BaseHigh = ((Base >> 24) & 0xFF);
|
|
|
|
/* Set descriptor limit */
|
|
GdtEntry->LimitLow = (Limit & 0xFFFF);
|
|
GdtEntry->Bits.LimitHigh = ((Limit >> 16) & 0xF);
|
|
|
|
/* Initialize GDT entry */
|
|
GdtEntry->Bits.DefaultBig = !!(SegmentMode & 2);
|
|
GdtEntry->Bits.Dpl = (Dpl & 0x3);
|
|
GdtEntry->Bits.Granularity = Granularity;
|
|
GdtEntry->Bits.Reserved0 = 0;
|
|
GdtEntry->Bits.Present = (Type != 0);
|
|
GdtEntry->Bits.System = 0;
|
|
GdtEntry->Bits.Type = (Type & 0x1F);
|
|
}
|
|
|
|
/**
|
|
* Fills in a call, interrupt, task or trap gate entry.
|
|
*
|
|
* @param Idt
|
|
* Supplies a pointer to IDT structure, where gate is located.
|
|
*
|
|
* @param Vector
|
|
* Supplies a gate vector pointing to the interrupt gate in the IDT
|
|
*
|
|
* @param Handler
|
|
* Supplies a pointer to the interrupt handler of the specified gate.
|
|
*
|
|
* @param Selector
|
|
* Supplies the code selector the gate should run in.
|
|
*
|
|
* @param Ist
|
|
* Supplies the interrupt stack table entry the gate should run in.
|
|
*
|
|
* @param Access
|
|
* Supplies the gate access rights.
|
|
*
|
|
* @return This routine does not return any value.
|
|
*
|
|
* @since XT 1.0
|
|
*/
|
|
XTAPI
|
|
VOID
|
|
ArpSetIdtGate(IN PKIDTENTRY Idt,
|
|
IN USHORT Vector,
|
|
IN PVOID Handler,
|
|
IN USHORT Selector,
|
|
IN USHORT Ist,
|
|
IN USHORT Access)
|
|
{
|
|
/* Setup the gate */
|
|
Idt[Vector].Offset = (USHORT)((ULONG)Handler & 0xFFFF);
|
|
Idt[Vector].ExtendedOffset = (USHORT)((ULONG)Handler >> 16);
|
|
Idt[Vector].Access = 0x8000 | (Access << 8);
|
|
Idt[Vector].Selector = Selector;
|
|
}
|
|
|
|
/**
|
|
* Initializes the Non-Maskable Interrupt TSS entry in the Global Descriptor Table.
|
|
*
|
|
* @param ProcessorBlock
|
|
* Supplies a pointer to the processor block to use.
|
|
*
|
|
* @return This routine does not return any value.
|
|
*
|
|
* @since XT 1.0
|
|
*/
|
|
XTAPI
|
|
VOID
|
|
ArpSetNonMaskableInterruptTssEntry(IN PKPROCESSOR_BLOCK ProcessorBlock)
|
|
{
|
|
PKGDTENTRY TaskGateEntry, TssEntry;
|
|
PKTSS Tss;
|
|
|
|
/* Setup task gate for NMI */
|
|
TaskGateEntry = (PKGDTENTRY)&ProcessorBlock->IdtBase[2];
|
|
TaskGateEntry->Bits.Dpl = 0;
|
|
TaskGateEntry->Bits.Present = 1;
|
|
TaskGateEntry->Bits.Type = I686_TASK_GATE;
|
|
((PKIDTENTRY)TaskGateEntry)->Selector = KGDT_NMI_TSS;
|
|
|
|
/* Initialize NMI TSS and set initial state */
|
|
Tss = (PKTSS)ArpNonMaskableInterruptTss;
|
|
Tss->IoMapBase = sizeof(KTSS);
|
|
Tss->Flags = 0;
|
|
Tss->LDT = KGDT_R0_LDT;
|
|
Tss->CR3 = ArReadControlRegister(3);
|
|
Tss->Esp = (ULONG_PTR)&ArKernelFaultStack;
|
|
Tss->Esp0 = (ULONG_PTR)&ArKernelFaultStack;
|
|
Tss->Eip = PtrToUlong(ArpHandleTrap02);
|
|
Tss->Cs = KGDT_R0_CODE;
|
|
Tss->Ds = KGDT_R3_DATA | RPL_MASK;
|
|
Tss->Es = KGDT_R3_DATA | RPL_MASK;
|
|
Tss->Fs = KGDT_R0_PB;
|
|
ArStoreSegment(SEGMENT_SS, (PVOID)&Tss->Ss);
|
|
|
|
/* Setup NMI TSS entry in Global Descriptor Table */
|
|
TssEntry = (PKGDTENTRY)(&(ProcessorBlock->GdtBase[KGDT_NMI_TSS / sizeof(KGDTENTRY)]));
|
|
TssEntry->BaseLow = ((ULONG_PTR)Tss & 0xFFFF);
|
|
TssEntry->Bytes.BaseMiddle = ((ULONG_PTR)Tss >> 16);
|
|
TssEntry->Bytes.BaseHigh = ((ULONG_PTR)Tss >> 24);
|
|
TssEntry->LimitLow = sizeof(KTSS) - 1;
|
|
TssEntry->Bits.LimitHigh = 0;
|
|
TssEntry->Bits.Dpl = 0;
|
|
TssEntry->Bits.Present = 1;
|
|
TssEntry->Bits.Type = I686_TSS;
|
|
}
|