299 lines
10 KiB
C++
299 lines
10 KiB
C++
/**
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* PROJECT: ExectOS
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* COPYRIGHT: See COPYING.md in the top level directory
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* FILE: xtldr/amd64/memory.cc
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* DESCRIPTION: EFI memory management for AMD64 target
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* DEVELOPERS: Rafal Kupiec <belliash@codingworkshop.eu.org>
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* Aiken Harris <harraiken91@gmail.com>
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*/
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#include <xtos.hh>
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/**
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* Determines the appropriate paging level (PML) for the AMD64 architecture.
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*
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* @param Parameters
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* A pointer to the wide character string containing the kernel boot parameters.
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*
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* @return This routine returns the appropriate page map level (5 if LA57 is enabled, 4 otherwise).
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*
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* @since XT 1.0
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*/
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XTCDECL
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ULONG
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Xtos::DeterminePagingLevel(IN CONST PWCHAR Parameters)
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{
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CPUID_REGISTERS CpuRegisters;
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/* Prepare CPUID registers to query for STD7 features */
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XtLdrProtocol->Memory.ZeroMemory(&CpuRegisters, sizeof(CPUID_REGISTERS));
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CpuRegisters.Leaf = CPUID_GET_VENDOR_STRING;
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/* Query CPUID */
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XtLdrProtocol->Cpu.CpuId(&CpuRegisters);
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/* Verify if the CPU supports the STD7 feature leaf (0x00000007) */
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if(CpuRegisters.Eax >= CPUID_GET_STANDARD7_FEATURES)
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{
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/* Prepare CPUID registers to query for LA57 support */
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XtLdrProtocol->Memory.ZeroMemory(&CpuRegisters, sizeof(CPUID_REGISTERS));
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CpuRegisters.Leaf = CPUID_GET_STANDARD7_FEATURES;
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/* Query CPUID */
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XtLdrProtocol->Cpu.CpuId(&CpuRegisters);
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/* Check if eXtended Physical Addressing (XPA) is enabled and if LA57 is supported by the CPU */
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if((CpuRegisters.Ecx & CPUID_FEATURES_ECX_LA57) &&
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!(XtLdrProtocol->BootUtils.GetBooleanParameter(Parameters, L"NOXPA")))
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{
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/* Enable LA57 (PML5) */
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return 5;
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}
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}
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/* Disable LA57 and use PML4 by default */
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return 4;
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}
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/**
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* Builds the actual memory mapping page table and enables paging. This routine exits EFI boot services as well.
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*
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* @param PageMap
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* Supplies a pointer to the page mapping structure.
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*
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* @return This routine returns a status code.
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*
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* @since XT 1.0
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*/
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XTCDECL
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EFI_STATUS
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Xtos::EnablePaging(IN PXTBL_PAGE_MAPPING PageMap)
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{
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EFI_STATUS Status;
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EFI_PHYSICAL_ADDRESS TrampolineAddress;
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PXT_TRAMPOLINE_ENTRY TrampolineEntry;
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ULONG_PTR TrampolineSize;
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PVOID TrampolineCode;
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/* Build page map */
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Status = XtLdrProtocol->Memory.BuildPageMap(PageMap, (PageMap->PageMapLevel > 4) ? MM_P5E_LA57_BASE : MM_PXE_BASE);
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if(Status != STATUS_EFI_SUCCESS)
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{
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/* Failed to build page map */
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XtLdrProtocol->Debug.Print(L"Failed to build page map (Status code: %zX)\n", Status);
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return Status;
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}
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/* Map memory for hardware layer */
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Status = MapHardwareMemoryPool(PageMap);
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if(Status != STATUS_EFI_SUCCESS)
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{
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/* Failed to map memory for hardware layer */
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XtLdrProtocol->Debug.Print(L"Failed to map memory for hardware leyer (Status code: %zX)\n", Status);
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return Status;
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}
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/* Check the configured page map level to set the LA57 state accordingly */
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if(PageMap->PageMapLevel == 5)
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{
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/* Get the trampoline code information */
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XtLdrProtocol->BootUtils.GetTrampolineInformation(TrampolineEnableXpa, &TrampolineCode, &TrampolineSize);
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if(TrampolineCode == NULLPTR || TrampolineSize == 0)
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{
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/* Failed to get trampoline information */
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XtLdrProtocol->Debug.Print(L"Failed to get trampoline information\n");
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return STATUS_EFI_INVALID_PARAMETER;
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}
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/* Set the address of the trampoline code below 1MB */
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TrampolineAddress = MM_TRAMPOLINE_ADDRESS;
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/* Allocate pages for the trampoline */
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Status = XtLdrProtocol->Memory.AllocatePages(AllocateAddress, EFI_SIZE_TO_PAGES(TrampolineSize), &TrampolineAddress);
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if(Status != STATUS_EFI_SUCCESS)
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{
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/* Failed to allocate memory for trampoline code */
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XtLdrProtocol->Debug.Print(L"Failed to allocate memory for trampoline code (Status code: %zX)\n", Status);
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return Status;
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}
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/* Set the trampoline entry point and copy its code into the allocated buffer */
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TrampolineEntry = (PXT_TRAMPOLINE_ENTRY)(UINT_PTR)TrampolineAddress;
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XtLdrProtocol->Memory.CopyMemory((PVOID)TrampolineEntry, TrampolineCode, TrampolineSize);
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}
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/* Exit EFI Boot Services */
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XtLdrProtocol->Debug.Print(L"Exiting EFI boot services\n");
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Status = XtLdrProtocol->Utils.ExitBootServices();
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if(Status != STATUS_EFI_SUCCESS)
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{
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/* Failed to exit boot services */
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XtLdrProtocol->Debug.Print(L"Failed to exit boot services (Status code: %zX)\n", Status);
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return STATUS_EFI_ABORTED;
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}
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/* Check the configured page map level to set the LA57 state accordingly */
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if(PageMap->PageMapLevel == 5)
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{
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/* Enable Linear Address 57-bit (LA57) extension */
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XtLdrProtocol->Debug.Print(L"Enabling Linear Address 57-bit (LA57)\n");
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/* Execute the trampoline to enable LA57 and write PML5 to CR3 */
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TrampolineEntry((UINT64)PageMap->PtePointer);
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}
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else
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{
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/* Disable Linear Address 57-bit (LA57) extension */
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XtLdrProtocol->Debug.Print(L"Disabling Linear Address 57-bit (LA57)\n");
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/* Write PML4 to CR3 and enable paging */
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XtLdrProtocol->Cpu.WriteControlRegister(3, (UINT_PTR)PageMap->PtePointer);
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XtLdrProtocol->Cpu.WriteControlRegister(0, XtLdrProtocol->Cpu.ReadControlRegister(0) | CR0_PG);
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}
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/* Return success */
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return STATUS_EFI_SUCCESS;
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}
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/**
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* Maps the page table for hardware layer addess space.
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*
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* @param PageMap
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* Supplies a pointer to the page mapping structure.
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*
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* @return This routine returns a status code.
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*
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* @since XT 1.0
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*/
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XTCDECL
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EFI_STATUS
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Xtos::MapHardwareMemoryPool(IN PXTBL_PAGE_MAPPING PageMap)
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{
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PHARDWARE_PTE P5eBase, PdeBase, PpeBase, PxeBase;
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EFI_PHYSICAL_ADDRESS Address;
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EFI_STATUS Status;
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if(PageMap->PageMapLevel == 5)
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{
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/* Get P5E (PML5) base address */
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P5eBase = (PHARDWARE_PTE)PageMap->PtePointer;
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/* Check if P5E entry already exists */
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if(!P5eBase[(MM_HARDWARE_VA_START >> MM_P5I_SHIFT) & 0x1FF].Valid)
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{
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/* No valid P5E, allocate memory */
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Status = XtLdrProtocol->Memory.AllocatePages(AllocateAnyPages, 1, &Address);
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if(Status != STATUS_EFI_SUCCESS)
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{
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/* Memory allocation failure, return error */
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return Status;
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}
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/* Zero fill memory used by P5E */
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XtLdrProtocol->Memory.ZeroMemory((PVOID)Address, EFI_PAGE_SIZE);
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/* Make P5E valid */
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P5eBase[(MM_HARDWARE_VA_START >> MM_P5I_SHIFT) & 0x1FF].Valid = 1;
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P5eBase[(MM_HARDWARE_VA_START >> MM_P5I_SHIFT) & 0x1FF].PageFrameNumber = Address / EFI_PAGE_SIZE;
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P5eBase[(MM_HARDWARE_VA_START >> MM_P5I_SHIFT) & 0x1FF].Writable = 1;
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/* Set PXE base address */
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PxeBase = (PHARDWARE_PTE)(UINT_PTR)Address;
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}
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else
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{
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/* Set PXE base address based on existing P5E */
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PxeBase = (PHARDWARE_PTE)((P5eBase[(MM_HARDWARE_VA_START >> MM_P5I_SHIFT) & 0x1FF].PageFrameNumber) << EFI_PAGE_SHIFT);
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}
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}
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else
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{
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/* Get PXE (PML4) base address */
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PxeBase = (PHARDWARE_PTE)PageMap->PtePointer;
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}
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/* Check if PXE entry already exists */
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if(!PxeBase[(MM_HARDWARE_VA_START >> MM_PXI_SHIFT) & 0x1FF].Valid)
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{
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/* No valid PXE, allocate memory */
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Status = XtLdrProtocol->Memory.AllocatePages(AllocateAnyPages, 1, &Address);
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if(Status != STATUS_EFI_SUCCESS)
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{
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/* Memory allocation failure, return error */
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return Status;
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}
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/* Zero fill memory used by PXE */
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XtLdrProtocol->Memory.ZeroMemory((PVOID)Address, EFI_PAGE_SIZE);
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/* Make PXE valid */
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PxeBase[(MM_HARDWARE_VA_START >> MM_PXI_SHIFT) & 0x1FF].Valid = 1;
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PxeBase[(MM_HARDWARE_VA_START >> MM_PXI_SHIFT) & 0x1FF].PageFrameNumber = Address / EFI_PAGE_SIZE;
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PxeBase[(MM_HARDWARE_VA_START >> MM_PXI_SHIFT) & 0x1FF].Writable = 1;
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/* Set PPE base address */
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PpeBase = (PHARDWARE_PTE)(UINT_PTR)Address;
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}
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else
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{
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/* Set PPE base address based on existing PXE */
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PpeBase = (PHARDWARE_PTE)((PxeBase[(MM_HARDWARE_VA_START >> MM_PXI_SHIFT) & 0x1FF].PageFrameNumber) << EFI_PAGE_SHIFT);
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}
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/* Check if PPE entry already exists */
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if(!PpeBase[(MM_HARDWARE_VA_START >> MM_PPI_SHIFT) & 0x1FF].Valid)
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{
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/* No valid PPE, allocate memory */
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Status = XtLdrProtocol->Memory.AllocatePages(AllocateAnyPages, 1, &Address);
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if(Status != STATUS_EFI_SUCCESS)
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{
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/* Memory allocation failure, return error */
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return Status;
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}
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/* Zero fill memory used by PPE */
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XtLdrProtocol->Memory.ZeroMemory((PVOID)Address, EFI_PAGE_SIZE);
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/* Make PPE valid */
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PpeBase[(MM_HARDWARE_VA_START >> MM_PPI_SHIFT) & 0x1FF].Valid = 1;
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PpeBase[(MM_HARDWARE_VA_START >> MM_PPI_SHIFT) & 0x1FF].PageFrameNumber = Address / EFI_PAGE_SIZE;
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PpeBase[(MM_HARDWARE_VA_START >> MM_PPI_SHIFT) & 0x1FF].Writable = 1;
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/* Set PDE base address */
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PdeBase = (PHARDWARE_PTE)Address;
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}
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else
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{
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/* Set PDE base address, based on existing PPE */
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PdeBase = (PHARDWARE_PTE)((PpeBase[(MM_HARDWARE_VA_START >> MM_PPI_SHIFT) & 0x1FF].PageFrameNumber) << EFI_PAGE_SHIFT);
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}
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/* Loop through 2 PDE entries */
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for(UINT Index = 0 ; Index < 2 ; Index++)
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{
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/* Check if PDE entry already exists */
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if(!PdeBase[((MM_HARDWARE_VA_START >> MM_PDI_SHIFT) & 0x1FF) + Index].Valid)
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{
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/* No valid PDE, allocate memory */
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Status = XtLdrProtocol->Memory.AllocatePages(AllocateAnyPages, 1, &Address);
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if(Status != STATUS_EFI_SUCCESS)
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{
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/* Memory allocation failure, return error */
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return Status;
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}
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/* Zero fill memory used by PDE */
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XtLdrProtocol->Memory.ZeroMemory((PVOID)Address, EFI_PAGE_SIZE);
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/* Make PDE valid */
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PdeBase[((MM_HARDWARE_VA_START >> MM_PDI_SHIFT) & 0x1FF) + Index].Valid = 1;
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PdeBase[((MM_HARDWARE_VA_START >> MM_PDI_SHIFT) & 0x1FF) + Index].PageFrameNumber = Address / EFI_PAGE_SIZE;
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PdeBase[((MM_HARDWARE_VA_START >> MM_PDI_SHIFT) & 0x1FF) + Index].Writable = 1;
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}
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}
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/* Return success */
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return STATUS_EFI_SUCCESS;
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}
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