454 lines
18 KiB
C
454 lines
18 KiB
C
/**
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* PROJECT: ExectOS
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* COPYRIGHT: See COPYING.md in the top level directory
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* FILE: sdk/xtdk/hltypes.h
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* DESCRIPTION: XT hardware abstraction layer structures definitions
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* DEVELOPERS: Rafal Kupiec <belliash@codingworkshop.eu.org>
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*/
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#ifndef __XTDK_HLTYPES_H
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#define __XTDK_HLTYPES_H
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#include <xtbase.h>
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#include <xtdefs.h>
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#include <xttypes.h>
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#include ARCH_HEADER(hltypes.h)
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/* ACPI Root System Description Pointer (RSDP) signature */
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#define ACPI_RSDP_SIGNATURE 0x2052545020445352
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/* ACPI table signatures */
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#define ACPI_BERT_SIGNATURE 0x54524542 /* Boot Error Record Table */
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#define ACPI_BGRT_SIGNATURE 0x54524742 /* Boot Graphics Record Table */
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#define ACPI_BOOT_SIGNATURE 0x544F4F42 /* ACPI BOOT Table */
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#define ACPI_CPEP_SIGNATURE 0x50455043 /* Corrected Platform Error Polling Table */
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#define ACPI_DBG2_SIGNATURE 0x32474244 /* Debug Port Table v2 */
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#define ACPI_DBGP_SIGNATURE 0x50474244 /* Debug Port Table */
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#define ACPI_DMAR_SIGNATURE 0x52414D44 /* DMA Remapping Table */
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#define ACPI_DSDT_SIGNATURE 0x54445344 /* Differentiated System Description Table */
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#define ACPI_ECDT_SIGNATURE 0x54444345 /* Embedded Controller Description Table */
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#define ACPI_ERST_SIGNATURE 0x54535245 /* Error Record Serialization Table */
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#define ACPI_FACS_SIGNATURE 0x53434146 /* Firmware ACPI Control Structure */
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#define ACPI_FADT_SIGNATURE 0x50434146 /* Fixed ACPI Description Table */
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#define ACPI_FBPT_SIGNATURE 0x54504246 /* Firmware Boot Performance Table */
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#define ACPI_FPDT_SIGNATURE 0x54445046 /* Firmware Performance Data Table */
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#define ACPI_GTDT_SIGNATURE 0x54445447 /* Generic Timer Description Table */
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#define ACPI_HPET_SIGNATURE 0x54455048 /* High Precision Event Timer */
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#define ACPI_IVRS_SIGNATURE 0x53525649 /* AMD IOMMU Resource Table */
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#define ACPI_MADT_SIGNATURE 0x43495041 /* MADT/APIC Description Table */
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#define ACPI_MCFG_SIGNATURE 0x4746434D /* Memory Mapped Configuration Space Access Table */
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#define ACPI_MPST_SIGNATURE 0x5453504D /* Memory Power State Table*/
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#define ACPI_MSCT_SIGNATURE 0x5443534D /* Maximum System Characteristics Table */
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#define ACPI_NFIT_SIGNATURE 0x5449464E /* NVDIMM Firmware Interface Table */
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#define ACPI_PMMT_SIGNATURE 0x544D4D50 /* Platform Memory Topology Table */
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#define ACPI_PSDT_SIGNATURE 0x54445350 /* Persistent System Description Table */
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#define ACPI_RAS2_SIGNATURE 0x32534152 /* ACPI RAS2 Feature Table */
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#define ACPI_RASF_SIGNATURE 0x46534152 /* ACPI RAS Feature Table */
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#define ACPI_RSDT_SIGNATURE 0x54445352 /* Root System Description Table */
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#define ACPI_SBST_SIGNATURE 0x54534253 /* Smart Battery Subsystem Table */
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#define ACPI_SDEV_SIGNATURE 0x56454453 /* Secure Device Table */
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#define ACPI_SLIT_SIGNATURE 0x54494C53 /* System Locality Distance Information Table */
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#define ACPI_SPCR_SIGNATURE 0x52435053 /* Serial Port Console Redirection Table */
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#define ACPI_SRAT_SIGNATURE 0x54415253 /* Static Resource Affinity Table */
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#define ACPI_SSDT_SIGNATURE 0x54445353 /* Secondary System Descriptor Table */
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#define ACPI_TPM2_SIGNATURE 0x324D5054 /* ACPI TPM 2.0 Table */
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#define ACPI_WAET_SIGNATURE 0x54454157 /* Windows ACPI Enlightenment Table */
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#define ACPI_WDAT_SIGNATURE 0x54414457 /* Watch Dog Action Table */
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#define ACPI_WDTT_SIGNATURE 0x54524457 /* Watchdog Timer Resource Table */
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#define ACPI_WPBT_SIGNATURE 0x54425057 /* Windows Platform Binary Table */
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#define ACPI_WSMT_SIGNATURE 0x544D5357 /* Windows SMM Security Mitigation Table */
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#define ACPI_XSDT_SIGNATURE 0x54445358 /* eXtended System Descriptor Table */
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/* ACPI FADT flags masks */
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#define ACPI_FADT_32BIT_TIMER (1<<8)
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/* ACPI Timer bit masks */
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#define ACPI_FADT_TIMER_32BIT 0x80000000
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#define ACPI_FADT_TIMER_24BIT 0x00800000
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/* ACPI MADT subtable type definitions */
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#define ACPI_MADT_TYPE_LOCAL_APIC 0
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#define ACPI_MADT_TYPE_IOAPIC 1
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#define ACPI_MADT_TYPE_INT_OVERRIDE 2
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#define ACPI_MADT_TYPE_NMI_SOURCE 3
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#define ACPI_MADT_TYPE_LOCAL_APIC_NMI 4
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#define ACPI_MADT_TYPE_LOCAL_APIC_OVERRIDE 5
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#define ACPI_MADT_TYPE_IO_SAPIC 6
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#define ACPI_MADT_TYPE_LOCAL_SAPIC 7
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#define ACPI_MADT_TYPE_INTERRUPT_SOURCE 8
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#define ACPI_MADT_TYPE_LOCAL_X2APIC 9
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#define ACPI_MADT_TYPE_LOCAL_X2APIC_NMI 10
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#define ACPI_MADT_TYPE_GENERIC_INTERRUPT 11
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#define ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR 12
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#define ACPI_MADT_TYPE_GENERIC_MSI_FRAME 13
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#define ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR 14
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#define ACPI_MADT_TYPE_GENERIC_TRANSLATOR 15
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#define ACPI_MADT_TYPE_MULTIPROC_WAKEUP 16
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#define ACPI_MADT_TYPE_CORE_PIC 17
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#define ACPI_MADT_TYPE_LIO_PIC 18
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#define ACPI_MADT_TYPE_HT_PIC 19
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#define ACPI_MADT_TYPE_EIO_PIC 20
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#define ACPI_MADT_TYPE_MSI_PIC 21
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#define ACPI_MADT_TYPE_BIO_PIC 22
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#define ACPI_MADT_TYPE_LPC_PIC 23
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#define ACPI_MADT_TYPE_RINTC 24
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#define ACPI_MADT_TYPE_IMSIC 25
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#define ACPI_MADT_TYPE_APLIC 26
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#define ACPI_MADT_TYPE_PLIC 27
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/* ACPI MADT Processor Local APIC Flags */
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#define ACPI_MADT_PLACE_ENABLED 0 /* Processor Local APIC CPU Enabled */
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#define ACPI_MADT_PLAOC_ENABLED 1 /* Processor Local APIC Online Capable */
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/* Default serial port settings */
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#define COMPORT_CLOCK_RATE 0x1C200
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#define COMPORT_WAIT_TIMEOUT 204800
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/* Serial port divisors */
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#define COMPORT_DIV_DLL 0x00 /* Divisor Latch Least */
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#define COMPORT_DIV_DLM 0x01 /* Divisor Latch Most */
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/* Serial port control flags */
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#define COMPORT_FLAG_INIT 0x01 /* Port Initialized */
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#define COMPORT_FLAG_DBR 0x02 /* Default Baud Rate */
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#define COMPORT_FLAG_MC 0x04 /* Modem Control */
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/* Serial port Fifo Control Register (FCR) access masks */
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#define COMPORT_FCR_DISABLE 0x00 /* Disable */
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#define COMPORT_FCR_ENABLE 0x01 /* Enable */
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#define COMPORT_FCR_RCVR_RESET 0x02 /* Receiver Reset */
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#define COMPORT_FCR_TXMT_RESET 0x04 /* Transmitter Reset */
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/* Serial port Line Control Register (LCR) access masks */
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#define COMPORT_LCR_1STOP 0x00 /* 1 Stop Bit */
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#define COMPORT_LCR_2STOP 0x04 /* 2 Stop Bits */
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#define COMPORT_LCR_5DATA 0x00 /* 5 Data Bits */
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#define COMPORT_LCR_6DATA 0x01 /* 6 Data Bits */
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#define COMPORT_LCR_7DATA 0x02 /* 7 Data Bits */
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#define COMPORT_LCR_8DATA 0x03 /* 8 Data Bits */
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#define COMPORT_LCR_PARN 0x00 /* None Parity */
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#define COMPORT_LCR_PARO 0x08 /* Odd Parity */
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#define COMPORT_LCR_PARE 0x18 /* Even Parity */
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#define COMPORT_LCR_PARM 0x28 /* Mark Parity */
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#define COMPORT_LCR_PARS 0x38 /* Space Parity */
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#define COMPORT_LCR_BREAK 0x40 /* Break */
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#define COMPORT_LCR_DLAB 0x80 /* Divisor Latch Access Bit */
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/* Serial port Line Status Register (LSR) access masks */
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#define COMPORT_LSR_DIS 0x00 /* Disable */
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#define COMPORT_LSR_DR 0x01 /* Data Ready */
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#define COMPORT_LSR_OE 0x02 /* Overrun Error */
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#define COMPORT_LSR_PE 0x04 /* Parity Error */
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#define COMPORT_LSR_FE 0x08 /* Framing Error */
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#define COMPORT_LSR_BI 0x10 /* Break Interrupt */
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#define COMPORT_LSR_THRE 0x20 /* Transmit Holding Register Empty */
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#define COMPORT_LSR_TEMPTY 0x40 /* Transmitter Empty */
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#define COMPORT_LSR_FIFOE 0x80 /* FIFO Error */
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/* Serial port Modem Control Register (MCR) access masks */
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#define COMPORT_MCR_DTR 0x01 /* Data Terminal Ready */
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#define COMPORT_MCR_RTS 0x02 /* Ready To Send */
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#define COMPORT_MCR_OUT1 0x04 /* Generic Output 1 */
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#define COMPORT_MCR_OUT2 0x08 /* Generic Output 2 */
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#define COMPORT_MCR_NOM 0x0F /* Normal Operation Mode */
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#define COMPORT_MCR_LOOP 0x10 /* Loopback Testing Mode */
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/* Serial port Modem Status Register (MSR) access masks */
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#define COMPORT_MSR_DCTS 0x01 /* Delta Clear To Send */
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#define COMPORT_MSR_DDSR 0x02 /* Delta Data Set Ready */
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#define COMPORT_MSR_DTRRTS 0x03 /* DTR and RTS */
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#define COMPORT_MSR_TERI 0x04 /* Trailing Edge Ring Indicator */
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#define COMPORT_MSR_DDCD 0x08 /* Delta Data Carrier Detect */
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#define COMPORT_MSR_CTS 0x10 /* Clear To Send */
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#define COMPORT_MSR_DSR 0x20 /* Data Set Ready */
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#define COMPORT_MSR_RI 0x40 /* Ring Indicator */
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#define COMPORT_MSR_DCD 0x80 /* Data Carrier Detect */
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#define COMPORT_MSR_DSRCTSCD 0xB0 /* DSR, CTS and CD */
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#define COMPORT_MSR_TST 0xAE /* Test Pattern */
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/* Serial port offsets of the various registers */
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#define COMPORT_REG_RBR 0x00 /* Receive Buffer Register */
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#define COMPORT_REG_THR 0x00 /* Transmit Holding Register */
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#define COMPORT_REG_IER 0x01 /* Interrupt Enable Register */
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#define COMPORT_REG_IIR 0x02 /* Interrupt Identity Register */
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#define COMPORT_REG_FCR 0x02 /* FIFO Control Register */
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#define COMPORT_REG_LCR 0x03 /* Line Control Register */
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#define COMPORT_REG_MCR 0x04 /* Modem Control Register */
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#define COMPORT_REG_LSR 0x05 /* Line Status Register */
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#define COMPORT_REG_MSR 0x06 /* Modem Status Register */
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#define COMPORT_REG_SR 0x07 /* Scratch Register */
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/* Generic Address structure */
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typedef struct _GENERIC_ADDRESS
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{
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UCHAR AddressSpaceID;
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UCHAR BitWidth;
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UCHAR BitOffset;
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UCHAR Reserved;
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PHYSICAL_ADDRESS Address;
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} PACKED GENERIC_ADDRESS, *PGENERIC_ADDRESS;
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/* Each ACPI table description header structure */
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typedef struct _ACPI_DESCRIPTION_HEADER
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{
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ULONG Signature;
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ULONG Length;
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UCHAR Revision;
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UCHAR Checksum;
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UCHAR OemId[6];
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UCHAR OemTableID[8];
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ULONG OemRevision;
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UCHAR CreatorID[4];
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ULONG CreatorRev;
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} PACKED ACPI_DESCRIPTION_HEADER, *PACPI_DESCRIPTION_HEADER;
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/* Each ACPI subtable description header structure */
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typedef struct _ACPI_SUBTABLE_HEADER
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{
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UCHAR Type;
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UCHAR Length;
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} PACKED ACPI_SUBTABLE_HEADER, *PACPI_SUBTABLE_HEADER;
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/* ACPI cache list structure */
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typedef struct _ACPI_CACHE_LIST
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{
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LIST_ENTRY ListEntry;
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ACPI_DESCRIPTION_HEADER Header;
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} ACPI_CACHE_LIST, *PACPI_CACHE_LIST;
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/* ACPI Root System Description Table Pointer (RSDP) structure */
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typedef struct _ACPI_RSDP
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{
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ULONGLONG Signature;
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UCHAR Checksum;
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UCHAR OemId[6];
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UCHAR Revision;
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ULONG RsdtAddress;
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ULONG Length;
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ULONGLONG XsdtAddress;
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UCHAR XChecksum;
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UCHAR Reserved[3];
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} PACKED ACPI_RSDP, *PACPI_RSDP;
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/* ACPI Root System Description Table (RSDT) structure */
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typedef struct _ACPI_RSDT
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{
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ACPI_DESCRIPTION_HEADER Header;
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ULONG Tables[];
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} PACKED ACPI_RSDT, *PACPI_RSDT;
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/* ACPI eXtended Root System Description Table (XSDT) structure */
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typedef struct _ACPI_XSDT
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{
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ACPI_DESCRIPTION_HEADER Header;
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ULONGLONG Tables[];
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} PACKED ACPI_XSDT, *PACPI_XSDT;
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/* Fixed ACPI Description Table (FADT) structure */
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typedef struct _ACPI_FADT
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{
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ACPI_DESCRIPTION_HEADER Header;
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ULONG FirmwareCtrl;
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ULONG Dsdt;
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UCHAR IntModel;
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UCHAR PmProfile;
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USHORT SciIntVector;
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ULONG SmiCmdIoPort;
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UCHAR AcpiOnValue;
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UCHAR AcpiOffValue;
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UCHAR S4BiosReq;
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UCHAR PStateControl;
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ULONG Pm1aEvtBlkIoPort;
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ULONG Pm1bEvtBlkIoPort;
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ULONG Pm1aCtrlBlkIoPort;
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ULONG Pm1bCtrlBlkIoPort;
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ULONG Pm2CtrlBlkIoPort;
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ULONG PmTmrBlkIoPort;
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ULONG Gp0BlkIoPort;
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ULONG Gp1BlkIoPort;
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UCHAR Pm1EvtLen;
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UCHAR Pm1CtrlLen;
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UCHAR Pm2CtrlLen;
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UCHAR PmTmrLen;
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UCHAR Gp0BlkLen;
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UCHAR Gp1BlkLen;
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UCHAR Gp1Base;
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UCHAR CStateControl;
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USHORT Lvl2Latency;
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USHORT Lvl3Latency;
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USHORT FlushSize;
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USHORT FlushStride;
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UCHAR DutyOffset;
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UCHAR DutyWidth;
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UCHAR DayAlarmIndex;
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UCHAR MonthAlarmIndex;
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UCHAR CenturyAlarmIndex;
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USHORT BootArch;
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UCHAR Reserved0;
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ULONG Flags;
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GENERIC_ADDRESS ResetReg;
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UCHAR ResetVal;
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USHORT ArmBootArch;
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UCHAR Reserved1;
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PHYSICAL_ADDRESS XFirmwareCtrl;
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PHYSICAL_ADDRESS XDsdt;
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GENERIC_ADDRESS XPm1aEvtBlk;
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GENERIC_ADDRESS XPm1bEvtBlk;
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GENERIC_ADDRESS XPm1aCtrlBlk;
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GENERIC_ADDRESS XPm1bCtrlBlk;
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GENERIC_ADDRESS XPm2CtrlBlk;
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GENERIC_ADDRESS XPmTmrBlk;
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GENERIC_ADDRESS XGp0Blk;
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GENERIC_ADDRESS XGp1Blk;
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GENERIC_ADDRESS SleepControlReg;
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GENERIC_ADDRESS SleepStatusReg;
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} PACKED ACPI_FADT, *PACPI_FADT;
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/* ACPI Multiple APIC Description Table (MADT) structure */
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typedef struct _ACPI_MADT
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{
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ACPI_DESCRIPTION_HEADER Header;
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ULONG LocalApicAddress;
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ULONG Flags;
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ULONG ApicTables[];
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} PACKED ACPI_MADT, *PACPI_MADT;
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/* ACPI Local APIC MADT subtable structure */
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typedef struct _ACPI_MADT_LOCAL_APIC
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{
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ACPI_SUBTABLE_HEADER Header;
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UCHAR AcpiId;
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UCHAR ApicId;
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ULONG Flags;
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} PACKED ACPI_MADT_LOCAL_APIC, *PACPI_MADT_LOCAL_APIC;
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/* ACPI Local X2APIC MADT subtable structure */
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typedef struct _ACPI_MADT_LOCAL_X2APIC
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{
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ACPI_SUBTABLE_HEADER Header;
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USHORT Reserved;
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ULONG ApicId;
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ULONG Flags;
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ULONG AcpiId;
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} PACKED ACPI_MADT_LOCAL_X2APIC, *PACPI_MADT_LOCAL_X2APIC;
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/* ACPI System Information structure */
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typedef struct _ACPI_SYSTEM_INFO
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{
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ULONG CpuCount;
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ULONG RunningCpus;
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ULONG BusCount;
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ULONG IoApicCount;
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ULONG IntiCount;
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ULONG LintiCount;
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BOOLEAN ImcrPresent;
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ULONG ApicBase;
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PPROCESSOR_IDENTITY CpuInfo;
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ULONG IoApicPhysicalBase[APIC_MAX_IOAPICS];
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ULONG IoApicVirtualBase[APIC_MAX_IOAPICS];
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ULONG IoApicVectorBase[APIC_MAX_IOAPICS];
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} ACPI_SYSTEM_INFO, *PACPI_SYSTEM_INFO;
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/* ACPI Timer information structure */
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typedef struct _ACPI_TIMER_INFO
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{
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ULONG TimerPort;
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ULONG MsbMask;
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} ACPI_TIMER_INFO, *PACPI_TIMER_INFO;
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/* Serial (COM) port state */
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typedef struct _CPPORT
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{
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PUCHAR Address;
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ULONG Baud;
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USHORT Flags;
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UCHAR Ring;
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} CPPORT, *PCPPORT;
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/* Framebuffer data structure */
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typedef struct _HL_FRAMEBUFFER_DATA
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{
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BOOLEAN Initialized;
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PVOID Address;
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ULONG_PTR BufferSize;
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UINT Width;
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UINT Height;
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UINT PixelsPerScanLine;
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UINT BytesPerPixel;
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UINT Pitch;
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PVOID Font;
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struct
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{
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USHORT BlueShift;
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USHORT BlueSize;
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USHORT GreenShift;
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USHORT GreenSize;
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USHORT RedShift;
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USHORT RedSize;
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USHORT ReservedShift;
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USHORT ReservedSize;
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} Pixels;
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} HL_FRAMEBUFFER_DATA, *PHL_FRAMEBUFFER_DATA;
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/* Scroll region data structure */
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typedef struct _HL_SCROLL_REGION_DATA
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{
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ULONG Left;
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ULONG Top;
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ULONG Right;
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ULONG Bottom;
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ULONG WidthInChars;
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ULONG HeightInChars;
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ULONG CursorX;
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ULONG CursorY;
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ULONG BackgroundColor;
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ULONG TextColor;
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} HL_SCROLL_REGION_DATA, *PHL_SCROLL_REGION_DATA;
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/* Processor identity structure */
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typedef struct _PROCESSOR_IDENTITY
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{
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ULONG AcpiId;
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ULONG ApicId;
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USHORT CpuNumber;
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BOOLEAN Bsp;
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BOOLEAN Started;
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} PROCESSOR_IDENTITY, *PPROCESSOR_IDENTITY;
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/* SMBIOS table header structure */
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typedef struct _SMBIOS_TABLE_HEADER
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{
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UCHAR Signature[4];
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UCHAR Checksum;
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UCHAR Length;
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UCHAR MajorVersion;
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UCHAR MinorVersion;
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USHORT MaxStructureSize;
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UCHAR EntryPointRevision;
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UCHAR Reserved[5];
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UCHAR Signature2[5];
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UCHAR IntermediateChecksum;
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USHORT TableLength;
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ULONG TableAddress;
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USHORT NumberOfStructures;
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UCHAR BcdRevision;
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} SMBIOS_TABLE_HEADER, *PSMBIOS_TABLE_HEADER;
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/* SMBIOS3 table header structure */
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typedef struct _SMBIOS3_TABLE_HEADER
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{
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UCHAR Signature[5];
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UCHAR Checksum;
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UCHAR Length;
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UCHAR MajorVersion;
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|
UCHAR MinorVersion;
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|
UCHAR DocRevision;
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|
UCHAR EntryPointRevision;
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|
UCHAR Reserved;
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|
ULONG MaxStructureSize;
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|
ULONGLONG TableAddress;
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|
} SMBIOS3_TABLE_HEADER, *PSMBIOS3_TABLE_HEADER;
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#endif /* __XTDK_HLTYPES_H */
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