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Tweaks to AMD64 architecture support

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This commit is contained in:
Rafal Kupiec 2024-04-19 23:37:39 +02:00
parent b30d15719c
commit 28c89986fb
Signed by: belliash
GPG Key ID: 4E829243E0CFE6B4
1 changed files with 9 additions and 1 deletions
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10
xtoskrnl/ar/amd64/procsup.c
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@ -56,7 +56,6 @@ ArInitializeProcessor(VOID)
ArLoadTaskRegister((UINT)KGDT_SYS_TSS);
/* Enter passive IRQ level */
ProcessorBlock->RunLevel = PASSIVE_LEVEL;
ArWriteControlRegister(8, PASSIVE_LEVEL);
/* Initialize segment registers */
@ -321,6 +320,9 @@ ArpInitializeProcessorBlock(OUT PKPROCESSOR_BLOCK ProcessorBlock,
/* Set initial MXCSR register value */
ProcessorBlock->Prcb.MxCsr = INITIAL_MXCSR;
/* Set initial runlevel */
ProcessorBlock->RunLevel = PASSIVE_LEVEL;
}
/**
@ -345,6 +347,9 @@ ArpInitializeProcessorRegisters(VOID)
/* Set debugger extension */
ArWriteControlRegister(4, ArReadControlRegister(4) | CR4_DE);
/* Enable large pages */
ArWriteControlRegister(4, ArReadControlRegister(4) | CR4_PSE);
/* Enable write-protection */
ArWriteControlRegister(0, ArReadControlRegister(0) | CR0_WP);
@ -357,6 +362,9 @@ ArpInitializeProcessorRegisters(VOID)
/* Disable x87 FPU exceptions */
ArWriteControlRegister(0, ArReadControlRegister(0) & ~CR0_NE);
/* Flush the TLB */
ArFlushTlb();
/* Initialize system calls MSR */
ArWriteModelSpecificRegister(X86_MSR_STAR, (((ULONG64)KGDT_R3_CMCODE | RPL_MASK) << 48) | ((ULONG64)KGDT_R0_CODE << 32));
ArWriteModelSpecificRegister(X86_MSR_CSTAR, (ULONG64)&ArpHandleSystemCall32);