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Author SHA1 Message Date
Aiken Harris
3c25934495
Add explanatory comments to string handling code 2025-09-02 19:31:13 +02:00
Aiken Harris
e23a4c71a2
Fix framebuffer address calculations by using Pitch and BytesPerPixel 2025-09-02 12:42:06 +02:00
Aiken Harris
6ee7243e04
Refactor APIC delivery mode handling and unify naming 2025-09-01 19:54:12 +02:00
Aiken Harris
d45cc5ffe5
Fix incorrect APIC delivery mode definitions 2025-09-01 19:32:29 +02:00
Aiken Harris
3c8b7cb1f2
Remove unused variable 2025-09-01 19:25:45 +02:00
Aiken Harris
2e415f6ec2
Remove broadcast INIT IPI 2025-09-01 19:23:02 +02:00
Aiken Harris
5ff9303bd1
Add debug screen clear at end of kernel initialization 2025-09-01 16:27:28 +02:00
Aiken Harris
84ac8f00e0
Fix APIC initialization and refine comments 2025-09-01 15:41:06 +02:00
Aiken Harris
418ff68be4
Add ESP boot support and improve block device enumeration 2025-09-01 14:02:38 +02:00
Aiken Harris
2d1b6363e6
Add CTRL-B shortcut to boot OS directly from edit menu 2025-09-01 12:43:33 +02:00
Aiken Harris
34cebf2810
Allow editing boot options using 'e' key 2025-09-01 11:47:36 +02:00
Aiken Harris
0fa4a175e0
Correct Backspace behavior in input dialog 2025-09-01 11:40:48 +02:00
Aiken Harris
72a832f190
Fix type mismatch in BlGetEditableOptions OptionsCount parameter 2025-08-30 20:35:01 +02:00
Aiken Harris
ba65264d1e
Remove unnecessary console input buffer reset 2025-08-27 22:21:39 +02:00
Aiken Harris
2ee33ab229
Refactor BlGetConfigValue to return EFI_STATUS and output value via parameter 2025-08-27 19:44:52 +02:00
Aiken Harris
1eea654a36
Expose BlGetBootOptionValue, BlGetEditableOptions and BlSetBootOptionValue 2025-08-27 19:26:01 +02:00
Aiken Harris
c6643125e1
Implement boot entry editor 2025-08-27 19:15:38 +02:00
Aiken Harris
b68514b176
Limit boot menu entry names to available menu width 2025-08-25 19:03:57 +02:00
Aiken Harris
960e913222
Optimize boot menu drawing to eliminate screen flickering 2025-08-25 17:56:40 +02:00
Aiken Harris
e99e563aff
Correct .modinfo section parsing 2025-08-25 12:07:49 +02:00
Aiken Harris
0b40a3fb10
Refactor MMU for multi-paging support and add 5-Level paging 2025-08-23 20:03:56 +02:00
Aiken Harris
a84ef21571
Adjust LA57 base addresses to prevent overflow 2025-08-21 01:42:36 +02:00
Aiken Harris
1ef2560ef6
Enable LA57 by invoking the trampoline code 2025-08-21 00:14:49 +02:00
Aiken Harris
d1b14fccdd
Resolve build issues caused by the last commit 2025-08-20 21:08:43 +02:00
Aiken Harris
88b3a57962
Allow specifying an allocation type when allocating pages 2025-08-20 20:59:31 +02:00
Aiken Harris
9f6121e9b2
Map the physical page for trampoline code 2025-08-20 20:37:55 +02:00
Aiken Harris
4a7ea6009d
Expose ArEnableExtendedPhysicalAddressing function in XTDK 2025-08-20 20:23:44 +02:00
Aiken Harris
c4a7df6f38
Extract trampoline code into a separate file 2025-08-20 20:20:35 +02:00
Aiken Harris
2468d80078
Add trampoline to enable 5-level paging 2025-08-20 00:20:10 +02:00
Aiken Harris
ebae8c655c
Expand CR4, MSR, and EFER register definitions 2025-08-19 23:59:58 +02:00
Aiken Harris
1a0bc7f65f
Update and correct CR4 bit definitions 2025-08-19 21:45:13 +02:00
Aiken Harris
91a5db2ee4
Implement PML5 support in XtpMapHardwareMemoryPool 2025-08-18 12:13:48 +02:00
Aiken Harris
b639bf3077
Implement PML5 self-mapping 2025-08-18 11:59:05 +02:00
Aiken Harris
c409400cbf
Correct VA masking in AMD64 page mapping functions 2025-08-18 01:07:28 +02:00
Aiken Harris
d602038858
Temporarily disable LA57 paging 2025-08-18 00:10:32 +02:00
Aiken Harris
017b8603d5
Align parameters in PTE manipulation functions 2025-08-17 21:55:21 +02:00
Aiken Harris
a9dd1eaacd
Implement MmpSetPteCaching function for AMD64 architecture 2025-08-17 21:51:43 +02:00
Aiken Harris
f30d3df5b3
Implement PTE manipulation functions for AMD64 architecture 2025-08-17 21:48:28 +02:00
Aiken Harris
c3ece4f317
Fix type usage in XtpMapHardwareMemoryPool 2025-08-17 00:51:26 +02:00
Aiken Harris
1e11acee72
Refactor hardware memory mapping to use page map routine callbacks 2025-08-17 00:47:56 +02:00
Aiken Harris
57193eecc0
Implement PML2/PML3 page table routines 2025-08-17 00:45:12 +02:00
Aiken Harris
720d525b95
Assign page map routines 2025-08-17 00:29:28 +02:00
Aiken Harris
f77f2bbf92
Introduce architecture-specific page map routines 2025-08-17 00:23:19 +02:00
Aiken Harris
0ed59f223c
Relocate page mapping helpers and add PML5 support 2025-08-16 21:07:54 +02:00
Aiken Harris
de2973ac42
Implement page map info initialization 2025-08-16 20:28:05 +02:00
Aiken Harris
8491e5fed1
Remove PageMapLevel from the loader information block 2025-08-16 20:18:34 +02:00
Aiken Harris
6a330e38f2
Consolidate paging-related globals into MmpPageMapInfo 2025-08-16 20:14:18 +02:00
Aiken Harris
1dcd3fceed
Define page map information structure for both supported architectures 2025-08-16 20:08:12 +02:00
Aiken Harris
5768d4bba6
Prepare for architecture-specific paging initialization 2025-08-16 19:58:00 +02:00
Aiken Harris
f85fe31b38
Adapt i686 memory mapping to new PML3 types 2025-08-16 00:36:20 +02:00