Initialize AMD64 processor registers

sdk/xtdk/amd64/artypes.h

@@ -82,6 +82,25 @@
 #define X86_MSR_EFER_NXE                                (1 << 11)
 #define X86_MSR_EFER_SVME                               (1 << 12)
 
+/* X86 EFLAG bit masks definitions */
+#define X86_EFLAGS_CF_MASK                              0x00000001
+#define X86_EFLAGS_PF_MASK                              0x00000004
+#define X86_EFALGS_AF_MASK                              0x00000010
+#define X86_EFLAGS_ZF_MASK                              0x00000040
+#define X86_EFLAGS_SF_MASK                              0x00000080
+#define X86_EFLAGS_TF_MASK                              0x00000100
+#define X86_EFLAGS_IF_MASK                              0x00000200
+#define X86_EFLAGS_DF_MASK                              0x00000400
+#define X86_EFLAGS_OF_MASK                              0x00000800
+#define X86_EFLAGS_IOPL_MASK                            0x00003000
+#define X86_EFLAGS_NT_MASK                              0x00004000
+#define X86_EFLAGS_RF_MASK                              0x00010000
+#define X86_EFLAGS_VM_MASK                              0x00020000
+#define X86_EFLAGS_AC_MASK                              0x00040000
+#define X86_EFLAGS_VIF_MASK                             0x00080000
+#define X86_EFLAGS_VIP_MASK                             0x00100000
+#define X86_EFLAGS_ID_MASK                              0x00200000
+
 /* CPUID features enumeration list */
 typedef enum _CPUID_FEATURES
 {

xtoskrnl/ar/amd64/procsup.c

@@ -63,6 +63,9 @@ ArInitializeProcessor(VOID)
     /* Set GS base */
     ArWriteModelSpecificRegister(X86_MSR_GSBASE, (ULONGLONG)ProcessorBlock);
     ArWriteModelSpecificRegister(X86_MSR_KERNEL_GSBASE, (ULONGLONG)ProcessorBlock);
+
+    /* Initialize processor registers */
+    ArpInitializeProcessorRegisters();
 }
 
 /**
@@ -195,6 +198,57 @@ ArpInitializeProcessorBlock(OUT PKPROCESSOR_BLOCK ProcessorBlock,
     ProcessorBlock->Prcb.MxCsr = INITIAL_MXCSR;
 }
 
+/**
+ * Initializes processor registers and other boot structures.
+ *
+ * @return This routine does not return any value.
+ *
+ * @since XT 1.0
+ */
+XTAPI
+VOID
+ArpInitializeProcessorRegisters(VOID)
+{
+    /* Enable FXSAVE restore */
+    ArWriteControlRegister(4, ArReadControlRegister(4) | CR4_FXSR);
+
+    /* Enable XMMI exceptions */
+    ArWriteControlRegister(4, ArReadControlRegister(4) | CR4_XMMEXCPT);
+
+    /* Set debugger extension */
+    ArWriteControlRegister(4, ArReadControlRegister(4) | CR4_DE);
+
+    /* Enable global paging support */
+    ArWriteControlRegister(4, ArReadControlRegister(4) | CR4_PGE);
+
+    /* Enable large pages */
+    ArWriteControlRegister(4, ArReadControlRegister(4) | CR4_PSE);
+
+    /* Enable write-protection */
+    ArWriteControlRegister(0, ArReadControlRegister(0) | CR0_WP);
+
+    /* Set alignment mask */
+    ArWriteControlRegister(0, ArReadControlRegister(0) | CR0_AM);
+
+    /* Disable FPU monitoring */
+    ArWriteControlRegister(0, ArReadControlRegister(0) & ~CR0_MP);
+
+    /* Disable x87 FPU exceptions */
+    ArWriteControlRegister(0, ArReadControlRegister(0) & ~CR0_NE);
+
+    /* Initialize system calls MSR */
+    ArWriteModelSpecificRegister(X86_MSR_STAR, (((ULONG64)KGDT_R3_CMCODE | RPL_MASK) << 48) | ((ULONG64)KGDT_R0_CODE << 32));
+    ArWriteModelSpecificRegister(X86_MSR_CSTAR, (ULONG64)&ArpHandleSystemCall32);
+    ArWriteModelSpecificRegister(X86_MSR_LSTAR, (ULONG64)&ArpHandleSystemCall64);
+    ArWriteModelSpecificRegister(X86_MSR_FMASK, X86_EFLAGS_IF_MASK | X86_EFLAGS_TF_MASK);
+
+    /* Enable system call extensions (SCE) in EFER MSR */
+    ArWriteModelSpecificRegister(X86_MSR_EFER, ArReadModelSpecificRegister(X86_MSR_EFER) | X86_MSR_EFER_SCE);
+
+    /* Enable No-Execute (NXE) in EFER MSR */
+    ArWriteModelSpecificRegister(X86_MSR_EFER, ArReadModelSpecificRegister(X86_MSR_EFER) | X86_MSR_EFER_NXE);
+}
+
 /**
  * Initializes segment registers.
  *

xtoskrnl/ar/amd64/traps.c

@@ -9,6 +9,20 @@
 #include <xtos.h>
 
 
+XTCDECL
+VOID
+ArpHandleSystemCall32()
+{
+    LdrPrint(L"Handled 32-bit system call!\n");
+}
+
+XTCDECL
+VOID
+ArpHandleSystemCall64()
+{
+    LdrPrint(L"Handled 64-bit system call!\n");
+}
+
 /**
  * Handles the trap 0x00 when a Divide By Zero exception occurs.
  *

xtoskrnl/includes/arpfuncs.h

@@ -12,6 +12,14 @@
 #include <xtos.h>
 
 
+XTCDECL
+VOID
+ArpHandleSystemCall32();
+
+XTCDECL
+VOID
+ArpHandleSystemCall64();
+
 XTCDECL
 VOID
 ArpHandleTrap00();
@@ -116,6 +124,10 @@ ArpInitializeProcessorBlock(OUT PKPROCESSOR_BLOCK ProcessorBlock,
                             IN PKTSS Tss,
                             IN PVOID DpcStack);
 
+XTAPI
+VOID
+ArpInitializeProcessorRegisters(VOID);
+
 XTAPI
 VOID
 ArpInitializeSegments(VOID);

xtoskrnl/ke/amd64/krnlinit.c

@@ -20,21 +20,9 @@ XTAPI
 VOID
 KepArchInitialize(VOID)
 {
-    /* Enable global paging support */
-    ArWriteControlRegister(4, ArReadControlRegister(4) | CR4_PGE);
-
-    /* Enable write-protection */
-    ArWriteControlRegister(0, ArReadControlRegister(0) | CR0_WP);
-
-    /* Set alignment mask */
-    ArWriteControlRegister(0, ArReadControlRegister(0) | CR0_AM);
-
     /* Re-enable IDE interrupts */
     HlIoPortOutByte(0x376, 0);
     HlIoPortOutByte(0x3F6, 0);
-
-    /* Set system call extensions (SCE) flag in EFER MSR */
-    ArWriteModelSpecificRegister(X86_MSR_EFER, ArReadModelSpecificRegister(X86_MSR_EFER) | X86_MSR_EFER_SCE);
 }
 
 /**