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Initialize IDT with specific trap handlers for each vector

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This commit is contained in:
Aiken Harris
2026-03-27 19:16:16 +01:00
parent a64aa83eb8
commit 9c449bed43
6 changed files with 27 additions and 3 deletions
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9
xtoskrnl/ar/amd64/archsup.S
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@@ -187,3 +187,12 @@ KernelModeReturn$\Vector:
ArCreateTrapHandler 0x\i\j ArCreateTrapHandler 0x\i\j
.endr .endr
.endr .endr
/* Define array of pointers to the trap handlers */
.global ArTrapEntry
ArTrapEntry:
.irp i,0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F
.irp j,0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F
.quad ArTrap0x\i\j
.endr
.endr

2
xtoskrnl/ar/amd64/procsup.cc
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@@ -249,7 +249,7 @@ AR::ProcSup::InitializeIdt(IN PKPROCESSOR_BLOCK ProcessorBlock)
for(Vector = 0; Vector < IDT_ENTRIES; Vector++) for(Vector = 0; Vector < IDT_ENTRIES; Vector++)
{ {
/* Set the IDT to handle unexpected interrupts */ /* Set the IDT to handle unexpected interrupts */
SetIdtGate(ProcessorBlock->IdtBase, Vector, (PVOID)ArTrap0xFF, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0, AMD64_INTERRUPT_GATE); SetIdtGate(ProcessorBlock->IdtBase, Vector, (PVOID)ArTrapEntry[Vector], KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0, AMD64_INTERRUPT_GATE);
} }
/* Setup IDT handlers for known interrupts and traps */ /* Setup IDT handlers for known interrupts and traps */

11
xtoskrnl/ar/i686/archsup.S
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@@ -82,7 +82,7 @@ _ArTrap\Vector:
jmp UserMode$\Vector jmp UserMode$\Vector
KernelMode$\Vector: KernelMode$\Vector:
/* Save kernel stack pointer (SS:ESP) as CPU did not push them */ /* Save kernel stack pointer (SS:ESP) */
movl %ss, %eax movl %ss, %eax
mov %eax, TrapSegSs(%ebp) mov %eax, TrapSegSs(%ebp)
lea TrapEsp(%ebp), %eax lea TrapEsp(%ebp), %eax
@@ -133,3 +133,12 @@ KernelModeReturn$\Vector:
ArCreateTrapHandler 0x\i\j ArCreateTrapHandler 0x\i\j
.endr .endr
.endr .endr
/* Define array of pointers to the trap handlers */
.global ArTrapEntry
ArTrapEntry:
.irp i,0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F
.irp j,0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F
.long ArTrap0x\i\j
.endr
.endr

2
xtoskrnl/ar/i686/procsup.cc
View File

@@ -242,7 +242,7 @@ AR::ProcSup::InitializeIdt(IN PKPROCESSOR_BLOCK ProcessorBlock)
for(Vector = 0; Vector < IDT_ENTRIES; Vector++) for(Vector = 0; Vector < IDT_ENTRIES; Vector++)
{ {
/* Set the IDT to handle unexpected interrupts */ /* Set the IDT to handle unexpected interrupts */
SetIdtGate(ProcessorBlock->IdtBase, Vector, (PVOID)ArTrap0xFF, KGDT_R0_CODE, 0, KIDT_ACCESS_RING0, I686_INTERRUPT_GATE); SetIdtGate(ProcessorBlock->IdtBase, Vector, (PVOID)ArTrapEntry[Vector], KGDT_R0_CODE, 0, KIDT_ACCESS_RING0, I686_INTERRUPT_GATE);
} }
/* Setup IDT handlers for known interrupts and traps */ /* Setup IDT handlers for known interrupts and traps */

3
xtoskrnl/includes/ar/amd64/procsup.hh
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@@ -12,6 +12,9 @@
#include <xtos.hh> #include <xtos.hh>
/* External array of pointers to the trap handlers */
XTCLINK ULONG_PTR ArTrapEntry[256];
/* Architecture-specific Library */ /* Architecture-specific Library */
namespace AR namespace AR
{ {

3
xtoskrnl/includes/ar/i686/procsup.hh
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@@ -12,6 +12,9 @@
#include <xtos.hh> #include <xtos.hh>
/* External array of pointers to the trap handlers */
XTCLINK ULONG_PTR ArTrapEntry[256];
/* Architecture-specific Library */ /* Architecture-specific Library */
namespace AR namespace AR
{ {