Implement memory barriers

xtoskrnl/ar/i686/cpufunc.c

@@ -252,6 +252,24 @@ ArLoadTaskRegister(USHORT Source)
                  : "rm" (Source));
 }
 
+/**
+ * Orders memory accesses as seen by other processors.
+ *
+ * @return This routine does not return any value.
+ *
+ * @since XT 1.0
+ */
+XTCDECL
+VOID
+ArMemoryBarrier()
+{
+   LONG Barrier;
+   asm volatile("xchg %%eax, %0"
+                :
+                : "m" (Barrier)
+                : "%eax");
+}
+
 /**
  * Reads the specified CPU control register and returns its value.
  *
@@ -454,6 +472,23 @@ ArReadTimeStampCounter()
     return Value;
 }
 
+/**
+ * Orders memory accesses as seen by other processors, without fence.
+ *
+ * @return This routine does not return any value.
+ *
+ * @since XT 1.0
+ */
+XTCDECL
+VOID
+ArReadWriteBarrier()
+{
+    asm volatile(""
+                 :
+                 :
+                 : "memory");
+}
+
 /**
  * Instructs the processor to set the interrupt flag.
  *