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Author	SHA1	Message	Date
Aiken Harris	7f0ca6a948	Compute PTE count per page from entry size	2025-12-15 13:56:39 +01:00
Aiken Harris	36c273ea13	Implement early page table mapping routines	2025-12-15 13:24:02 +01:00
Aiken Harris	5cf3dfa844	Add bootstrap physical page allocator	2025-12-15 12:38:08 +01:00
Aiken Harris	070c508e42	Introduce kernel virtual memory layout	2025-12-14 15:35:24 +01:00
Aiken Harris	5224dc315f	Compute PFN database size during MM initialization	2025-12-13 22:50:27 +01:00
Aiken Harris	b7bbf9ffa8	Tidy up memory type verification helpers	2025-12-13 21:04:55 +01:00
Aiken Harris	eae48320f3	Harden PFN initialization and expose page count	2025-12-13 21:01:13 +01:00
Aiken Harris	17b5649362	Make memory type verification helpers accessible to PFN	2025-12-13 20:50:32 +01:00
Aiken Harris	783a9eea3a	Extract PFN management into separate module	2025-12-13 20:42:48 +01:00
Aiken Harris	237f6a2974	Refactor memory manager initialization into MM::Manager	2025-12-13 20:21:08 +01:00
Aiken Harris	ee9514fd5c	Fix GetP5eAddress return type	2025-12-13 19:58:49 +01:00
Aiken Harris	63c27a149a	Add missing virtual GetPteDistance to pagemap interface	2025-12-06 00:29:51 +01:00
Aiken Harris	7694df7744	Add architecture-specific GetPteDistance	2025-12-06 00:19:24 +01:00
Aiken Harris	c710ec4688	Refactor XPA detection API	2025-12-04 23:07:59 +01:00
Aiken Harris	8054bb915a	Fix incorrect pointer types	2025-11-30 20:06:51 +01:00
Aiken Harris	86aa22e5f8	Fix incorrect pointer types	2025-11-30 20:03:12 +01:00
Aiken Harris	4a7494ad3f	Split paging interface into arch-specific code	2025-11-30 19:19:32 +01:00
Aiken Harris	d4287198b0	Implement virtual address resolvers for all page map levels and add XPA status accessor	2025-11-30 18:23:51 +01:00
Aiken Harris	4265ae92d0	Add MM::PageMap::GetXpaStatus() for querying PML level	2025-11-29 23:45:00 +01:00
Aiken Harris	931586eebd	Refactor PageMap to enable architecture-specific VA translation	2025-11-29 23:37:08 +01:00
Aiken Harris	c099882866	Add PFN_COUNT typedef	2025-11-29 23:14:30 +01:00
Aiken Harris	0097cb88d7	Correct LA57 paging base addresses, add self-map constants and extend PTE structures	2025-11-29 23:11:54 +01:00
Aiken Harris	20b0bfdfad	Add kernel parameters section and fix minor formatting issues	2025-11-17 23:19:16 +01:00
Aiken Harris	35523a230a	Prevent duplicate object generation by linking xtoskrnl with libxtos	2025-11-17 23:15:22 +01:00
Aiken Harris	7b11a8feb1	Add page list and PTE pool type enums	2025-11-06 06:55:31 +01:00
Aiken Harris	0cf178a648	Fix class name	2025-11-04 23:10:02 +01:00
Aiken Harris	66f27e4b9a	Add GetPageFrameNumber() to PTE interfaces	2025-11-04 23:03:47 +01:00
Aiken Harris	10b8ab347a	Make MM::Paging::GetExtendedPhysicalAddressingStatus public	2025-11-04 22:51:34 +01:00
Aiken Harris	071c840ca8	Replace writable flag with AttributesMask in PTE setup	2025-11-04 17:34:49 +01:00
Aiken Harris	dda8f88830	Add PTE attribute definitions	2025-11-04 17:26:47 +01:00
Aiken Harris	cb2da54956	Unify PTE pointer types across MM subsystem	2025-11-03 22:13:32 +01:00
Aiken Harris	fd13091476	Unify MMPML2_PTE field naming convention	2025-11-03 22:02:59 +01:00
Aiken Harris	c28c3f8344	Add input qualifiers to page map interface definitions	2025-11-03 20:04:21 +01:00
Aiken Harris	dfb0284427	Add input qualifiers to paging interface definitions	2025-11-03 16:00:46 +01:00
Aiken Harris	1150b9ecdb	Add PTE management routines	2025-10-30 22:03:25 +01:00
Aiken Harris	f6dac12057	Add missing EmptyPteList field to MMPAGEMAP_INFO	2025-10-30 20:19:35 +01:00
Aiken Harris	ffa480d69a	Implement unified PTE accessors and management helpers	2025-10-30 20:14:02 +01:00
Aiken Harris	0120ba167f	Introduce RAII helpers for runlevel transitions	2025-10-29 23:07:27 +01:00
Aiken Harris	4e9dc15501	Define VIRTUAL macro	2025-10-29 22:32:07 +01:00
Aiken Harris	164ff0c135	Expand spinlock queue levels	2025-10-28 08:35:34 +01:00
Aiken Harris	f538d035e2	Introduce global spinlock initialization and RAII guard classes	2025-10-27 20:48:44 +01:00
Aiken Harris	72b92f853e	Use PTE base from PageMapInfo	2025-10-23 08:54:57 +02:00
Aiken Harris	00b04f5405	Refactor IDT gate setup to use explicit DPL and type fields	2025-10-18 18:29:49 +02:00
Aiken Harris	52afd31e77	Implement Stage2 loading in VBR code	2025-10-17 20:44:57 +02:00
Aiken Harris	7f06abf236	New message for unsupported CPUs	2025-10-17 09:18:49 +02:00
Aiken Harris	4f4df52d3d	Include architecture-specific code in VBR	2025-10-17 09:12:54 +02:00
Aiken Harris	764fec4d75	Implement low-level CPU initialization support for i686 and AMD64 boot sectors	2025-10-17 09:05:24 +02:00
Aiken Harris	ca8a539c0e	Change message labels naming convention	2025-10-17 08:58:41 +02:00
Aiken Harris	c206b443ed	Move XTLDR image base definition to arch-specific config	2025-10-16 12:22:30 +02:00
Aiken Harris	b19b27a621	Build relocatable image to allow proper UEFI loading	2025-10-16 12:10:00 +02:00