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6 Commits

Author SHA1 Message Date
d8e50bde48 Complete ArpIdentifyProcessor unimplemented logic
- Fixes CPUID VendorName
- Fixes Model on AMD Family 0x19
- Stores raw CPU features to PRCB
2024-05-06 17:20:02 +02:00
a53f53263d Add missing CPU_FEATURES typedef 2024-05-06 17:20:02 +02:00
d13bdf3930 Add CPU features to PRCB 2024-05-06 17:20:02 +02:00
e28ab2fbed Add CPU features struct 2024-05-06 17:20:02 +02:00
243aacc9c1
Cleanup thread context initialization code 2024-05-06 16:57:29 +02:00
cf0d23b6fe
Correct a typo causing page fault during int handling after switching to new kernel stack 2024-05-06 16:47:12 +02:00
3 changed files with 3 additions and 9 deletions

View File

@ -102,7 +102,7 @@ ArpTrap\Vector:
movdqa %xmm0, TrapXmm0(%rbp)
/* Test previous mode and swap GS if needed */
movl $0, TrapPreviousMode(%ebp)
movl $0, TrapPreviousMode(%rbp)
mov %cs, %ax
and $1, %al
mov %al, TrapPreviousMode(%rbp)

View File

@ -82,7 +82,7 @@ KepInitializeThreadContext(IN PKTHREAD Thread,
ThreadFrame->TrapFrame.Dr7 = 0;
/* Set initial MXCSR register value */
// ThreadFrame->TrapFrame.MxCsr = INITIAL_MXCSR;
ThreadFrame->TrapFrame.MxCsr = INITIAL_MXCSR;
/* Initialize exception frame */
ThreadFrame->ExceptionFrame.P1Home = (ULONG64)StartContext;

View File

@ -80,19 +80,13 @@ KepInitializeThreadContext(IN PKTHREAD Thread,
ThreadFrame->TrapFrame.Dr6 = 0;
ThreadFrame->TrapFrame.Dr7 = 0;
/* Set exception list pointer in the trap frame */
// ThreadFrame->TrapFrame.ExceptionList = (PEXCEPTION_REGISTRATION_RECORD) - 1;
/* Set DS, ES and SS segments for user mode */
ThreadFrame->TrapFrame.SegDs |= RPL_MASK;
ThreadFrame->TrapFrame.SegEs |= RPL_MASK;
ThreadFrame->TrapFrame.SegSs |= RPL_MASK;
/* Set debug mark in the trap frame */
// ThreadFrame->TrapFrame.DbgMark = 0x8BADF00D;
/* Set user mode thread in the trap frame */
// ThreadFrame->TrapFrame.PreviousMode = UserMode;
ThreadFrame->TrapFrame.PreviousMode = UserMode;
}
else
{