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Align parameters in PTE manipulation functions
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This commit is contained in:
Aiken Harris 2025-08-17 21:55:21 +02:00
parent a9dd1eaacd
commit 017b8603d5
Signed by: harraiken
GPG Key ID: C40F06CB7493C1F5
1 changed files with 8 additions and 8 deletions
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16
xtoskrnl/mm/i686/pmap.c
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@ -137,8 +137,8 @@ MmpPml2PteValid(PHARDWARE_PTE PtePointer)
XTAPI
VOID
MmpSetPml2Pte(PHARDWARE_PTE PtePointer,
PFN_NUMBER PageFrameNumber,
BOOLEAN Writable)
PFN_NUMBER PageFrameNumber,
BOOLEAN Writable)
{
PtePointer->Pml2.PageFrameNumber = PageFrameNumber;
PtePointer->Pml2.Valid = 1;
@ -164,8 +164,8 @@ MmpSetPml2Pte(PHARDWARE_PTE PtePointer,
XTAPI
VOID
MmpSetPml2PteCaching(PHARDWARE_PTE PtePointer,
BOOLEAN CacheDisable,
BOOLEAN WriteThrough)
BOOLEAN CacheDisable,
BOOLEAN WriteThrough)
{
PtePointer->Pml2.CacheDisable = CacheDisable;
PtePointer->Pml2.WriteThrough = WriteThrough;
@ -207,8 +207,8 @@ MmpPml3PteValid(PHARDWARE_PTE PtePointer)
XTAPI
VOID
MmpSetPml3Pte(PHARDWARE_PTE PtePointer,
PFN_NUMBER PageFrameNumber,
BOOLEAN Writable)
PFN_NUMBER PageFrameNumber,
BOOLEAN Writable)
{
PtePointer->Pml3.PageFrameNumber = PageFrameNumber;
PtePointer->Pml3.Valid = 1;
@ -234,8 +234,8 @@ MmpSetPml3Pte(PHARDWARE_PTE PtePointer,
XTAPI
VOID
MmpSetPml3PteCaching(PHARDWARE_PTE PtePointer,
BOOLEAN CacheDisable,
BOOLEAN WriteThrough)
BOOLEAN CacheDisable,
BOOLEAN WriteThrough)
{
PtePointer->Pml3.CacheDisable = CacheDisable;
PtePointer->Pml3.WriteThrough = WriteThrough;