Add non-PAE paging support to BlMapPage
This commit is contained in:
parent
0d3fb550f2
commit
1ffddfd0e2
@ -31,7 +31,7 @@ BlBuildPageMap(IN PXTBL_PAGE_MAPPING PageMap,
|
|||||||
EFI_STATUS Status;
|
EFI_STATUS Status;
|
||||||
ULONG Index;
|
ULONG Index;
|
||||||
|
|
||||||
/* Check the page map level to determine which paging structure to create. */
|
/* Check the page map level to determine which paging structure to create */
|
||||||
if(PageMap->PageMapLevel == 3)
|
if(PageMap->PageMapLevel == 3)
|
||||||
{
|
{
|
||||||
/* Allocate a page for the 3-level page map structure (PAE enabled) */
|
/* Allocate a page for the 3-level page map structure (PAE enabled) */
|
||||||
@ -189,55 +189,77 @@ BlMapPage(IN PXTBL_PAGE_MAPPING PageMap,
|
|||||||
IN ULONG_PTR PhysicalAddress,
|
IN ULONG_PTR PhysicalAddress,
|
||||||
IN ULONG NumberOfPages)
|
IN ULONG NumberOfPages)
|
||||||
{
|
{
|
||||||
SIZE_T Pml1Entry, Pml2Entry, Pml3Entry;
|
|
||||||
PHARDWARE_PTE Pml1, Pml2, Pml3;
|
|
||||||
SIZE_T PageFrameNumber;
|
SIZE_T PageFrameNumber;
|
||||||
|
PVOID Pml1, Pml2, Pml3;
|
||||||
|
SIZE_T Pml1Entry, Pml2Entry, Pml3Entry;
|
||||||
|
PHARDWARE_PTE PmlTable;
|
||||||
|
PHARDWARE_LEGACY_PTE LegacyPmlTable;
|
||||||
EFI_STATUS Status;
|
EFI_STATUS Status;
|
||||||
|
|
||||||
/* Set the Page Frame Number (PFN) */
|
/* Set the Page Frame Number (PFN) */
|
||||||
PageFrameNumber = PhysicalAddress >> EFI_PAGE_SHIFT;
|
PageFrameNumber = PhysicalAddress >> EFI_PAGE_SHIFT;
|
||||||
|
|
||||||
/* Do the recursive mapping */
|
/* Map all requested pages */
|
||||||
while(NumberOfPages > 0)
|
while(NumberOfPages > 0)
|
||||||
{
|
{
|
||||||
/* Calculate the indices in the various Page Tables from the virtual address */
|
/* Check the paging mode to use the correct page table structure */
|
||||||
Pml3Entry = (VirtualAddress & ((ULONGLONG)0x1FF << 30)) >> 30;
|
|
||||||
Pml2Entry = (VirtualAddress & ((ULONGLONG)0x1FF << 21)) >> 21;
|
|
||||||
Pml1Entry = (VirtualAddress & ((ULONGLONG)0x1FF << 12)) >> 12;
|
|
||||||
|
|
||||||
/* Check page map level */
|
|
||||||
if(PageMap->PageMapLevel == 3)
|
if(PageMap->PageMapLevel == 3)
|
||||||
{
|
{
|
||||||
/* Three level Page Map */
|
/* Calculate the indices for PAE page tables */
|
||||||
Pml3 = ((PHARDWARE_PTE)(PageMap->PtePointer));
|
Pml3Entry = (VirtualAddress >> 30) & 0x3;
|
||||||
|
Pml2Entry = (VirtualAddress >> 21) & 0x1FF;
|
||||||
|
Pml1Entry = (VirtualAddress >> 12) & 0x1FF;
|
||||||
|
|
||||||
/* Get PML2 */
|
/* Get Page Directory Pointer Table (PML3) */
|
||||||
|
Pml3 = PageMap->PtePointer;
|
||||||
|
|
||||||
|
/* Get Page Directory (PML2) */
|
||||||
Status = BlpGetNextPageTable(PageMap, Pml3, Pml3Entry, &Pml2);
|
Status = BlpGetNextPageTable(PageMap, Pml3, Pml3Entry, &Pml2);
|
||||||
if(Status != STATUS_EFI_SUCCESS)
|
if(Status != STATUS_EFI_SUCCESS)
|
||||||
{
|
{
|
||||||
/* Memory mapping failure */
|
/* Failed to get the Page Table, abort mapping */
|
||||||
return Status;
|
return Status;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
/* Get Page Table (PML1) */
|
||||||
|
Status = BlpGetNextPageTable(PageMap, Pml2, Pml2Entry, &Pml1);
|
||||||
|
if(Status != STATUS_EFI_SUCCESS)
|
||||||
|
{
|
||||||
|
/* Failed to get the Page Table, abort mapping */
|
||||||
|
return Status;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Set the 64-bit PTE entry */
|
||||||
|
PmlTable = (PHARDWARE_PTE)Pml1;
|
||||||
|
RtlZeroMemory(&PmlTable[Pml1Entry], sizeof(HARDWARE_PTE));
|
||||||
|
PmlTable[Pml1Entry].PageFrameNumber = PageFrameNumber;
|
||||||
|
PmlTable[Pml1Entry].Valid = 1;
|
||||||
|
PmlTable[Pml1Entry].Writable = 1;
|
||||||
}
|
}
|
||||||
else
|
else
|
||||||
{
|
{
|
||||||
/* Two level Page Map */
|
/* Calculate the indices for non-PAE page tables */
|
||||||
Pml2 = ((PHARDWARE_PTE)(PageMap->PtePointer));
|
Pml2Entry = (VirtualAddress >> 22) & 0x3FF;
|
||||||
}
|
Pml1Entry = (VirtualAddress >> 12) & 0x3FF;
|
||||||
|
|
||||||
/* Get PML1 */
|
/* Get Page Directory (PML2) */
|
||||||
Status = BlpGetNextPageTable(PageMap, Pml2, Pml2Entry, &Pml1);
|
Pml2 = PageMap->PtePointer;
|
||||||
if(Status != STATUS_EFI_SUCCESS)
|
|
||||||
{
|
|
||||||
/* Memory mapping failure */
|
|
||||||
return Status;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Set paging entry settings */
|
/* Get Page Table (PML1) */
|
||||||
RtlZeroMemory(&Pml1[Pml1Entry], sizeof(HARDWARE_PTE));
|
Status = BlpGetNextPageTable(PageMap, Pml2, Pml2Entry, &Pml1);
|
||||||
Pml1[Pml1Entry].PageFrameNumber = PageFrameNumber;
|
if(Status != STATUS_EFI_SUCCESS)
|
||||||
Pml1[Pml1Entry].Valid = 1;
|
{
|
||||||
Pml1[Pml1Entry].Writable = 1;
|
/* Failed to get the Page Table, abort mapping */
|
||||||
|
return Status;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Set the 32-bit PTE entry */
|
||||||
|
LegacyPmlTable = (PHARDWARE_LEGACY_PTE)Pml1;
|
||||||
|
RtlZeroMemory(&LegacyPmlTable[Pml1Entry], sizeof(HARDWARE_LEGACY_PTE));
|
||||||
|
LegacyPmlTable[Pml1Entry].PageFrameNumber = (UINT32)PageFrameNumber;
|
||||||
|
LegacyPmlTable[Pml1Entry].Valid = 1;
|
||||||
|
LegacyPmlTable[Pml1Entry].Writable = 1;
|
||||||
|
}
|
||||||
|
|
||||||
/* Take next virtual address and PFN */
|
/* Take next virtual address and PFN */
|
||||||
VirtualAddress += EFI_PAGE_SIZE;
|
VirtualAddress += EFI_PAGE_SIZE;
|
||||||
|
Loading…
x
Reference in New Issue
Block a user