Introduce architecture library as new kernel subsystem and move selected routines into new subsystem
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This commit is contained in:
2023-01-28 10:34:55 +01:00
parent 651113c4e8
commit 27e2fdf4f2
19 changed files with 837 additions and 736 deletions

View File

@@ -121,7 +121,7 @@ BlEnablePaging(IN PLIST_ENTRY MemoryMappings,
}
/* Write PML4 to CR3 */
HlWriteControlRegister(3, (UINT_PTR)*PtePointer);
ArWriteControlRegister(3, (UINT_PTR)*PtePointer);
/* Return success */
return STATUS_EFI_SUCCESS;

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@@ -54,7 +54,7 @@ BlEnablePaging(IN PLIST_ENTRY MemoryMappings,
CpuRegisters->Edx = 0;
/* Get CPUID */
HlCpuId(CpuRegisters);
ArCpuId(CpuRegisters);
/* Store PAE status from the CPUID results */
if(!(CpuRegisters->Edx & CPUID_FEATURES_EDX_PAE))
@@ -215,13 +215,13 @@ BlEnablePaging(IN PLIST_ENTRY MemoryMappings,
}
/* Enable Physical Address Extension (PAE) */
HlWriteControlRegister(4, HlReadControlRegister(4) | CR4_PAE);
ArWriteControlRegister(4, ArReadControlRegister(4) | CR4_PAE);
/* Write page mappings to CR3 */
HlWriteControlRegister(3, (UINT_PTR)*PtePointer);
ArWriteControlRegister(3, (UINT_PTR)*PtePointer);
/* Enable paging */
HlWriteControlRegister(0, HlReadControlRegister(0) | CR0_PG);
ArWriteControlRegister(0, ArReadControlRegister(0) | CR0_PG);
/* Return success */
return STATUS_EFI_SUCCESS;

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@@ -197,7 +197,7 @@ XtpInitializeDescriptors(IN PLIST_ENTRY MemoryMappings,
RtlZeroMemory(IdtEntry, EFI_SIZE_TO_PAGES(256 * sizeof(KIDTENTRY)) * EFI_PAGE_SIZE);
/* Stores IDT register into new IDT entry */
HlStoreInterruptDescriptorTable(&OriginalIdt.Limit);
ArStoreInterruptDescriptorTable(&OriginalIdt.Limit);
RtlCopyMemory(IdtEntry, OriginalIdt.Base, OriginalIdt.Limit + 1);
/* Map IDT and set its virtual address */
@@ -239,9 +239,9 @@ XtpLoadProcessorContext(IN PKGDTENTRY Gdt,
IdtDescriptor.Limit = 256 * sizeof(KIDTENTRY) - 1;
/* Load GDT, IDT and TSS */
HlLoadGlobalDescriptorTable(&GdtDescriptor.Limit);
HlLoadInterruptDescriptorTable(&IdtDescriptor.Limit);
HlLoadTaskRegister((UINT32)KGDT_SYS_TSS);
ArLoadGlobalDescriptorTable(&GdtDescriptor.Limit);
ArLoadInterruptDescriptorTable(&IdtDescriptor.Limit);
ArLoadTaskRegister((UINT32)KGDT_SYS_TSS);
/* Re-enable IDE interrupts */
HlIoPortOutByte(0x376, 0);
@@ -280,7 +280,7 @@ XtpSetProcessorContext(IN PLIST_ENTRY MemoryMappings,
XtLdrProtocol->DbgPrint(L"Setting processor context\n");
/* Disable interrupts */
HlClearInterruptFlag();
ArClearInterruptFlag();
/* Initialize GDT */
Status = XtpInitializeDescriptors(MemoryMappings, VirtualAddress, Gdt, Idt);

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@@ -221,7 +221,7 @@ XtpInitializeDescriptors(IN PLIST_ENTRY MemoryMappings,
RtlZeroMemory(IdtEntry, EFI_SIZE_TO_PAGES(256 * sizeof(KIDTENTRY)) * EFI_PAGE_SIZE);
/* Stores IDT register into new IDT entry */
HlStoreInterruptDescriptorTable(&OriginalIdt.Limit);
ArStoreInterruptDescriptorTable(&OriginalIdt.Limit);
RtlCopyMemory(IdtEntry, OriginalIdt.Base, OriginalIdt.Limit + 1);
/* Map IDT and set its virtual address */
@@ -262,12 +262,12 @@ XtpLoadProcessorContext(IN PKGDTENTRY Gdt,
IdtDescriptor.Limit = 256 * sizeof(KIDTENTRY) - 1;
/* Load GDT and TSS */
HlLoadGlobalDescriptorTable(&GdtDescriptor.Limit);
HlLoadInterruptDescriptorTable(&IdtDescriptor.Limit);
HlLoadTaskRegister((UINT32)KGDT_SYS_TSS);
ArLoadGlobalDescriptorTable(&GdtDescriptor.Limit);
ArLoadInterruptDescriptorTable(&IdtDescriptor.Limit);
ArLoadTaskRegister((UINT32)KGDT_SYS_TSS);
/* Load PCR in FS segment */
HlLoadSegment(SEGMENT_FS, KGDT_R0_PCR);
ArLoadSegment(SEGMENT_FS, KGDT_R0_PCR);
/* Re-enable IDE interrupts */
HlIoPortOutByte(0x376, 0);
@@ -306,7 +306,7 @@ XtpSetProcessorContext(IN PLIST_ENTRY MemoryMappings,
XtLdrProtocol->DbgPrint(L"Setting processor context\n");
/* Disable interrupts */
HlClearInterruptFlag();
ArClearInterruptFlag();
/* Initialize GDT */
Status = XtpInitializeDescriptors(MemoryMappings, VirtualAddress, Gdt, Idt);

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@@ -404,8 +404,8 @@ BlStartXtLoader(IN EFI_HANDLE ImageHandle,
BlEfiPrint(L"System halted!");
for(;;)
{
HlClearInterruptFlag();
HlHalt();
ArClearInterruptFlag();
ArHalt();
}
/* Return success */