Introduce architecture library as new kernel subsystem and move selected routines into new subsystem
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@@ -121,7 +121,7 @@ BlEnablePaging(IN PLIST_ENTRY MemoryMappings,
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}
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/* Write PML4 to CR3 */
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HlWriteControlRegister(3, (UINT_PTR)*PtePointer);
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ArWriteControlRegister(3, (UINT_PTR)*PtePointer);
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/* Return success */
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return STATUS_EFI_SUCCESS;
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@@ -54,7 +54,7 @@ BlEnablePaging(IN PLIST_ENTRY MemoryMappings,
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CpuRegisters->Edx = 0;
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/* Get CPUID */
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HlCpuId(CpuRegisters);
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ArCpuId(CpuRegisters);
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/* Store PAE status from the CPUID results */
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if(!(CpuRegisters->Edx & CPUID_FEATURES_EDX_PAE))
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@@ -215,13 +215,13 @@ BlEnablePaging(IN PLIST_ENTRY MemoryMappings,
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}
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/* Enable Physical Address Extension (PAE) */
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HlWriteControlRegister(4, HlReadControlRegister(4) | CR4_PAE);
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ArWriteControlRegister(4, ArReadControlRegister(4) | CR4_PAE);
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/* Write page mappings to CR3 */
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HlWriteControlRegister(3, (UINT_PTR)*PtePointer);
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ArWriteControlRegister(3, (UINT_PTR)*PtePointer);
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/* Enable paging */
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HlWriteControlRegister(0, HlReadControlRegister(0) | CR0_PG);
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ArWriteControlRegister(0, ArReadControlRegister(0) | CR0_PG);
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/* Return success */
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return STATUS_EFI_SUCCESS;
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@@ -197,7 +197,7 @@ XtpInitializeDescriptors(IN PLIST_ENTRY MemoryMappings,
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RtlZeroMemory(IdtEntry, EFI_SIZE_TO_PAGES(256 * sizeof(KIDTENTRY)) * EFI_PAGE_SIZE);
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/* Stores IDT register into new IDT entry */
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HlStoreInterruptDescriptorTable(&OriginalIdt.Limit);
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ArStoreInterruptDescriptorTable(&OriginalIdt.Limit);
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RtlCopyMemory(IdtEntry, OriginalIdt.Base, OriginalIdt.Limit + 1);
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/* Map IDT and set its virtual address */
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@@ -239,9 +239,9 @@ XtpLoadProcessorContext(IN PKGDTENTRY Gdt,
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IdtDescriptor.Limit = 256 * sizeof(KIDTENTRY) - 1;
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/* Load GDT, IDT and TSS */
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HlLoadGlobalDescriptorTable(&GdtDescriptor.Limit);
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HlLoadInterruptDescriptorTable(&IdtDescriptor.Limit);
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HlLoadTaskRegister((UINT32)KGDT_SYS_TSS);
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ArLoadGlobalDescriptorTable(&GdtDescriptor.Limit);
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ArLoadInterruptDescriptorTable(&IdtDescriptor.Limit);
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ArLoadTaskRegister((UINT32)KGDT_SYS_TSS);
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/* Re-enable IDE interrupts */
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HlIoPortOutByte(0x376, 0);
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@@ -280,7 +280,7 @@ XtpSetProcessorContext(IN PLIST_ENTRY MemoryMappings,
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XtLdrProtocol->DbgPrint(L"Setting processor context\n");
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/* Disable interrupts */
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HlClearInterruptFlag();
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ArClearInterruptFlag();
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/* Initialize GDT */
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Status = XtpInitializeDescriptors(MemoryMappings, VirtualAddress, Gdt, Idt);
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@@ -221,7 +221,7 @@ XtpInitializeDescriptors(IN PLIST_ENTRY MemoryMappings,
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RtlZeroMemory(IdtEntry, EFI_SIZE_TO_PAGES(256 * sizeof(KIDTENTRY)) * EFI_PAGE_SIZE);
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/* Stores IDT register into new IDT entry */
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HlStoreInterruptDescriptorTable(&OriginalIdt.Limit);
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ArStoreInterruptDescriptorTable(&OriginalIdt.Limit);
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RtlCopyMemory(IdtEntry, OriginalIdt.Base, OriginalIdt.Limit + 1);
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/* Map IDT and set its virtual address */
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@@ -262,12 +262,12 @@ XtpLoadProcessorContext(IN PKGDTENTRY Gdt,
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IdtDescriptor.Limit = 256 * sizeof(KIDTENTRY) - 1;
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/* Load GDT and TSS */
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HlLoadGlobalDescriptorTable(&GdtDescriptor.Limit);
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HlLoadInterruptDescriptorTable(&IdtDescriptor.Limit);
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HlLoadTaskRegister((UINT32)KGDT_SYS_TSS);
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ArLoadGlobalDescriptorTable(&GdtDescriptor.Limit);
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ArLoadInterruptDescriptorTable(&IdtDescriptor.Limit);
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ArLoadTaskRegister((UINT32)KGDT_SYS_TSS);
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/* Load PCR in FS segment */
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HlLoadSegment(SEGMENT_FS, KGDT_R0_PCR);
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ArLoadSegment(SEGMENT_FS, KGDT_R0_PCR);
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/* Re-enable IDE interrupts */
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HlIoPortOutByte(0x376, 0);
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@@ -306,7 +306,7 @@ XtpSetProcessorContext(IN PLIST_ENTRY MemoryMappings,
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XtLdrProtocol->DbgPrint(L"Setting processor context\n");
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/* Disable interrupts */
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HlClearInterruptFlag();
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ArClearInterruptFlag();
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/* Initialize GDT */
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Status = XtpInitializeDescriptors(MemoryMappings, VirtualAddress, Gdt, Idt);
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@@ -404,8 +404,8 @@ BlStartXtLoader(IN EFI_HANDLE ImageHandle,
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BlEfiPrint(L"System halted!");
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for(;;)
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{
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HlClearInterruptFlag();
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HlHalt();
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ArClearInterruptFlag();
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ArHalt();
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}
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/* Return success */
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