Implement HlCpuId() routine and corresponding structures for issueing CPUID instruction
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@@ -18,6 +18,10 @@
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extern ULONG ComPortAddress[];
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/* HAL library routines forward references */
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XTAPI
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BOOLEAN
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HlCpuId(IN OUT PCPUID_REGISTERS Registers);
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XTAPI
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UCHAR
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HlIoPortInByte(IN USHORT Port);
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@@ -45,18 +49,18 @@ HlReadCR4();
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XTAPI
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VOID
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HlWriteCR0(UINT_PTR Data);
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HlWriteCR0(IN UINT_PTR Data);
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XTAPI
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VOID
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HlWriteCR2(UINT_PTR Data);
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HlWriteCR2(IN UINT_PTR Data);
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XTAPI
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VOID
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HlWriteCR3(UINT_PTR Data);
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HlWriteCR3(IN UINT_PTR Data);
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XTAPI
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VOID
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HlWriteCR4(UINT_PTR Data);
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HlWriteCR4(IN UINT_PTR Data);
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#endif /* __XTDK_I686_HLFUNCS_H */
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100
sdk/xtdk/i686/hltypes.h
Normal file
100
sdk/xtdk/i686/hltypes.h
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@@ -0,0 +1,100 @@
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/**
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* PROJECT: ExectOS
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* COPYRIGHT: See COPYING.md in the top level directory
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* FILE: sdk/xtdk/i686/hltypes.h
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* DESCRIPTION: XT hardware abstraction layer structures definitions specific to i686 architecture
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* DEVELOPERS: Rafal Kupiec <belliash@codingworkshop.eu.org>
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*/
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#ifndef __XTDK_I686_HLTYPES_H
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#define __XTDK_I686_HLTYPES_H
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#include "xtdefs.h"
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#include "xtstruct.h"
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#include "xttypes.h"
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typedef enum _CPUID_FEATURES
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{
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CPUID_FEATURES_ECX_SSE3 = 1 << 0,
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CPUID_FEATURES_ECX_PCLMUL = 1 << 1,
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CPUID_FEATURES_ECX_DTES64 = 1 << 2,
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CPUID_FEATURES_ECX_MONITOR = 1 << 3,
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CPUID_FEATURES_ECX_DS_CPL = 1 << 4,
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CPUID_FEATURES_ECX_VMX = 1 << 5,
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CPUID_FEATURES_ECX_SMX = 1 << 6,
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CPUID_FEATURES_ECX_EST = 1 << 7,
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CPUID_FEATURES_ECX_TM2 = 1 << 8,
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CPUID_FEATURES_ECX_SSSE3 = 1 << 9,
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CPUID_FEATURES_ECX_CID = 1 << 10,
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CPUID_FEATURES_ECX_SDBG = 1 << 11,
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CPUID_FEATURES_ECX_FMA = 1 << 12,
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CPUID_FEATURES_ECX_CX16 = 1 << 13,
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CPUID_FEATURES_ECX_XTPR = 1 << 14,
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CPUID_FEATURES_ECX_PDCM = 1 << 15,
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CPUID_FEATURES_ECX_PCID = 1 << 17,
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CPUID_FEATURES_ECX_DCA = 1 << 18,
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CPUID_FEATURES_ECX_SSE4_1 = 1 << 19,
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CPUID_FEATURES_ECX_SSE4_2 = 1 << 20,
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CPUID_FEATURES_ECX_X2APIC = 1 << 21,
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CPUID_FEATURES_ECX_MOVBE = 1 << 22,
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CPUID_FEATURES_ECX_POPCNT = 1 << 23,
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CPUID_FEATURES_ECX_TSC = 1 << 24,
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CPUID_FEATURES_ECX_AES = 1 << 25,
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CPUID_FEATURES_ECX_XSAVE = 1 << 26,
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CPUID_FEATURES_ECX_OSXSAVE = 1 << 27,
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CPUID_FEATURES_ECX_AVX = 1 << 28,
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CPUID_FEATURES_ECX_F16C = 1 << 29,
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CPUID_FEATURES_ECX_RDRAND = 1 << 30,
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CPUID_FEATURES_ECX_HYPERVISOR = 1 << 31,
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CPUID_FEATURES_EDX_FPU = 1 << 0,
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CPUID_FEATURES_EDX_VME = 1 << 1,
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CPUID_FEATURES_EDX_DE = 1 << 2,
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CPUID_FEATURES_EDX_PSE = 1 << 3,
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CPUID_FEATURES_EDX_TSC = 1 << 4,
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CPUID_FEATURES_EDX_MSR = 1 << 5,
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CPUID_FEATURES_EDX_PAE = 1 << 6,
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CPUID_FEATURES_EDX_MCE = 1 << 7,
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CPUID_FEATURES_EDX_CX8 = 1 << 8,
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CPUID_FEATURES_EDX_APIC = 1 << 9,
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CPUID_FEATURES_EDX_SEP = 1 << 11,
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CPUID_FEATURES_EDX_MTRR = 1 << 12,
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CPUID_FEATURES_EDX_PGE = 1 << 13,
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CPUID_FEATURES_EDX_MCA = 1 << 14,
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CPUID_FEATURES_EDX_CMOV = 1 << 15,
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CPUID_FEATURES_EDX_PAT = 1 << 16,
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CPUID_FEATURES_EDX_PSE36 = 1 << 17,
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CPUID_FEATURES_EDX_PSN = 1 << 18,
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CPUID_FEATURES_EDX_CLFLUSH = 1 << 19,
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CPUID_FEATURES_EDX_DS = 1 << 21,
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CPUID_FEATURES_EDX_ACPI = 1 << 22,
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CPUID_FEATURES_EDX_MMX = 1 << 23,
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CPUID_FEATURES_EDX_FXSR = 1 << 24,
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CPUID_FEATURES_EDX_SSE = 1 << 25,
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CPUID_FEATURES_EDX_SSE2 = 1 << 26,
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CPUID_FEATURES_EDX_SS = 1 << 27,
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CPUID_FEATURES_EDX_HTT = 1 << 28,
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CPUID_FEATURES_EDX_TM = 1 << 29,
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CPUID_FEATURES_EDX_IA64 = 1 << 30,
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CPUID_FEATURES_EDX_PBE = 1 << 31
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} CPUID_FEATURES, *PCPUID_FEATURES;
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typedef enum _CPUID_REQUESTS
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{
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CPUID_GET_VENDOR_STRING,
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CPUID_GET_CPU_FEATURES,
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CPUID_GET_TLB,
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CPUID_GET_SERIAL
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} CPUID_REQUESTS, *PCPUID_REQUESTS;
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typedef struct _CPUID_REGISTERS
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{
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UINT32 Leaf;
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UINT32 SubLeaf;
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UINT32 Eax;
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UINT32 Ebx;
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UINT32 Ecx;
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UINT32 Edx;
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} CPUID_REGISTERS, *PCPUID_REGISTERS;
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#endif /* __XTDK_I686_HLTYPES_H */
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@@ -11,5 +11,8 @@
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/* Architecture-related structures forward references */
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typedef struct _CPUID_REGISTERS CPUID_REGISTERS, *PCPUID_REGISTERS;
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typedef struct _HARDWARE_PTE HARDWARE_PTE, *PHARDWARE_PTE;
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typedef struct _HARDWARE_PTE_PAE HARDWARE_PTE_PAE, *PHARDWARE_PTE_PAE;
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#endif /* __XTDK_I686_XTSTRUCT_H */
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