xt-sys/exectos
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Merge branch 'master' into master

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This commit is contained in:
Jozef Nagy
2023-11-28 15:38:53 +01:00
committed by Jozef Nagy
parent 56a73132f8 d17b06a180
commit 656c6b7d59
15 changed files with 461 additions and 15 deletions
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6
sdk/cmake/qemu.cmake
View File

@@ -8,14 +8,14 @@ endif()
# This target creates a disk image
add_custom_target(diskimg
DEPENDS install
COMMAND sh -c "dd if=/dev/zero of=${EXECTOS_BINARY_DIR}/output/disk.img bs=512 count=${PROJECT_DISK_IMAGE_BLOCKS} 2> /dev/null 1> /dev/null"
COMMAND sh -c "dd if=/dev/zero of=${EXECTOS_BINARY_DIR}/output/disk.img bs=512 count=${PROJECT_DISK_IMAGE_BLOCKS} 2>/dev/null 1>/dev/null"
COMMAND parted ${EXECTOS_BINARY_DIR}/output/disk.img -s -a minimal mklabel gpt
COMMAND parted ${EXECTOS_BINARY_DIR}/output/disk.img -s -a minimal mkpart EFI FAT32 2048s ${PROJECT_PART_IMAGE_BLOCKS}s
COMMAND parted ${EXECTOS_BINARY_DIR}/output/disk.img -s -a minimal toggle 1 boot
COMMAND sh -c "dd if=/dev/zero of=${EXECTOS_BINARY_DIR}/output/part.img bs=512 count=${PROJECT_PART_IMAGE_BLOCKS} 2> /dev/null 1> /dev/null"
COMMAND sh -c "dd if=/dev/zero of=${EXECTOS_BINARY_DIR}/output/part.img bs=512 count=${PROJECT_PART_IMAGE_BLOCKS} 2>/dev/null 1>/dev/null"
COMMAND mformat -i ${EXECTOS_BINARY_DIR}/output/part.img -h32 -t32 -n64 -L32
COMMAND sh -c "mcopy -s -i ${EXECTOS_BINARY_DIR}/output/part.img ${EXECTOS_BINARY_DIR}/output/binaries/* ::"
COMMAND sh -c "dd if=${EXECTOS_BINARY_DIR}/output/part.img of=${EXECTOS_BINARY_DIR}/output/disk.img bs=512 count=${PROJECT_PART_IMAGE_BLOCKS} seek=2048 conv=notrunc 2> /dev/null 1> /dev/null"
COMMAND sh -c "dd if=${EXECTOS_BINARY_DIR}/output/part.img of=${EXECTOS_BINARY_DIR}/output/disk.img bs=512 count=${PROJECT_PART_IMAGE_BLOCKS} seek=2048 conv=notrunc 2>/dev/null 1>/dev/null"
COMMAND rm ${EXECTOS_BINARY_DIR}/output/part.img
VERBATIM)

2
sdk/cmake/version.cmake
View File

@@ -17,7 +17,7 @@ string(TIMESTAMP XTOS_VERSION_FULLDATE "%d/%m/%Y %H:%M UTC" UTC)
# Set latest GIT revision
set(XTOS_VERSION_HASH "unknown")
if(EXISTS "${EXECTOS_SOURCE_DIR}/.git")
execute_process(COMMAND git describe --abbrev=7 --long --always
execute_process(COMMAND git describe --abbrev=10 --long --always
WORKING_DIRECTORY ${EXECTOS_SOURCE_DIR}
OUTPUT_VARIABLE XTOS_VERSION_HASH
OUTPUT_STRIP_TRAILING_WHITESPACE)

81
sdk/xtdk/amd64/hltypes.h
View File

@@ -15,8 +15,10 @@
#include ARCH_HEADER(xtstruct.h)
/* APIC base address */
/* APIC base addresses */
#define APIC_BASE 0xFFFFFFFFFFFE0000
#define APIC_LAPIC_MSR_BASE 0x0000001B
#define APIC_X2APIC_MSR_BASE 0x00000800
/* APIC vector definitions */
#define APIC_VECTOR_ZERO 0x00
@@ -36,7 +38,84 @@
#define APIC_VECTOR_PERF 0xFE
#define APIC_VECTOR_NMI 0xFF
/* APIC destination formats */
#define APIC_DF_FLAT 0xFFFFFFFF
#define APIC_DF_CLUSTER 0x0FFFFFFF
/* APIC delivery modes */
#define APIC_DM_FIXED 0
#define APIC_DM_LOWPRIO 1
#define APIC_DM_SMI 2
#define APIC_DM_REMOTE 3
#define APIC_DM_NMI 4
#define APIC_DM_INIT 5
#define APIC_DM_STARTUP 6
#define APIC_DM_EXTINT 7
/* APIC trigger modes */
#define APIC_TGM_EDGE 0
#define APIC_TGM_LEVEL 1
/* 8259/ISP PIC ports definitions */
#define PIC1_CONTROL_PORT 0x20
#define PIC1_DATA_PORT 0x21
#define PIC1_ELCR_PORT 0x04D0
#define PIC2_CONTROL_PORT 0xA0
#define PIC2_DATA_PORT 0xA1
#define PIC2_ELCR_PORT 0x04D1
/* PIC vector definitions */
#define PIC1_VECTOR_SPURIOUS 0x37
/* Serial port I/O addresses */
#define COMPORT_ADDRESSES {0x000, 0x3F8, 0x2F8, 0x3E8, 0x2E8, 0x5F8, 0x4F8, 0x5E8, 0x4E8}
/* APIC Base Register */
typedef union _APIC_BASE_REGISTER
{
ULONGLONG LongLong;
struct
{
ULONGLONG Reserved1:8;
ULONGLONG BootStrapProcessor:1;
ULONGLONG Reserved2:1;
ULONGLONG ExtendedMode:1;
ULONGLONG Enable:1;
ULONGLONG BaseAddress:40;
ULONGLONG Reserved3:12;
};
} APIC_BASE_REGISTER, *PAPIC_BASE_REGISTER;
/* APIC Local Vector Table (LVT) Register */
typedef union _APIC_LVT_REGISTER
{
ULONG Long;
struct
{
ULONG Vector:8;
ULONG MessageType:3;
ULONG Reserved1:1;
ULONG DeliveryStatus:1;
ULONG Reserved2:1;
ULONG RemoteIRR:1;
ULONG TriggerMode:1;
ULONG Mask:1;
ULONG TimerMode:1;
ULONG Reserved3:13;
};
} APIC_LVT_REGISTER, *PAPIC_LVT_REGISTER;
/* APIC Spurious Register */
typedef union _APIC_SPURIOUS_REGISTER
{
ULONG Long;
struct
{
ULONG Vector:8;
ULONG SoftwareEnable:1;
ULONG CoreChecking:1;
ULONG Reserved:22;
};
} APIC_SPURIOUS_REGISTER, *PAPIC_SPURIOUS_REGISTER;
#endif /* __XTDK_AMD64_HLTYPES_H */

11
sdk/xtdk/hltypes.h
View File

@@ -120,14 +120,14 @@ typedef enum _APIC_REGISTER
APIC_EOI = 0x0B, /* EOI Register */
APIC_RRR = 0x0C, /* Remote Read Register */
APIC_LDR = 0x0D, /* Logical Destination Register */
APIC_DFR = 0x0E, /* Destination Format Register */
APIC_DFR = 0x0E, /* Destination Format Register (not available in extended mode) */
APIC_SIVR = 0x0F, /* Spurious Interrupt Vector Register */
APIC_ISR = 0x10, /* Interrupt Service Register*/
APIC_TMR = 0x18, /* Trigger Mode Register */
APIC_IRR = 0x20, /* Interrupt Request Register */
APIC_ESR = 0x28, /* Error Status Register */
APIC_ICR0 = 0x30, /* Interrupt Command Register */
APIC_ICR1 = 0x31, /* Interrupt Command Register */
APIC_ICR1 = 0x31, /* Interrupt Command Register (not available in extended mode) */
APIC_TMRLVTR = 0x32, /* Timer Local Vector Table */
APIC_THRMLVTR = 0x33, /* Thermal Local Vector Table */
APIC_PCLVTR = 0x34, /* Performance Counter Local Vector Table */
@@ -146,6 +146,13 @@ typedef enum _APIC_REGISTER
APIC_EXT3LVTR = 0x53 /* Extended Interrupt 3 Local Vector Table */
} APIC_REGISTER, *PAPIC_REGISTER;
/* APIC mode list */
typedef enum _HAL_APIC_MODE
{
APIC_MODE_COMPAT,
APIC_MODE_X2APIC
} HAL_APIC_MODE, *PHAL_APIC_MODE;
/* Serial (COM) port initial state */
typedef struct _CPPORT
{

81
sdk/xtdk/i686/hltypes.h
View File

@@ -15,8 +15,10 @@
#include ARCH_HEADER(xtstruct.h)
/* APIC base address */
/* APIC base addresses */
#define APIC_BASE 0xFFFE0000
#define APIC_LAPIC_MSR_BASE 0x0000001B
#define APIC_X2APIC_MSR_BASE 0x00000800
/* APIC vector definitions */
#define APIC_VECTOR_ZERO 0x00
@@ -41,7 +43,84 @@
#define APIC_VECTOR_PERF 0xFE
#define APIC_VECTOR_NMI 0xFF
/* APIC destination formats */
#define APIC_DF_FLAT 0xFFFFFFFF
#define APIC_DF_CLUSTER 0x0FFFFFFF
/* APIC delivery modes */
#define APIC_DM_FIXED 0
#define APIC_DM_LOWPRIO 1
#define APIC_DM_SMI 2
#define APIC_DM_REMOTE 3
#define APIC_DM_NMI 4
#define APIC_DM_INIT 5
#define APIC_DM_STARTUP 6
#define APIC_DM_EXTINT 7
/* APIC trigger modes */
#define APIC_TGM_EDGE 0
#define APIC_TGM_LEVEL 1
/* 8259/ISP PIC ports definitions */
#define PIC1_CONTROL_PORT 0x20
#define PIC1_DATA_PORT 0x21
#define PIC1_ELCR_PORT 0x04D0
#define PIC2_CONTROL_PORT 0xA0
#define PIC2_DATA_PORT 0xA1
#define PIC2_ELCR_PORT 0x04D1
/* PIC vector definitions */
#define PIC1_VECTOR_SPURIOUS 0x37
/* Serial port I/O addresses */
#define COMPORT_ADDRESSES {0x000, 0x3F8, 0x2F8, 0x3E8, 0x2E8, 0x5F8, 0x4F8, 0x5E8, 0x4E8}
/* APIC Base Register */
typedef union _APIC_BASE_REGISTER
{
ULONGLONG LongLong;
struct
{
ULONGLONG Reserved1:8;
ULONGLONG BootStrapProcessor:1;
ULONGLONG Reserved2:1;
ULONGLONG ExtendedMode:1;
ULONGLONG Enable:1;
ULONGLONG BaseAddress:40;
ULONGLONG Reserved3:12;
};
} APIC_BASE_REGISTER, *PAPIC_BASE_REGISTER;
/* APIC Local Vector Table (LVT) Register */
typedef union _APIC_LVT_REGISTER
{
ULONG Long;
struct
{
ULONG Vector:8;
ULONG MessageType:3;
ULONG Reserved1:1;
ULONG DeliveryStatus:1;
ULONG Reserved2:1;
ULONG RemoteIRR:1;
ULONG TriggerMode:1;
ULONG Mask:1;
ULONG TimerMode:1;
ULONG Reserved3:13;
};
} APIC_LVT_REGISTER, *PAPIC_LVT_REGISTER;
/* APIC Spurious Register */
typedef union _APIC_SPURIOUS_REGISTER
{
ULONG Long;
struct
{
ULONG Vector:8;
ULONG SoftwareEnable:1;
ULONG CoreChecking:1;
ULONG Reserved:22;
};
} APIC_SPURIOUS_REGISTER, *PAPIC_SPURIOUS_REGISTER;
#endif /* __XTDK_I686_HLTYPES_H */