Merge branch 'master' into master

xtoskrnl/CMakeLists.txt

@@ -31,6 +31,7 @@ list(APPEND XTOSKRNL_SOURCE
     ${XTOSKRNL_SOURCE_DIR}/ke/semphore.c
     ${XTOSKRNL_SOURCE_DIR}/ke/spinlock.c
     ${XTOSKRNL_SOURCE_DIR}/ke/timer.c
+    ${XTOSKRNL_SOURCE_DIR}/ke/${ARCH}/irqs.c
     ${XTOSKRNL_SOURCE_DIR}/ke/${ARCH}/krnlinit.c
     ${XTOSKRNL_SOURCE_DIR}/ke/${ARCH}/kthread.c
     ${XTOSKRNL_SOURCE_DIR}/ke/${ARCH}/proc.c

xtoskrnl/ar/amd64/procsup.c

@@ -539,8 +539,8 @@ ArpSetIdtGate(IN PKIDTENTRY Idt,
               IN USHORT Access)
 {
     /* Setup the gate */
-    Idt[Vector].OffsetLow = (ULONG_PTR)Handler;
-    Idt[Vector].OffsetMiddle = ((ULONG_PTR)Handler >> 16);
+    Idt[Vector].OffsetLow = ((ULONG_PTR)Handler & 0xFFFF);
+    Idt[Vector].OffsetMiddle = (((ULONG_PTR)Handler >> 16) & 0xFFFF);
     Idt[Vector].OffsetHigh = (ULONG_PTR)Handler >> 32;
     Idt[Vector].Dpl = Access;
     Idt[Vector].IstIndex = Ist;

xtoskrnl/hl/globals.c

@@ -9,5 +9,8 @@
 #include <xtos.h>
 
 
+/* APIC mode */
+HAL_APIC_MODE HlpApicMode;
+
 /* FrameBuffer information */
 HAL_FRAMEBUFFER_DATA HlpFrameBufferData;

xtoskrnl/hl/pic.c

@@ -124,7 +124,7 @@ HlWritePic(IN UCHAR Register, IN UCHAR Value)
 }
 
 /**
- * Reads from the local APIC register.
+ * Reads from the APIC register.
  *
  * @param Register
  *        Supplies the APIC register to read from.
@@ -137,11 +137,20 @@ XTFASTCALL
 ULONG
 HlReadApicRegister(IN APIC_REGISTER Register)
 {
-    return RtlReadRegisterLong((PULONG)APIC_BASE + (Register << 4));
+    if(HlpApicMode == APIC_MODE_X2APIC)
+    {
+        /* Read from x2APIC MSR */
+        return ArReadModelSpecificRegister((ULONG)(APIC_X2APIC_MSR_BASE + Register));
+    }
+    else
+    {
+        /* Read from xAPIC */
+        return RtlReadRegisterLong((PULONG)(APIC_BASE + (Register << 4)));
+    }
 }
 
 /**
- * Writes to the local APIC register.
+ * Writes to the APIC register.
  *
  * @param Register
  *        Supplies the APIC register to write to.
@@ -158,5 +167,172 @@ VOID
 HlWriteApicRegister(IN APIC_REGISTER Register,
                     IN ULONG Value)
 {
-    RtlWriteRegisterLong((PULONG)APIC_BASE + (Register << 4), Value);
+    if(HlpApicMode == APIC_MODE_X2APIC)
+    {
+        /* Write to x2APIC MSR */
+        ArWriteModelSpecificRegister((ULONG)(APIC_X2APIC_MSR_BASE + Register), Value);
+    }
+    else
+    {
+        /* Write to xAPIC */
+        RtlWriteRegisterLong((PULONG)(APIC_BASE + (Register << 4)), Value);
+    }
+}
+
+/**
+ * Checks whether the x2APIC extension is supported by the processor.
+ *
+ * @return This routine returns TRUE if x2APIC is supported, or FALSE otherwise.
+ *
+ * @since XT 1.0
+ *
+ * @todo Check if bits 0 and 1 of DMAR ACPI table flags are set after implementing ACPI support.
+ *       Intel VT-d spec says x2apic should not be enabled if they are.
+ */
+XTAPI
+BOOLEAN
+HlpCheckX2ApicSupport(VOID)
+{
+    CPUID_REGISTERS CpuRegisters;
+
+    /* Prepare CPUID registers */
+    CpuRegisters.Leaf = CPUID_GET_CPU_FEATURES;
+    CpuRegisters.SubLeaf = 0;
+    CpuRegisters.Eax = 0;
+    CpuRegisters.Ebx = 0;
+    CpuRegisters.Ecx = 0;
+    CpuRegisters.Edx = 0;
+
+    /* Get CPUID */
+    ArCpuId(&CpuRegisters);
+
+    /* Check x2APIC status from the CPUID results */
+    if(!(CpuRegisters.Ecx & CPUID_FEATURES_ECX_X2APIC))
+    {
+        /* x2APIC is not supported */
+        return FALSE;
+    }
+
+    /* x2APIC is supported */
+    return TRUE;
+}
+
+/**
+ * Allows an APIC spurious interrupts to end up.
+ *
+ * @return This routine does not return any value.
+ *
+ * @since XT 1.0
+ */
+XTCDECL
+VOID
+HlpHandleApicSpuriousService()
+{
+}
+
+/**
+ * Allows a PIC spurious interrupts to end up.
+ *
+ * @return This routine does not return any value.
+ *
+ * @since XT 1.0
+ */
+XTCDECL
+VOID
+HlpHandlePicSpuriousService()
+{
+}
+
+/**
+ * Initializes the APIC interrupt controller.
+ *
+ * @return This routine does not return any value.
+ *
+ * @since XT 1.0
+ *
+ * @todo Register interrupt handlers for spurious vectors.
+ */
+XTAPI
+VOID
+HlpInitializeApic()
+{
+    APIC_BASE_REGISTER BaseRegister;
+    APIC_LVT_REGISTER LvtRegister;
+    APIC_SPURIOUS_REGISTER SpuriousRegister;
+    ULONG CpuNumber = 0;
+
+    /* Check if this is an x2APIC compatible machine */
+    if(HlpCheckX2ApicSupport())
+    {
+        /* Enable x2APIC */
+        HlpApicMode = APIC_MODE_X2APIC;
+    }
+    else
+    {
+        /* Use xAPIC compatibility mode */
+        HlpApicMode = APIC_MODE_COMPAT;
+    }
+
+    /* Enable the APIC */
+    BaseRegister.LongLong = ArReadModelSpecificRegister(APIC_LAPIC_MSR_BASE);
+    BaseRegister.Enable = 1;
+    BaseRegister.ExtendedMode = (HlpApicMode == APIC_MODE_X2APIC);
+    BaseRegister.BootStrapProcessor = 1;
+    ArWriteModelSpecificRegister(APIC_LAPIC_MSR_BASE, BaseRegister.LongLong);
+
+    /* xAPIC compatibility mode specific initialization */
+    if(HlpApicMode == APIC_MODE_COMPAT)
+    {
+        /* Initialize Destination Format Register with flat model */
+        HlWriteApicRegister(APIC_DFR, APIC_DF_FLAT);
+
+        /* Set the logical APIC ID */
+        HlWriteApicRegister(APIC_LDR, (1UL << CpuNumber) << 24);
+    }
+
+    /* Set the spurious interrupt vector */
+    SpuriousRegister.Long = HlReadApicRegister(APIC_SIVR);
+    SpuriousRegister.Vector = APIC_VECTOR_SPURIOUS;
+    SpuriousRegister.SoftwareEnable = 1;
+    SpuriousRegister.CoreChecking = 0;
+    HlWriteApicRegister(APIC_SIVR, SpuriousRegister.Long);
+
+    /* Initialize Logical Vector Table */
+    LvtRegister.Long = 0;
+    LvtRegister.Vector = APIC_VECTOR_NMI;
+    LvtRegister.MessageType = APIC_DM_FIXED;
+    LvtRegister.DeliveryStatus = 0;
+    LvtRegister.RemoteIRR = 0;
+    LvtRegister.TriggerMode = APIC_TGM_EDGE;
+    LvtRegister.Mask = 0;
+    LvtRegister.TimerMode = 0;
+
+    /* Mask LVT tables */
+    HlWriteApicRegister(APIC_TMRLVTR, LvtRegister.Long);
+    HlWriteApicRegister(APIC_THRMLVTR, LvtRegister.Long);
+    HlWriteApicRegister(APIC_PCLVTR, LvtRegister.Long);
+
+    /* Mask LINT0 */
+    LvtRegister.Vector = APIC_VECTOR_SPURIOUS;
+    LvtRegister.MessageType = APIC_DM_EXTINT;
+    HlWriteApicRegister(APIC_LINT0, LvtRegister.Long);
+
+    /* Mask LINT1 */
+    LvtRegister.Mask = 0;
+    LvtRegister.Vector = APIC_VECTOR_NMI;
+    LvtRegister.MessageType = APIC_DM_NMI;
+    LvtRegister.TriggerMode = APIC_TGM_LEVEL;
+    HlWriteApicRegister(APIC_LINT1, LvtRegister.Long);
+
+    /* Mask LVTR_ERROR */
+    LvtRegister.Vector = APIC_VECTOR_ERROR;
+    LvtRegister.MessageType = APIC_DM_FIXED;
+    HlWriteApicRegister(APIC_ERRLVTR, LvtRegister.Long);
+
+    /* Clear errors after enabling vectors */
+    HlWriteApicRegister(APIC_ESR, 0);
+
+    /* Register interrupt handlers once the APIC initialization is done */
+    KeSetInterruptHandler(APIC_VECTOR_SPURIOUS, HlpHandleApicSpuriousService);
+    KeSetInterruptHandler(PIC1_VECTOR_SPURIOUS, HlpHandlePicSpuriousService);
 }

xtoskrnl/includes/globals.h

@@ -12,6 +12,9 @@
 #include <xtos.h>
 
 
+/* APIC mode */
+EXTERN HAL_APIC_MODE HlpApicMode;
+
 /* FrameBuffer information */
 EXTERN HAL_FRAMEBUFFER_DATA HlpFrameBufferData;
 

xtoskrnl/includes/hl.h

@@ -89,6 +89,22 @@ VOID
 HlWriteApicRegister(IN APIC_REGISTER Register,
                     IN ULONG Value);
 
+XTAPI
+BOOLEAN
+HlpCheckX2ApicSupport(VOID);
+
+XTCDECL
+VOID
+HlpHandleApicSpuriousService();
+
+XTCDECL
+VOID
+HlpHandlePicSpuriousService();
+
+XTAPI
+VOID
+HlpInitializeApic();
+
 XTFASTCALL
 KRUNLEVEL
 HlpTransformApicTprToRunLevel(IN UCHAR Tpr);

xtoskrnl/includes/ke.h

@@ -77,6 +77,11 @@ KeSetEvent(IN PKEVENT Event,
            IN KPRIORITY Increment,
            IN BOOLEAN Wait);
 
+XTAPI
+VOID
+KeSetInterruptHandler(IN ULONG Vector,
+                      IN PVOID Handler);
+
 XTAPI
 VOID
 KeStartThread(IN PKTHREAD Thread);

xtoskrnl/ke/amd64/irqs.c

@@ -0,0 +1,39 @@
+/**
+ * PROJECT:         ExectOS
+ * COPYRIGHT:       See COPYING.md in the top level directory
+ * FILE:            xtoskrnl/ke/amd64/irqs.c
+ * DESCRIPTION:     Kernel interrupts support for amd64 architecture
+ * DEVELOPERS:      Rafal Kupiec <belliash@codingworkshop.eu.org>
+ */
+
+#include <xtos.h>
+
+
+/**
+ * Sets new interrupt handler for the existing IDT entry.
+ *
+ * @param HalVector
+ *        Supplies the HAL vector number.
+ *
+ * @param Handler
+ *        Supplies the new interrupt handler.
+ *
+ * @return This routine does not return any value.
+ *
+ * @since XT 1.0
+ */
+XTAPI
+VOID
+KeSetInterruptHandler(IN ULONG Vector,
+                      IN PVOID Handler)
+{
+    PKPROCESSOR_BLOCK ProcessorBlock;
+
+    /* Get current processor block */
+    ProcessorBlock = KeGetCurrentProcessorBlock();
+
+    /* Update interrupt handler */
+    ProcessorBlock->IdtBase[(UCHAR) Vector].OffsetLow = ((ULONG_PTR)Handler & 0xFFFF);
+    ProcessorBlock->IdtBase[(UCHAR) Vector].OffsetMiddle = (((ULONG_PTR)Handler >> 16) & 0xFFFF);
+    ProcessorBlock->IdtBase[(UCHAR) Vector].OffsetHigh = (ULONG_PTR)Handler >> 32;
+}

xtoskrnl/ke/i686/irqs.c

@@ -0,0 +1,38 @@
+/**
+ * PROJECT:         ExectOS
+ * COPYRIGHT:       See COPYING.md in the top level directory
+ * FILE:            xtoskrnl/ke/i686/irqs.c
+ * DESCRIPTION:     Kernel interrupts support for i686 architecture
+ * DEVELOPERS:      Rafal Kupiec <belliash@codingworkshop.eu.org>
+ */
+
+#include <xtos.h>
+
+
+/**
+ * Sets new interrupt handler for the existing IDT entry.
+ *
+ * @param HalVector
+ *        Supplies the HAL vector number.
+ *
+ * @param Handler
+ *        Supplies the new interrupt handler.
+ *
+ * @return This routine does not return any value.
+ *
+ * @since XT 1.0
+ */
+XTAPI
+VOID
+KeSetInterruptHandler(IN ULONG Vector,
+                      IN PVOID Handler)
+{
+    PKPROCESSOR_BLOCK ProcessorBlock;
+
+    /* Get current processor block */
+    ProcessorBlock = KeGetCurrentProcessorBlock();
+
+    /* Update interrupt handler */
+    ProcessorBlock->IdtBase[(UCHAR) Vector].Offset = (USHORT)((ULONG)Handler & 0xFFFF);
+    ProcessorBlock->IdtBase[(UCHAR) Vector].ExtendedOffset = (USHORT)((ULONG)Handler >> 16);
+}

xtoskrnl/ke/i686/kthread.c

@@ -43,7 +43,7 @@ KepInitializeThreadContext(IN PKTHREAD Thread,
     PFX_SAVE_FORMAT FxSaveFormat;
 
     /* Set initial thread frame */
-    ThreadFrame = ((PKTHREAD_INIT_FRAME)Thread->InitialStack) - sizeof(KTHREAD_INIT_FRAME);
+    ThreadFrame = (PKTHREAD_INIT_FRAME)(Thread->InitialStack - sizeof(KTHREAD_INIT_FRAME));
 
     /* Fill floating point save area with zeroes */
     RtlZeroMemory(&ThreadFrame->NpxFrame, sizeof(FX_SAVE_AREA));