xt-sys/exectos
xt-sys/exectos
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Merge branch 'master' into master

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Jozef Nagy 2023-11-28 15:38:53 +01:00 committed by Jozef Nagy
commit 656c6b7d59
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15 changed files with 461 additions and 15 deletions
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6
sdk/cmake/qemu.cmake
View File

@ -8,14 +8,14 @@ endif()
# This target creates a disk image
add_custom_target(diskimg
DEPENDS install
COMMAND sh -c "dd if=/dev/zero of=${EXECTOS_BINARY_DIR}/output/disk.img bs=512 count=${PROJECT_DISK_IMAGE_BLOCKS} 2> /dev/null 1> /dev/null"
COMMAND sh -c "dd if=/dev/zero of=${EXECTOS_BINARY_DIR}/output/disk.img bs=512 count=${PROJECT_DISK_IMAGE_BLOCKS} 2>/dev/null 1>/dev/null"
COMMAND parted ${EXECTOS_BINARY_DIR}/output/disk.img -s -a minimal mklabel gpt
COMMAND parted ${EXECTOS_BINARY_DIR}/output/disk.img -s -a minimal mkpart EFI FAT32 2048s ${PROJECT_PART_IMAGE_BLOCKS}s
COMMAND parted ${EXECTOS_BINARY_DIR}/output/disk.img -s -a minimal toggle 1 boot
COMMAND sh -c "dd if=/dev/zero of=${EXECTOS_BINARY_DIR}/output/part.img bs=512 count=${PROJECT_PART_IMAGE_BLOCKS} 2> /dev/null 1> /dev/null"
COMMAND sh -c "dd if=/dev/zero of=${EXECTOS_BINARY_DIR}/output/part.img bs=512 count=${PROJECT_PART_IMAGE_BLOCKS} 2>/dev/null 1>/dev/null"
COMMAND mformat -i ${EXECTOS_BINARY_DIR}/output/part.img -h32 -t32 -n64 -L32
COMMAND sh -c "mcopy -s -i ${EXECTOS_BINARY_DIR}/output/part.img ${EXECTOS_BINARY_DIR}/output/binaries/* ::"
COMMAND sh -c "dd if=${EXECTOS_BINARY_DIR}/output/part.img of=${EXECTOS_BINARY_DIR}/output/disk.img bs=512 count=${PROJECT_PART_IMAGE_BLOCKS} seek=2048 conv=notrunc 2> /dev/null 1> /dev/null"
COMMAND sh -c "dd if=${EXECTOS_BINARY_DIR}/output/part.img of=${EXECTOS_BINARY_DIR}/output/disk.img bs=512 count=${PROJECT_PART_IMAGE_BLOCKS} seek=2048 conv=notrunc 2>/dev/null 1>/dev/null"
COMMAND rm ${EXECTOS_BINARY_DIR}/output/part.img
VERBATIM)

2
sdk/cmake/version.cmake
View File

@ -17,7 +17,7 @@ string(TIMESTAMP XTOS_VERSION_FULLDATE "%d/%m/%Y %H:%M UTC" UTC)
# Set latest GIT revision
set(XTOS_VERSION_HASH "unknown")
if(EXISTS "${EXECTOS_SOURCE_DIR}/.git")
execute_process(COMMAND git describe --abbrev=7 --long --always
execute_process(COMMAND git describe --abbrev=10 --long --always
WORKING_DIRECTORY ${EXECTOS_SOURCE_DIR}
OUTPUT_VARIABLE XTOS_VERSION_HASH
OUTPUT_STRIP_TRAILING_WHITESPACE)

81
sdk/xtdk/amd64/hltypes.h
View File

@ -15,8 +15,10 @@
#include ARCH_HEADER(xtstruct.h)
/* APIC base address */
/* APIC base addresses */
#define APIC_BASE 0xFFFFFFFFFFFE0000
#define APIC_LAPIC_MSR_BASE 0x0000001B
#define APIC_X2APIC_MSR_BASE 0x00000800
/* APIC vector definitions */
#define APIC_VECTOR_ZERO 0x00
@ -36,7 +38,84 @@
#define APIC_VECTOR_PERF 0xFE
#define APIC_VECTOR_NMI 0xFF
/* APIC destination formats */
#define APIC_DF_FLAT 0xFFFFFFFF
#define APIC_DF_CLUSTER 0x0FFFFFFF
/* APIC delivery modes */
#define APIC_DM_FIXED 0
#define APIC_DM_LOWPRIO 1
#define APIC_DM_SMI 2
#define APIC_DM_REMOTE 3
#define APIC_DM_NMI 4
#define APIC_DM_INIT 5
#define APIC_DM_STARTUP 6
#define APIC_DM_EXTINT 7
/* APIC trigger modes */
#define APIC_TGM_EDGE 0
#define APIC_TGM_LEVEL 1
/* 8259/ISP PIC ports definitions */
#define PIC1_CONTROL_PORT 0x20
#define PIC1_DATA_PORT 0x21
#define PIC1_ELCR_PORT 0x04D0
#define PIC2_CONTROL_PORT 0xA0
#define PIC2_DATA_PORT 0xA1
#define PIC2_ELCR_PORT 0x04D1
/* PIC vector definitions */
#define PIC1_VECTOR_SPURIOUS 0x37
/* Serial port I/O addresses */
#define COMPORT_ADDRESSES {0x000, 0x3F8, 0x2F8, 0x3E8, 0x2E8, 0x5F8, 0x4F8, 0x5E8, 0x4E8}
/* APIC Base Register */
typedef union _APIC_BASE_REGISTER
{
ULONGLONG LongLong;
struct
{
ULONGLONG Reserved1:8;
ULONGLONG BootStrapProcessor:1;
ULONGLONG Reserved2:1;
ULONGLONG ExtendedMode:1;
ULONGLONG Enable:1;
ULONGLONG BaseAddress:40;
ULONGLONG Reserved3:12;
};
} APIC_BASE_REGISTER, *PAPIC_BASE_REGISTER;
/* APIC Local Vector Table (LVT) Register */
typedef union _APIC_LVT_REGISTER
{
ULONG Long;
struct
{
ULONG Vector:8;
ULONG MessageType:3;
ULONG Reserved1:1;
ULONG DeliveryStatus:1;
ULONG Reserved2:1;
ULONG RemoteIRR:1;
ULONG TriggerMode:1;
ULONG Mask:1;
ULONG TimerMode:1;
ULONG Reserved3:13;
};
} APIC_LVT_REGISTER, *PAPIC_LVT_REGISTER;
/* APIC Spurious Register */
typedef union _APIC_SPURIOUS_REGISTER
{
ULONG Long;
struct
{
ULONG Vector:8;
ULONG SoftwareEnable:1;
ULONG CoreChecking:1;
ULONG Reserved:22;
};
} APIC_SPURIOUS_REGISTER, *PAPIC_SPURIOUS_REGISTER;
#endif /* __XTDK_AMD64_HLTYPES_H */

11
sdk/xtdk/hltypes.h
View File

@ -120,14 +120,14 @@ typedef enum _APIC_REGISTER
APIC_EOI = 0x0B, /* EOI Register */
APIC_RRR = 0x0C, /* Remote Read Register */
APIC_LDR = 0x0D, /* Logical Destination Register */
APIC_DFR = 0x0E, /* Destination Format Register */
APIC_DFR = 0x0E, /* Destination Format Register (not available in extended mode) */
APIC_SIVR = 0x0F, /* Spurious Interrupt Vector Register */
APIC_ISR = 0x10, /* Interrupt Service Register*/
APIC_TMR = 0x18, /* Trigger Mode Register */
APIC_IRR = 0x20, /* Interrupt Request Register */
APIC_ESR = 0x28, /* Error Status Register */
APIC_ICR0 = 0x30, /* Interrupt Command Register */
APIC_ICR1 = 0x31, /* Interrupt Command Register */
APIC_ICR1 = 0x31, /* Interrupt Command Register (not available in extended mode) */
APIC_TMRLVTR = 0x32, /* Timer Local Vector Table */
APIC_THRMLVTR = 0x33, /* Thermal Local Vector Table */
APIC_PCLVTR = 0x34, /* Performance Counter Local Vector Table */
@ -146,6 +146,13 @@ typedef enum _APIC_REGISTER
APIC_EXT3LVTR = 0x53 /* Extended Interrupt 3 Local Vector Table */
} APIC_REGISTER, *PAPIC_REGISTER;
/* APIC mode list */
typedef enum _HAL_APIC_MODE
{
APIC_MODE_COMPAT,
APIC_MODE_X2APIC
} HAL_APIC_MODE, *PHAL_APIC_MODE;
/* Serial (COM) port initial state */
typedef struct _CPPORT
{

81
sdk/xtdk/i686/hltypes.h
View File

@ -15,8 +15,10 @@
#include ARCH_HEADER(xtstruct.h)
/* APIC base address */
/* APIC base addresses */
#define APIC_BASE 0xFFFE0000
#define APIC_LAPIC_MSR_BASE 0x0000001B
#define APIC_X2APIC_MSR_BASE 0x00000800
/* APIC vector definitions */
#define APIC_VECTOR_ZERO 0x00
@ -41,7 +43,84 @@
#define APIC_VECTOR_PERF 0xFE
#define APIC_VECTOR_NMI 0xFF
/* APIC destination formats */
#define APIC_DF_FLAT 0xFFFFFFFF
#define APIC_DF_CLUSTER 0x0FFFFFFF
/* APIC delivery modes */
#define APIC_DM_FIXED 0
#define APIC_DM_LOWPRIO 1
#define APIC_DM_SMI 2
#define APIC_DM_REMOTE 3
#define APIC_DM_NMI 4
#define APIC_DM_INIT 5
#define APIC_DM_STARTUP 6
#define APIC_DM_EXTINT 7
/* APIC trigger modes */
#define APIC_TGM_EDGE 0
#define APIC_TGM_LEVEL 1
/* 8259/ISP PIC ports definitions */
#define PIC1_CONTROL_PORT 0x20
#define PIC1_DATA_PORT 0x21
#define PIC1_ELCR_PORT 0x04D0
#define PIC2_CONTROL_PORT 0xA0
#define PIC2_DATA_PORT 0xA1
#define PIC2_ELCR_PORT 0x04D1
/* PIC vector definitions */
#define PIC1_VECTOR_SPURIOUS 0x37
/* Serial port I/O addresses */
#define COMPORT_ADDRESSES {0x000, 0x3F8, 0x2F8, 0x3E8, 0x2E8, 0x5F8, 0x4F8, 0x5E8, 0x4E8}
/* APIC Base Register */
typedef union _APIC_BASE_REGISTER
{
ULONGLONG LongLong;
struct
{
ULONGLONG Reserved1:8;
ULONGLONG BootStrapProcessor:1;
ULONGLONG Reserved2:1;
ULONGLONG ExtendedMode:1;
ULONGLONG Enable:1;
ULONGLONG BaseAddress:40;
ULONGLONG Reserved3:12;
};
} APIC_BASE_REGISTER, *PAPIC_BASE_REGISTER;
/* APIC Local Vector Table (LVT) Register */
typedef union _APIC_LVT_REGISTER
{
ULONG Long;
struct
{
ULONG Vector:8;
ULONG MessageType:3;
ULONG Reserved1:1;
ULONG DeliveryStatus:1;
ULONG Reserved2:1;
ULONG RemoteIRR:1;
ULONG TriggerMode:1;
ULONG Mask:1;
ULONG TimerMode:1;
ULONG Reserved3:13;
};
} APIC_LVT_REGISTER, *PAPIC_LVT_REGISTER;
/* APIC Spurious Register */
typedef union _APIC_SPURIOUS_REGISTER
{
ULONG Long;
struct
{
ULONG Vector:8;
ULONG SoftwareEnable:1;
ULONG CoreChecking:1;
ULONG Reserved:22;
};
} APIC_SPURIOUS_REGISTER, *PAPIC_SPURIOUS_REGISTER;
#endif /* __XTDK_I686_HLTYPES_H */

1
xtoskrnl/CMakeLists.txt
View File

@ -31,6 +31,7 @@ list(APPEND XTOSKRNL_SOURCE
${XTOSKRNL_SOURCE_DIR}/ke/semphore.c
${XTOSKRNL_SOURCE_DIR}/ke/spinlock.c
${XTOSKRNL_SOURCE_DIR}/ke/timer.c
${XTOSKRNL_SOURCE_DIR}/ke/${ARCH}/irqs.c
${XTOSKRNL_SOURCE_DIR}/ke/${ARCH}/krnlinit.c
${XTOSKRNL_SOURCE_DIR}/ke/${ARCH}/kthread.c
${XTOSKRNL_SOURCE_DIR}/ke/${ARCH}/proc.c

4
xtoskrnl/ar/amd64/procsup.c
View File

@ -539,8 +539,8 @@ ArpSetIdtGate(IN PKIDTENTRY Idt,
IN USHORT Access)
{
/* Setup the gate */
Idt[Vector].OffsetLow = (ULONG_PTR)Handler;
Idt[Vector].OffsetMiddle = ((ULONG_PTR)Handler >> 16);
Idt[Vector].OffsetLow = ((ULONG_PTR)Handler & 0xFFFF);
Idt[Vector].OffsetMiddle = (((ULONG_PTR)Handler >> 16) & 0xFFFF);
Idt[Vector].OffsetHigh = (ULONG_PTR)Handler >> 32;
Idt[Vector].Dpl = Access;
Idt[Vector].IstIndex = Ist;

3
xtoskrnl/hl/globals.c
View File

@ -9,5 +9,8 @@
#include <xtos.h>
/* APIC mode */
HAL_APIC_MODE HlpApicMode;
/* FrameBuffer information */
HAL_FRAMEBUFFER_DATA HlpFrameBufferData;

184
xtoskrnl/hl/pic.c
View File

@ -124,7 +124,7 @@ HlWritePic(IN UCHAR Register, IN UCHAR Value)
}
/**
* Reads from the local APIC register.
* Reads from the APIC register.
*
* @param Register
* Supplies the APIC register to read from.
@ -137,11 +137,20 @@ XTFASTCALL
ULONG
HlReadApicRegister(IN APIC_REGISTER Register)
{
return RtlReadRegisterLong((PULONG)APIC_BASE + (Register << 4));
if(HlpApicMode == APIC_MODE_X2APIC)
{
/* Read from x2APIC MSR */
return ArReadModelSpecificRegister((ULONG)(APIC_X2APIC_MSR_BASE + Register));
}
else
{
/* Read from xAPIC */
return RtlReadRegisterLong((PULONG)(APIC_BASE + (Register << 4)));
}
}
/**
* Writes to the local APIC register.
* Writes to the APIC register.
*
* @param Register
* Supplies the APIC register to write to.
@ -158,5 +167,172 @@ VOID
HlWriteApicRegister(IN APIC_REGISTER Register,
IN ULONG Value)
{
RtlWriteRegisterLong((PULONG)APIC_BASE + (Register << 4), Value);
if(HlpApicMode == APIC_MODE_X2APIC)
{
/* Write to x2APIC MSR */
ArWriteModelSpecificRegister((ULONG)(APIC_X2APIC_MSR_BASE + Register), Value);
}
else
{
/* Write to xAPIC */
RtlWriteRegisterLong((PULONG)(APIC_BASE + (Register << 4)), Value);
}
}
/**
* Checks whether the x2APIC extension is supported by the processor.
*
* @return This routine returns TRUE if x2APIC is supported, or FALSE otherwise.
*
* @since XT 1.0
*
* @todo Check if bits 0 and 1 of DMAR ACPI table flags are set after implementing ACPI support.
* Intel VT-d spec says x2apic should not be enabled if they are.
*/
XTAPI
BOOLEAN
HlpCheckX2ApicSupport(VOID)
{
CPUID_REGISTERS CpuRegisters;
/* Prepare CPUID registers */
CpuRegisters.Leaf = CPUID_GET_CPU_FEATURES;
CpuRegisters.SubLeaf = 0;
CpuRegisters.Eax = 0;
CpuRegisters.Ebx = 0;
CpuRegisters.Ecx = 0;
CpuRegisters.Edx = 0;
/* Get CPUID */
ArCpuId(&CpuRegisters);
/* Check x2APIC status from the CPUID results */
if(!(CpuRegisters.Ecx & CPUID_FEATURES_ECX_X2APIC))
{
/* x2APIC is not supported */
return FALSE;
}
/* x2APIC is supported */
return TRUE;
}
/**
* Allows an APIC spurious interrupts to end up.
*
* @return This routine does not return any value.
*
* @since XT 1.0
*/
XTCDECL
VOID
HlpHandleApicSpuriousService()
{
}
/**
* Allows a PIC spurious interrupts to end up.
*
* @return This routine does not return any value.
*
* @since XT 1.0
*/
XTCDECL
VOID
HlpHandlePicSpuriousService()
{
}
/**
* Initializes the APIC interrupt controller.
*
* @return This routine does not return any value.
*
* @since XT 1.0
*
* @todo Register interrupt handlers for spurious vectors.
*/
XTAPI
VOID
HlpInitializeApic()
{
APIC_BASE_REGISTER BaseRegister;
APIC_LVT_REGISTER LvtRegister;
APIC_SPURIOUS_REGISTER SpuriousRegister;
ULONG CpuNumber = 0;
/* Check if this is an x2APIC compatible machine */
if(HlpCheckX2ApicSupport())
{
/* Enable x2APIC */
HlpApicMode = APIC_MODE_X2APIC;
}
else
{
/* Use xAPIC compatibility mode */
HlpApicMode = APIC_MODE_COMPAT;
}
/* Enable the APIC */
BaseRegister.LongLong = ArReadModelSpecificRegister(APIC_LAPIC_MSR_BASE);
BaseRegister.Enable = 1;
BaseRegister.ExtendedMode = (HlpApicMode == APIC_MODE_X2APIC);
BaseRegister.BootStrapProcessor = 1;
ArWriteModelSpecificRegister(APIC_LAPIC_MSR_BASE, BaseRegister.LongLong);
/* xAPIC compatibility mode specific initialization */
if(HlpApicMode == APIC_MODE_COMPAT)
{
/* Initialize Destination Format Register with flat model */
HlWriteApicRegister(APIC_DFR, APIC_DF_FLAT);
/* Set the logical APIC ID */
HlWriteApicRegister(APIC_LDR, (1UL << CpuNumber) << 24);
}
/* Set the spurious interrupt vector */
SpuriousRegister.Long = HlReadApicRegister(APIC_SIVR);
SpuriousRegister.Vector = APIC_VECTOR_SPURIOUS;
SpuriousRegister.SoftwareEnable = 1;
SpuriousRegister.CoreChecking = 0;
HlWriteApicRegister(APIC_SIVR, SpuriousRegister.Long);
/* Initialize Logical Vector Table */
LvtRegister.Long = 0;
LvtRegister.Vector = APIC_VECTOR_NMI;
LvtRegister.MessageType = APIC_DM_FIXED;
LvtRegister.DeliveryStatus = 0;
LvtRegister.RemoteIRR = 0;
LvtRegister.TriggerMode = APIC_TGM_EDGE;
LvtRegister.Mask = 0;
LvtRegister.TimerMode = 0;
/* Mask LVT tables */
HlWriteApicRegister(APIC_TMRLVTR, LvtRegister.Long);
HlWriteApicRegister(APIC_THRMLVTR, LvtRegister.Long);
HlWriteApicRegister(APIC_PCLVTR, LvtRegister.Long);
/* Mask LINT0 */
LvtRegister.Vector = APIC_VECTOR_SPURIOUS;
LvtRegister.MessageType = APIC_DM_EXTINT;
HlWriteApicRegister(APIC_LINT0, LvtRegister.Long);
/* Mask LINT1 */
LvtRegister.Mask = 0;
LvtRegister.Vector = APIC_VECTOR_NMI;
LvtRegister.MessageType = APIC_DM_NMI;
LvtRegister.TriggerMode = APIC_TGM_LEVEL;
HlWriteApicRegister(APIC_LINT1, LvtRegister.Long);
/* Mask LVTR_ERROR */
LvtRegister.Vector = APIC_VECTOR_ERROR;
LvtRegister.MessageType = APIC_DM_FIXED;
HlWriteApicRegister(APIC_ERRLVTR, LvtRegister.Long);
/* Clear errors after enabling vectors */
HlWriteApicRegister(APIC_ESR, 0);
/* Register interrupt handlers once the APIC initialization is done */
KeSetInterruptHandler(APIC_VECTOR_SPURIOUS, HlpHandleApicSpuriousService);
KeSetInterruptHandler(PIC1_VECTOR_SPURIOUS, HlpHandlePicSpuriousService);
}

3
xtoskrnl/includes/globals.h
View File

@ -12,6 +12,9 @@
#include <xtos.h>
/* APIC mode */
EXTERN HAL_APIC_MODE HlpApicMode;
/* FrameBuffer information */
EXTERN HAL_FRAMEBUFFER_DATA HlpFrameBufferData;

16
xtoskrnl/includes/hl.h
View File

@ -89,6 +89,22 @@ VOID
HlWriteApicRegister(IN APIC_REGISTER Register,
IN ULONG Value);
XTAPI
BOOLEAN
HlpCheckX2ApicSupport(VOID);
XTCDECL
VOID
HlpHandleApicSpuriousService();
XTCDECL
VOID
HlpHandlePicSpuriousService();
XTAPI
VOID
HlpInitializeApic();
XTFASTCALL
KRUNLEVEL
HlpTransformApicTprToRunLevel(IN UCHAR Tpr);

5
xtoskrnl/includes/ke.h
View File

@ -77,6 +77,11 @@ KeSetEvent(IN PKEVENT Event,
IN KPRIORITY Increment,
IN BOOLEAN Wait);
XTAPI
VOID
KeSetInterruptHandler(IN ULONG Vector,
IN PVOID Handler);
XTAPI
VOID
KeStartThread(IN PKTHREAD Thread);

39
xtoskrnl/ke/amd64/irqs.c Normal file
View File

@ -0,0 +1,39 @@
/**
* PROJECT: ExectOS
* COPYRIGHT: See COPYING.md in the top level directory
* FILE: xtoskrnl/ke/amd64/irqs.c
* DESCRIPTION: Kernel interrupts support for amd64 architecture
* DEVELOPERS: Rafal Kupiec <belliash@codingworkshop.eu.org>
*/
#include <xtos.h>
/**
* Sets new interrupt handler for the existing IDT entry.
*
* @param HalVector
* Supplies the HAL vector number.
*
* @param Handler
* Supplies the new interrupt handler.
*
* @return This routine does not return any value.
*
* @since XT 1.0
*/
XTAPI
VOID
KeSetInterruptHandler(IN ULONG Vector,
IN PVOID Handler)
{
PKPROCESSOR_BLOCK ProcessorBlock;
/* Get current processor block */
ProcessorBlock = KeGetCurrentProcessorBlock();
/* Update interrupt handler */
ProcessorBlock->IdtBase[(UCHAR) Vector].OffsetLow = ((ULONG_PTR)Handler & 0xFFFF);
ProcessorBlock->IdtBase[(UCHAR) Vector].OffsetMiddle = (((ULONG_PTR)Handler >> 16) & 0xFFFF);
ProcessorBlock->IdtBase[(UCHAR) Vector].OffsetHigh = (ULONG_PTR)Handler >> 32;
}

38
xtoskrnl/ke/i686/irqs.c Normal file
View File

@ -0,0 +1,38 @@
/**
* PROJECT: ExectOS
* COPYRIGHT: See COPYING.md in the top level directory
* FILE: xtoskrnl/ke/i686/irqs.c
* DESCRIPTION: Kernel interrupts support for i686 architecture
* DEVELOPERS: Rafal Kupiec <belliash@codingworkshop.eu.org>
*/
#include <xtos.h>
/**
* Sets new interrupt handler for the existing IDT entry.
*
* @param HalVector
* Supplies the HAL vector number.
*
* @param Handler
* Supplies the new interrupt handler.
*
* @return This routine does not return any value.
*
* @since XT 1.0
*/
XTAPI
VOID
KeSetInterruptHandler(IN ULONG Vector,
IN PVOID Handler)
{
PKPROCESSOR_BLOCK ProcessorBlock;
/* Get current processor block */
ProcessorBlock = KeGetCurrentProcessorBlock();
/* Update interrupt handler */
ProcessorBlock->IdtBase[(UCHAR) Vector].Offset = (USHORT)((ULONG)Handler & 0xFFFF);
ProcessorBlock->IdtBase[(UCHAR) Vector].ExtendedOffset = (USHORT)((ULONG)Handler >> 16);
}

2
xtoskrnl/ke/i686/kthread.c
View File

@ -43,7 +43,7 @@ KepInitializeThreadContext(IN PKTHREAD Thread,
PFX_SAVE_FORMAT FxSaveFormat;
/* Set initial thread frame */
ThreadFrame = ((PKTHREAD_INIT_FRAME)Thread->InitialStack) - sizeof(KTHREAD_INIT_FRAME);
ThreadFrame = (PKTHREAD_INIT_FRAME)(Thread->InitialStack - sizeof(KTHREAD_INIT_FRAME));
/* Fill floating point save area with zeroes */
RtlZeroMemory(&ThreadFrame->NpxFrame, sizeof(FX_SAVE_AREA));