xt-sys/exectos
xt-sys/exectos
3
5
Fork 3
Code Issues 3 Pull Requests 1 Actions Projects 1 Releases Wiki Activity

Merge branch 'master' into prcb-cpu-features

Browse Source
This commit is contained in:
Pedro Valadés 2023-11-26 18:53:01 +01:00
commit 73c768ba0e
No known key found for this signature in database
GPG Key ID: 25780ED196EFD8F5
21 changed files with 402 additions and 23 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
sdk/cmake/version.cmake
View File

@ -17,7 +17,7 @@ string(TIMESTAMP XTOS_VERSION_FULLDATE "%d/%m/%Y %H:%M UTC" UTC)
# Set latest GIT revision
set(XTOS_VERSION_HASH "unknown")
if(EXISTS "${EXECTOS_SOURCE_DIR}/.git")
execute_process(COMMAND git describe --abbrev=7 --long --always
execute_process(COMMAND git describe --abbrev=10 --long --always
WORKING_DIRECTORY ${EXECTOS_SOURCE_DIR}
OUTPUT_VARIABLE XTOS_VERSION_HASH
OUTPUT_STRIP_TRAILING_WHITESPACE)

21
sdk/xtdk/amd64/hltypes.h
View File

@ -12,10 +12,29 @@
#include <xtdefs.h>
#include <xtstruct.h>
#include <xttypes.h>
#include ARCH_HEADER(xtstruct.h)
/* APIC base address */
#define APIC_BASE 0xFFFFFFFFFFFE0000ULL
#define APIC_BASE 0xFFFFFFFFFFFE0000
/* APIC vector definitions */
#define APIC_VECTOR_ZERO 0x00
#define APIC_VECTOR_APC 0x1F
#define APIC_VECTOR_DPC 0x2F
#define APIC_VECTOR_CMCI 0x35
#define APIC_VECTOR_SPURIOUS 0x3F
#define APIC_VECTOR_REBOOT 0x50
#define APIC_VECTOR_GENERIC 0xC1
#define APIC_VECTOR_SYNC 0xD1
#define APIC_VECTOR_CLOCK 0xD1
#define APIC_VECTOR_CLOCK_IPI 0xD2
#define APIC_VECTOR_IPI 0xE1
#define APIC_VECTOR_ERROR 0xE3
#define APIC_VECTOR_POWERFAIL 0xEF
#define APIC_VECTOR_PROFILE 0xFD
#define APIC_VECTOR_PERF 0xFE
#define APIC_VECTOR_NMI 0xFF
/* Serial port I/O addresses */
#define COMPORT_ADDRESSES {0x000, 0x3F8, 0x2F8, 0x3E8, 0x2E8, 0x5F8, 0x4F8, 0x5E8, 0x4E8}

14
sdk/xtdk/amd64/ketypes.h
View File

@ -106,6 +106,14 @@
#define APC_LEVEL 1
#define DISPATCH_LEVEL 2
#define CMC_LEVEL 5
#define DEVICE1_LEVEL 6
#define DEVICE2_LEVEL 7
#define DEVICE3_LEVEL 8
#define DEVICE4_LEVEL 9
#define DEVICE5_LEVEL 10
#define DEVICE6_LEVEL 11
#define DEVICE7_LEVEL 12
#define SYNC_LEVEL 12
#define CLOCK_LEVEL 13
#define IPI_LEVEL 14
#define DRS_LEVEL 14
@ -361,7 +369,7 @@ typedef struct _KSWITCH_FRAME
ULONG64 P4Home;
ULONG64 P5Home;
ULONG MxCsr;
KIRQL ApcBypass;
KRUNLEVEL ApcBypass;
UCHAR Reserved[3];
ULONG64 Rbp;
ULONG64 Return;
@ -376,7 +384,7 @@ typedef struct _KTRAP_FRAME
ULONG64 P4Home;
ULONG64 P5;
KPROCESSOR_MODE PreviousMode;
KIRQL PreviousIrql;
KRUNLEVEL PreviousRunLevel;
UCHAR FaultIndicator;
UCHAR ExceptionActive;
ULONG MxCsr;
@ -540,7 +548,7 @@ typedef struct _KPROCESSOR_BLOCK
};
};
PKIDTENTRY IdtBase;
KIRQL Irql;
KRUNLEVEL RunLevel;
KPROCESSOR_CONTROL_BLOCK Prcb;
ULONG ContextSwitches;
} KPROCESSOR_BLOCK, *PKPROCESSOR_BLOCK;

24
sdk/xtdk/i686/hltypes.h
View File

@ -12,11 +12,35 @@
#include <xtdefs.h>
#include <xtstruct.h>
#include <xttypes.h>
#include ARCH_HEADER(xtstruct.h)
/* APIC base address */
#define APIC_BASE 0xFFFE0000
/* APIC vector definitions */
#define APIC_VECTOR_ZERO 0x00
#define APIC_VECTOR_SPURIOUS 0x1F
#define APIC_VECTOR_APC 0x3D
#define APIC_VECTOR_DPC 0x41
#define APIC_VECTOR_REBOOT 0x50
#define APIC_VECTOR_DEVICE1 0x51
#define APIC_VECTOR_DEVICE2 0x61
#define APIC_VECTOR_DEVICE3 0x71
#define APIC_VECTOR_DEVICE4 0x81
#define APIC_VECTOR_DEVICE5 0x91
#define APIC_VECTOR_DEVICE6 0xA1
#define APIC_VECTOR_DEVICE7 0xB1
#define APIC_VECTOR_GENERIC 0xC1
#define APIC_VECTOR_SYNC 0xC1
#define APIC_VECTOR_CLOCK 0xD1
#define APIC_VECTOR_IPI 0xE1
#define APIC_VECTOR_ERROR 0xE3
#define APIC_VECTOR_POWERFAIL 0xEF
#define APIC_VECTOR_PROFILE 0xFD
#define APIC_VECTOR_PERF 0xFE
#define APIC_VECTOR_NMI 0xFF
/* Serial port I/O addresses */
#define COMPORT_ADDRESSES {0x000, 0x3F8, 0x2F8, 0x3E8, 0x2E8, 0x5F8, 0x4F8, 0x5E8, 0x4E8}

9
sdk/xtdk/i686/ketypes.h
View File

@ -135,6 +135,13 @@
#define APC_LEVEL 1
#define DISPATCH_LEVEL 2
#define CMCI_LEVEL 5
#define DEVICE1_LEVEL 6
#define DEVICE2_LEVEL 7
#define DEVICE3_LEVEL 8
#define DEVICE4_LEVEL 9
#define DEVICE5_LEVEL 10
#define DEVICE6_LEVEL 11
#define DEVICE7_LEVEL 12
#define PROFILE_LEVEL 27
#define SYNC_LEVEL 27
#define CLOCK_LEVEL 28
@ -471,7 +478,7 @@ typedef struct _KPROCESSOR_BLOCK
THREAD_INFORMATION_BLOCK ThreadInformationBlock;
PKPROCESSOR_BLOCK Self;
PKPROCESSOR_CONTROL_BLOCK CurrentPrcb;
KIRQL Irql;
KRUNLEVEL RunLevel;
PKIDTENTRY IdtBase;
PKGDTENTRY GdtBase;
PKTSS TssBase;

4
sdk/xtdk/ketypes.h
View File

@ -280,7 +280,7 @@ typedef struct _KSPIN_LOCK_QUEUE
typedef struct _KLOCK_QUEUE_HANDLE
{
KSPIN_LOCK_QUEUE LockQueue;
KIRQL OldIrql;
KRUNLEVEL OldRunLevel;
} KLOCK_QUEUE_HANDLE, *PKLOCK_QUEUE_HANDLE;
/* Queue object structure definition */
@ -431,7 +431,7 @@ typedef struct _KTHREAD
};
KWAIT_BLOCK WaitBlock[KTHREAD_WAIT_BLOCK + 1];
UCHAR NpxState;
KIRQL WaitIrql;
KRUNLEVEL WaitRunLevel;
LIST_ENTRY QueueListEntry;
PKTRAP_FRAME TrapFrame;
PVOID CallbackStack;

6
sdk/xtdk/xtbase.h
View File

@ -17,15 +17,15 @@
/* Kernel affinity */
typedef ULONG_PTR KAFFINITY, *PKAFFINITY;
/* Interrupt Request Level (IRQL) */
typedef UCHAR KIRQL, *PKIRQL;
/* Kernel priority */
typedef LONG KPRIORITY, *PKPRIORITY;
/* Processor modes */
typedef CHAR KPROCESSOR_MODE, *PKPROCESSOR_MODE;
/* Interrupt Request Run Level (IRQL) */
typedef UCHAR KRUNLEVEL, *PKRUNLEVEL;
/* Spin locks synchronization mechanism */
typedef ULONG_PTR KSPIN_LOCK, *PKSPIN_LOCK;

4
xtoskrnl/CMakeLists.txt
View File

@ -13,11 +13,12 @@ list(APPEND XTOSKRNL_SOURCE
${XTOSKRNL_SOURCE_DIR}/ar/${ARCH}/procsup.c
${XTOSKRNL_SOURCE_DIR}/ar/${ARCH}/traps.c
${XTOSKRNL_SOURCE_DIR}/ex/rundown.c
${XTOSKRNL_SOURCE_DIR}/hl/apic.c
${XTOSKRNL_SOURCE_DIR}/hl/cport.c
${XTOSKRNL_SOURCE_DIR}/hl/efifb.c
${XTOSKRNL_SOURCE_DIR}/hl/globals.c
${XTOSKRNL_SOURCE_DIR}/hl/pic.c
${XTOSKRNL_SOURCE_DIR}/hl/${ARCH}/ioport.c
${XTOSKRNL_SOURCE_DIR}/hl/${ARCH}/runlevel.c
${XTOSKRNL_SOURCE_DIR}/ke/apc.c
${XTOSKRNL_SOURCE_DIR}/ke/dpc.c
${XTOSKRNL_SOURCE_DIR}/ke/event.c
@ -26,6 +27,7 @@ list(APPEND XTOSKRNL_SOURCE
${XTOSKRNL_SOURCE_DIR}/ke/krnlinit.c
${XTOSKRNL_SOURCE_DIR}/ke/kthread.c
${XTOSKRNL_SOURCE_DIR}/ke/panic.c
${XTOSKRNL_SOURCE_DIR}/ke/runlevel.c
${XTOSKRNL_SOURCE_DIR}/ke/semphore.c
${XTOSKRNL_SOURCE_DIR}/ke/spinlock.c
${XTOSKRNL_SOURCE_DIR}/ke/timer.c

1
xtoskrnl/ar/amd64/cpufunc.c
View File

@ -324,6 +324,7 @@ ArReadControlRegister(IN USHORT ControlRegister)
: "=r" (Value)
:
: "memory");
break;
default:
/* Invalid control register set */
Value = 0;

2
xtoskrnl/ar/amd64/procsup.c
View File

@ -56,7 +56,7 @@ ArInitializeProcessor(VOID)
ArLoadTaskRegister((UINT)KGDT_SYS_TSS);
/* Enter passive IRQ level */
ProcessorBlock->Irql = PASSIVE_LEVEL;
ProcessorBlock->RunLevel = PASSIVE_LEVEL;
ArWriteControlRegister(8, PASSIVE_LEVEL);
/* Initialize segment registers */

2
xtoskrnl/ar/i686/procsup.c
View File

@ -56,7 +56,7 @@ ArInitializeProcessor(VOID)
ArLoadTaskRegister((UINT)KGDT_SYS_TSS);
/* Enter passive IRQ level */
ProcessorBlock->Irql = PASSIVE_LEVEL;
ProcessorBlock->RunLevel = PASSIVE_LEVEL;
/* Initialize segment registers */
ArpInitializeSegments();

75
xtoskrnl/hl/amd64/runlevel.c Normal file
View File

@ -0,0 +1,75 @@
/**
* PROJECT: ExectOS
* COPYRIGHT: See COPYING.md in the top level directory
* FILE: xtoskrnl/hl/amd64/runlevel.c
* DESCRIPTION: Run Level management support for AMD64 architecture
* DEVELOPERS: Rafal Kupiec <belliash@codingworkshop.eu.org>
*/
#include <xtos.h>
/**
* Gets the current run level from APIC for the current processor.
*
* @return This routine returns the current run level.
*
* @since XT 1.0
*/
XTFASTCALL
KRUNLEVEL
HlGetRunLevel(VOID)
{
return (KRUNLEVEL)ArReadControlRegister(8);
}
/**
* Sets new run level for the current processor.
*
* @param RunLevel
* Supplies the new run level to store into APIC.
*
* @return This routine does not return any value.
*
* @since XT 1.0
*/
XTFASTCALL
VOID
HlSetRunLevel(IN KRUNLEVEL RunLevel)
{
ArWriteControlRegister(8, RunLevel);
}
/**
* Maps APIC interrupt vector to XT run level.
*
* @param Tpr
* Supplies the interrupt vector rad from APIC Task Priority Register.
*
* @return This routine returns the XT run level corresponding to the specified APIC interrupt vector.
*
* @since XT 1.0
*/
XTFASTCALL
KRUNLEVEL
HlpTransformApicTprToRunLevel(IN UCHAR Tpr)
{
return (KRUNLEVEL)(Tpr >> 4);
}
/**
* Maps XT run level to interrupt vector suitable for the APIC Task Priority Register.
*
* @param RunLevel
* Supplies the XT run level.
*
* @return This routine returns the APIC interrupt vector corresponding to the specified XT run level.
*
* @since XT 1.0
*/
XTFASTCALL
UCHAR
HlpTransformRunLevelToApicTpr(IN KRUNLEVEL RunLevel)
{
return (RunLevel << 4);
}

133
xtoskrnl/hl/i686/runlevel.c Normal file
View File

@ -0,0 +1,133 @@
/**
* PROJECT: ExectOS
* COPYRIGHT: See COPYING.md in the top level directory
* FILE: xtoskrnl/hl/i686/runlevel.c
* DESCRIPTION: Run Level management support for i686 architecture
* DEVELOPERS: Rafal Kupiec <belliash@codingworkshop.eu.org>
*/
#include <xtos.h>
/**
* Gets the current run level from APIC for the current processor.
*
* @return This routine returns the current run level.
*
* @since XT 1.0
*/
XTFASTCALL
KRUNLEVEL
HlGetRunLevel(VOID)
{
return HlpTransformApicTprToRunLevel(HlReadApicRegister(APIC_TPR));
}
/**
* Sets new run level for the current processor.
*
* @param RunLevel
* Supplies the new run level to store into APIC.
*
* @return This routine does not return any value.
*
* @since XT 1.0
*/
XTFASTCALL
VOID
HlSetRunLevel(IN KRUNLEVEL RunLevel)
{
HlWriteApicRegister(APIC_TPR, HlpTransformRunLevelToApicTpr(RunLevel));
}
/**
* Maps APIC interrupt vector to XT run level.
*
* @param Tpr
* Supplies the interrupt vector rad from APIC Task Priority Register.
*
* @return This routine returns the XT run level corresponding to the specified APIC interrupt vector.
*
* @since XT 1.0
*/
XTFASTCALL
KRUNLEVEL
HlpTransformApicTprToRunLevel(IN UCHAR Tpr)
{
STATIC KRUNLEVEL TransformationTable[16] =
{
PASSIVE_LEVEL,
PASSIVE_LEVEL,
PASSIVE_LEVEL,
APC_LEVEL,
DISPATCH_LEVEL,
DEVICE1_LEVEL,
DEVICE2_LEVEL,
DEVICE3_LEVEL,
DEVICE4_LEVEL,
DEVICE5_LEVEL,
DEVICE6_LEVEL,
DEVICE7_LEVEL,
PROFILE_LEVEL,
CLOCK_LEVEL,
IPI_LEVEL,
HIGH_LEVEL
};
/* Return the run level corresponding to the TPR from the transformation table. */
return TransformationTable[Tpr / 16];
}
/**
* Maps XT run level to interrupt vector suitable for the APIC Task Priority Register.
*
* @param RunLevel
* Supplies the XT run level.
*
* @return This routine returns the APIC interrupt vector corresponding to the specified XT run level.
*
* @since XT 1.0
*/
XTFASTCALL
UCHAR
HlpTransformRunLevelToApicTpr(IN KRUNLEVEL RunLevel)
{
STATIC UCHAR TransformationTable[32] =
{
APIC_VECTOR_ZERO,
APIC_VECTOR_APC,
APIC_VECTOR_DPC,
APIC_VECTOR_DPC,
APIC_VECTOR_DEVICE1,
APIC_VECTOR_DEVICE2,
APIC_VECTOR_DEVICE3,
APIC_VECTOR_DEVICE4,
APIC_VECTOR_DEVICE5,
APIC_VECTOR_DEVICE6,
APIC_VECTOR_DEVICE7,
APIC_VECTOR_DEVICE7,
APIC_VECTOR_DEVICE7,
APIC_VECTOR_DEVICE7,
APIC_VECTOR_DEVICE7,
APIC_VECTOR_DEVICE7,
APIC_VECTOR_DEVICE7,
APIC_VECTOR_DEVICE7,
APIC_VECTOR_DEVICE7,
APIC_VECTOR_DEVICE7,
APIC_VECTOR_DEVICE7,
APIC_VECTOR_DEVICE7,
APIC_VECTOR_DEVICE7,
APIC_VECTOR_DEVICE7,
APIC_VECTOR_DEVICE7,
APIC_VECTOR_DEVICE7,
APIC_VECTOR_DEVICE7,
APIC_VECTOR_GENERIC,
APIC_VECTOR_CLOCK,
APIC_VECTOR_IPI,
APIC_VECTOR_POWERFAIL,
APIC_VECTOR_NMI
};
/* Return the TPR corresponding to the run level from the transformation table. */
return TransformationTable[RunLevel];
}

8
xtoskrnl/hl/apic.c → xtoskrnl/hl/pic.c
View File

@ -1,8 +1,8 @@
/**
* PROJECT: ExectOS
* COPYRIGHT: See COPYING.md in the top level directory
* FILE: xtoskrnl/hl/apic.c
* DESCRIPTION: Advanced Programmable Interrupt Controller (APIC) support
* FILE: xtoskrnl/hl/pic.c
* DESCRIPTION: Programmable Interrupt Controller (PIC) support
* DEVELOPERS: Rafal Kupiec <belliash@codingworkshop.eu.org>
*/
@ -23,7 +23,7 @@ XTFASTCALL
ULONG
HlReadApicRegister(IN APIC_REGISTER Register)
{
return RtlReadRegisterLong((PULONG)APIC_BASE + (Register << 4));
return RtlReadRegisterLong((PULONG)(APIC_BASE + (Register << 4)));
}
/**
@ -44,5 +44,5 @@ VOID
HlWriteApicRegister(IN APIC_REGISTER Register,
IN ULONG Value)
{
RtlWriteRegisterLong((PULONG)APIC_BASE + (Register << 4), Value);
RtlWriteRegisterLong((PULONG)(APIC_BASE + (Register << 4)), Value);
}

17
xtoskrnl/includes/hl.h
View File

@ -40,6 +40,11 @@ HlDrawPixel(IN ULONG PosX,
IN ULONG PosY,
IN ULONG Color);
XTFASTCALL
KRUNLEVEL
HlGetRunLevel(VOID);
XTCDECL
XTSTATUS
HlInitializeComPort(IN OUT PCPPORT Port,
@ -55,9 +60,21 @@ XTFASTCALL
ULONG
HlReadApicRegister(IN APIC_REGISTER Register);
XTFASTCALL
VOID
HlSetRunLevel(IN KRUNLEVEL RunLevel);
XTFASTCALL
VOID
HlWriteApicRegister(IN APIC_REGISTER Register,
IN ULONG Value);
XTFASTCALL
KRUNLEVEL
HlpTransformApicTprToRunLevel(IN UCHAR Tpr);
XTFASTCALL
UCHAR
HlpTransformRunLevelToApicTpr(IN KRUNLEVEL RunLevel);
#endif /* __XTOSKRNL_HL_H */

14
xtoskrnl/includes/ke.h
View File

@ -17,9 +17,13 @@ XTAPI
VOID
KeClearEvent(IN PKEVENT Event);
XTFASTCALL
KRUNLEVEL
KeGetCurrentRunLevel(VOID);
XTAPI
VOID
KeHaltSystem();
KeHaltSystem(VOID);
XTAPI
VOID
@ -47,6 +51,10 @@ KeInitializeThread(IN PKPROCESS Process,
IN PVOID Stack,
IN BOOLEAN StartThread);
XTFASTCALL
VOID
KeLowerRunLevel(IN KRUNLEVEL RunLevel);
XTAPI
VOID
KePanic(IN ULONG Code);
@ -59,6 +67,10 @@ KePanicEx(IN ULONG Code,
IN ULONG_PTR Parameter3,
IN ULONG_PTR Parameter4);
XTFASTCALL
KRUNLEVEL
KeRaiseRunLevel(IN KRUNLEVEL RunLevel);
XTAPI
LONG
KeSetEvent(IN PKEVENT Event,

2
xtoskrnl/ke/amd64/krnlinit.c
View File

@ -51,7 +51,7 @@ KepInitializeKernel(VOID)
CurrentThread->Priority = THREAD_HIGH_PRIORITY;
CurrentThread->State = Running;
CurrentThread->Affinity = (ULONG_PTR)1 << Prcb->Number;
CurrentThread->WaitIrql = DISPATCH_LEVEL;
CurrentThread->WaitRunLevel = DISPATCH_LEVEL;
CurrentProcess->ActiveProcessors |= (ULONG_PTR)1 << Prcb->Number;
}

2
xtoskrnl/ke/i686/krnlinit.c
View File

@ -51,7 +51,7 @@ KepInitializeKernel(VOID)
CurrentThread->Priority = THREAD_HIGH_PRIORITY;
CurrentThread->State = Running;
CurrentThread->Affinity = (ULONG_PTR)1 << Prcb->Number;
CurrentThread->WaitIrql = DISPATCH_LEVEL;
CurrentThread->WaitRunLevel = DISPATCH_LEVEL;
CurrentProcess->ActiveProcessors |= (ULONG_PTR)1 << Prcb->Number;
}

2
xtoskrnl/ke/i686/kthread.c
View File

@ -43,7 +43,7 @@ KepInitializeThreadContext(IN PKTHREAD Thread,
PFX_SAVE_FORMAT FxSaveFormat;
/* Set initial thread frame */
ThreadFrame = ((PKTHREAD_INIT_FRAME)Thread->InitialStack) - sizeof(KTHREAD_INIT_FRAME);
ThreadFrame = (PKTHREAD_INIT_FRAME)(Thread->InitialStack - sizeof(KTHREAD_INIT_FRAME));
/* Fill floating point save area with zeroes */
RtlZeroMemory(&ThreadFrame->NpxFrame, sizeof(FX_SAVE_AREA));

2
xtoskrnl/ke/panic.c
View File

@ -18,7 +18,7 @@
*/
XTAPI
VOID
KeHaltSystem()
KeHaltSystem(VOID)
{
/* Enter infinite loop */
for(;;)

81
xtoskrnl/ke/runlevel.c Normal file
View File

@ -0,0 +1,81 @@
/**
* PROJECT: ExectOS
* COPYRIGHT: See COPYING.md in the top level directory
* FILE: xtoskrnl/ke/runlevel.c
* DESCRIPTION: Running Level management support
* DEVELOPERS: Rafal Kupiec <belliash@codingworkshop.eu.org>
*/
#include <xtos.h>
/**
* Gets the current running level of the current processor.
*
* @return This routine returns the current running level.
*
* @since XT 1.0
*/
XTFASTCALL
KRUNLEVEL
KeGetCurrentRunLevel(VOID)
{
return HlGetRunLevel();
}
/**
* Lowers the running level of the current processor.
*
* @param RunLevel
* Supplies the new running level to lower to.
*
* @return This routine does not return any value.
*
* @since XT 1.0
*/
XTFASTCALL
VOID
KeLowerRunLevel(IN KRUNLEVEL RunLevel)
{
KRUNLEVEL OldRunLevel;
/* Read current run level */
OldRunLevel = HlGetRunLevel();
/* Validate run level lowerage */
if(OldRunLevel > RunLevel)
{
/* Set new, lower run level */
HlSetRunLevel(RunLevel);
}
}
/**
* Raises the running level of the current processor.
*
* @param RunLevel
* Supplies the new running level to raise to.
*
* @return This routine returns the old running level.
*
* @since XT 1.0
*/
XTFASTCALL
KRUNLEVEL
KeRaiseRunLevel(IN KRUNLEVEL RunLevel)
{
KRUNLEVEL OldRunLevel;
/* Read current run level */
OldRunLevel = HlGetRunLevel();
/* Validate run level raise */
if(OldRunLevel < RunLevel)
{
/* Set new, higher run level */
HlSetRunLevel(RunLevel);
}
/* Return old run level */
return OldRunLevel;
}