Implement ArInterruptsEnabled() routine

xtoskrnl/ar/amd64/cpufunc.c

@@ -140,6 +140,26 @@ ArHalt(VOID)
     asm volatile("hlt");
 }
 
+/**
+ * Checks whether interrupts are enabled or not.
+ *
+ * @return This routine returns TRUE if interrupts are enabled, or FALSE otherwise.
+ *
+ * @since XT 1.0
+ */
+XTCDECL
+BOOLEAN
+ArInterruptsEnabled(VOID)
+{
+    ULONG_PTR Flags;
+
+    /* Get RFLAGS register */
+    Flags = ArGetCpuFlags();
+
+    /* Check if interrupts are enabled and return result */
+    return (Flags & X86_EFLAGS_IF_MASK) ? TRUE : FALSE;
+}
+
 /**
  * Invalidates the TLB (Translation Lookaside Buffer) for specified virtual address.
  *

xtoskrnl/ar/i686/cpufunc.c

@@ -140,6 +140,26 @@ ArHalt(VOID)
     asm volatile("hlt");
 }
 
+/**
+ * Checks whether interrupts are enabled or not.
+ *
+ * @return This routine returns TRUE if interrupts are enabled, or FALSE otherwise.
+ *
+ * @since XT 1.0
+ */
+XTCDECL
+BOOLEAN
+ArInterruptsEnabled(VOID)
+{
+    ULONG_PTR Flags;
+
+    /* Get RFLAGS register */
+    Flags = ArGetCpuFlags();
+
+    /* Check if interrupts are enabled and return result */
+    return (Flags & X86_EFLAGS_IF_MASK) ? TRUE : FALSE;
+}
+
 /**
  * Invalidates the TLB (Translation Lookaside Buffer) for specified virtual address.
  *

xtoskrnl/includes/amd64/ari.h

@@ -42,6 +42,10 @@ XTAPI
 VOID
 ArInitializeProcessor(IN PVOID ProcessorStructures);
 
+XTCDECL
+BOOLEAN
+ArInterruptsEnabled(VOID);
+
 XTCDECL
 VOID
 ArInvalidateTlbEntry(IN PVOID Address);

xtoskrnl/includes/i686/ari.h

@@ -42,6 +42,10 @@ XTAPI
 VOID
 ArInitializeProcessor(IN PVOID ProcessorStructures);
 
+XTCDECL
+BOOLEAN
+ArInterruptsEnabled(VOID);
+
 XTCDECL
 VOID
 ArInvalidateTlbEntry(IN PVOID Address);