Implement support for APIC Self-InterProcessor Interrupts (SIPI)
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This commit is contained in:
2026-04-09 20:25:55 +02:00
parent d00e96baa4
commit 7d8bfa8f0a
4 changed files with 30 additions and 0 deletions

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@@ -134,6 +134,7 @@ typedef enum _APIC_REGISTER
APIC_TICR = 0x38, /* Initial Count Register for Timer */ APIC_TICR = 0x38, /* Initial Count Register for Timer */
APIC_TCCR = 0x39, /* Current Count Register for Timer */ APIC_TCCR = 0x39, /* Current Count Register for Timer */
APIC_TDCR = 0x3E, /* Timer Divide Configuration Register */ APIC_TDCR = 0x3E, /* Timer Divide Configuration Register */
APIC_SIPI = 0x3F, /* Self-IPI Register */
APIC_EAFR = 0x40, /* extended APIC Feature register */ APIC_EAFR = 0x40, /* extended APIC Feature register */
APIC_EACR = 0x41, /* Extended APIC Control Register */ APIC_EACR = 0x41, /* Extended APIC Control Register */
APIC_SEOI = 0x42, /* Specific End Of Interrupt Register */ APIC_SEOI = 0x42, /* Specific End Of Interrupt Register */

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@@ -141,6 +141,7 @@ typedef enum _APIC_REGISTER
APIC_TICR = 0x38, /* Initial Count Register for Timer */ APIC_TICR = 0x38, /* Initial Count Register for Timer */
APIC_TCCR = 0x39, /* Current Count Register for Timer */ APIC_TCCR = 0x39, /* Current Count Register for Timer */
APIC_TDCR = 0x3E, /* Timer Divide Configuration Register */ APIC_TDCR = 0x3E, /* Timer Divide Configuration Register */
APIC_SIPI = 0x3F, /* Self-IPI Register */
APIC_EAFR = 0x40, /* extended APIC Feature register */ APIC_EAFR = 0x40, /* extended APIC Feature register */
APIC_EACR = 0x41, /* Extended APIC Control Register */ APIC_EACR = 0x41, /* Extended APIC Control Register */
APIC_SEOI = 0x42, /* Specific End Of Interrupt Register */ APIC_SEOI = 0x42, /* Specific End Of Interrupt Register */

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@@ -404,6 +404,33 @@ HL::Pic::SendIpi(ULONG ApicId,
} }
} }
/**
* Sends a Self-IPI (Inter-Processor Interrupt) to the current CPU.
*
* @param Vector
* Supplies the IPI vector to send.
*
* @return This routine does not return any value.
*
* @since XT 1.0
*/
XTAPI
VOID
HL::Pic::SendSelfIpi(ULONG Vector)
{
/* Check current APIC mode */
if(ApicMode == APIC_MODE_X2APIC)
{
/* In x2APIC mode, a dedicated Self-IPI register is used */
WriteApicRegister(APIC_SIPI, Vector);
}
else
{
/* In xAPIC compatibility mode, ICR0 is used */
WriteApicRegister(APIC_ICR0, Vector | (1 << 18));
}
}
/** /**
* Writes to the APIC register. * Writes to the APIC register.
* *

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@@ -28,6 +28,7 @@ namespace HL
STATIC XTAPI VOID SendEoi(VOID); STATIC XTAPI VOID SendEoi(VOID);
STATIC XTAPI VOID SendIpi(ULONG ApicId, STATIC XTAPI VOID SendIpi(ULONG ApicId,
ULONG Vector); ULONG Vector);
STATIC XTAPI VOID SendSelfIpi(ULONG Vector);
STATIC XTFASTCALL VOID WriteApicRegister(IN APIC_REGISTER Register, STATIC XTFASTCALL VOID WriteApicRegister(IN APIC_REGISTER Register,
IN ULONGLONG Value); IN ULONGLONG Value);