Extract trampoline code into a separate file
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2468d80078
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c4a7df6f38
GPG Key ID:
C40F06CB7493C1F5
@ -9,6 +9,7 @@ include_directories(
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# Specify list of library source code files
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list(APPEND LIBXTOS_SOURCE
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${XTOSKRNL_SOURCE_DIR}/ar/${ARCH}/boot.S
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${XTOSKRNL_SOURCE_DIR}/ar/${ARCH}/cpufunc.c
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${XTOSKRNL_SOURCE_DIR}/hl/cport.c
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${XTOSKRNL_SOURCE_DIR}/hl/${ARCH}/ioport.c
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@ -23,6 +24,7 @@ list(APPEND LIBXTOS_SOURCE
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# Specify list of kernel source code files
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list(APPEND XTOSKRNL_SOURCE
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${XTOSKRNL_SOURCE_DIR}/ar/${ARCH}/archsup.S
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${XTOSKRNL_SOURCE_DIR}/ar/${ARCH}/boot.S
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${XTOSKRNL_SOURCE_DIR}/ar/${ARCH}/cpufunc.c
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${XTOSKRNL_SOURCE_DIR}/ar/${ARCH}/globals.c
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${XTOSKRNL_SOURCE_DIR}/ar/${ARCH}/procsup.c
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@ -4,7 +4,6 @@
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* FILE: xtoskrnl/ar/amd64/archsup.S
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* DESCRIPTION: Provides AMD64 architecture features not implementable in C
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* DEVELOPERS: Rafal Kupiec <belliash@codingworkshop.eu.org>
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* Aiken Harris <harraiken91@gmail.com>
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*/
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#include <amd64/asmsup.h>
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@ -13,126 +12,6 @@
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.text
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/**
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* Enables eXtended Physical Addressing (XPA).
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*
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* @param PageMap
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* Supplies a pointer to the page map to be used.
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*
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* @return This routine does not return any value.
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*
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* @since XT 1.0
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*/
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.global ArEnableExtendedPhysicalAddressing
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ArEnableExtendedPhysicalAddressing:
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/* Save the original CR4 register */
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movq %cr4, %rax
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/* Save the state of stack pointer and non-volatile registers */
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movq %rsp, XpaRegisterSaveArea(%rip)
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movq %rbp, XpaRegisterSaveArea+0x08(%rip)
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movq %rax, XpaRegisterSaveArea+0x10(%rip)
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movq %rbx, XpaRegisterSaveArea+0x18(%rip)
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/* Save the original CR0 register */
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movq %cr0, %rbp
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/* Load temporary GDT required for mode transitions */
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leaq XpaTemporaryGdtDesc(%rip), %rax
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movq %rax, XpaTemporaryGdtBase(%rip)
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lgdtq XpaTemporaryGdtSize(%rip)
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/* Load addresses for entering compatibility mode and re-entering long mode */
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leaq XpaEnterCompatMode(%rip), %rax
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leaq XpaEnterLongMode(%rip), %rbx
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/* Push the 32-bit code segment selector and the target address for a far jump */
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pushq $GDT_R0_CMCODE
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pushq %rax
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/* Perform a far return to switch to 32-bit compatibility mode */
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lretq
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XpaEnterCompatMode:
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/* Enter 32-bit compatibility mode */
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.code32
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/* Store the PageMap pointer on the stack for future use */
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pushl %ecx
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/* Set the stack segment to the 32-bit data segment selector */
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movl $GDT_R0_DATA, %eax
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movl %eax, %ss
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/* Disable PGE and PCIDE to ensure all TLB entries will be flushed */
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movl %cr4, %eax
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andl $~(CR4_PGE | CR4_PCIDE), %eax
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movl %eax, %cr4
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/* Temporarily disable paging */
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movl %ebp, %eax
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andl $~CR0_PG, %eax
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movl %eax, %cr0
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/* Disable Long Mode as prerequisite for enabling 5-level paging */
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movl $X86_MSR_EFER, %ecx
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rdmsr
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andl $~X86_MSR_EFER_LME, %eax
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wrmsr
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/* Transition to 5-level paging (PML5/LA57) */
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movl %cr4, %eax
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orl $CR4_LA57, %eax
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movl %eax, %cr4
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/* Restore the PageMap pointer from the stack and load it into CR3 */
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popl %ecx
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movl %ecx, %cr3
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/* Re-enable Long Mode */
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movl $X86_MSR_EFER, %ecx
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rdmsr
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orl $X86_MSR_EFER_LME, %eax
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wrmsr
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/* Restore CR0 with paging enabled and flush the instruction pipeline */
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movl %ebp, %cr0
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call XpaFlushInstructions
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XpaFlushInstructions:
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/* Push the 64-bit code segment selector and the target address for a far jump */
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pushl $GDT_R0_CODE
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pushl %ebx
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/* Perform a far return to switch to 64-bit long mode */
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lretl
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XpaEnterLongMode:
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/* Enter 64-bit long mode */
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.code64
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/* Restore the stack pointer and non-volatile registers */
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movq XpaRegisterSaveArea(%rip), %rsp
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movq XpaRegisterSaveArea+8(%rip), %rbp
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movq XpaRegisterSaveArea+0x10(%rip), %rax
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movq XpaRegisterSaveArea+0x18(%rip), %rbx
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/* Restore the original CR4 register with LA57 bit set */
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orq $CR4_LA57, %rax
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movq %rax, %cr4
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/* Return to the caller */
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retq
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/* Data section for saving registers and temporary GDT */
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XpaRegisterSaveArea: .quad 0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000
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XpaTemporaryGdtSize: .short ArEnableExtendedPhysicalAddressingEnd - XpaTemporaryGdtDesc - 1
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XpaTemporaryGdtBase: .quad 0x0000000000000000
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XpaTemporaryGdtDesc: .quad 0x0000000000000000, 0x00CF9A000000FFFF, 0x00AF9A000000FFFF, 0x00CF92000000FFFF
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.global ArEnableExtendedPhysicalAddressingEnd
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ArEnableExtendedPhysicalAddressingEnd:
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/**
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* Creates a trap handler for the specified vector.
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*
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133
xtoskrnl/ar/amd64/boot.S
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133
xtoskrnl/ar/amd64/boot.S
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@ -0,0 +1,133 @@
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/**
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* PROJECT: ExectOS
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* COPYRIGHT: See COPYING.md in the top level directory
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* FILE: xtoskrnl/ar/amd64/boot.S
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* DESCRIPTION: AMD64-specific boot code for setting up the low-level CPU environment
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* DEVELOPERS: Aiken Harris <harraiken91@gmail.com>
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*/
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#include <amd64/asmsup.h>
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.altmacro
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.text
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/**
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* Enables eXtended Physical Addressing (XPA).
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*
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* @param PageMap
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* Supplies a pointer to the page map to be used.
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*
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* @return This routine does not return any value.
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*
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* @since XT 1.0
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*/
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.global ArEnableExtendedPhysicalAddressing
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ArEnableExtendedPhysicalAddressing:
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/* Save the original CR4 register */
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movq %cr4, %rax
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/* Save the state of stack pointer and non-volatile registers */
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movq %rsp, XpaRegisterSaveArea(%rip)
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movq %rbp, XpaRegisterSaveArea+0x08(%rip)
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movq %rax, XpaRegisterSaveArea+0x10(%rip)
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movq %rbx, XpaRegisterSaveArea+0x18(%rip)
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/* Save the original CR0 register */
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movq %cr0, %rbp
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/* Load temporary GDT required for mode transitions */
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leaq XpaTemporaryGdtDesc(%rip), %rax
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movq %rax, XpaTemporaryGdtBase(%rip)
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lgdtq XpaTemporaryGdtSize(%rip)
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/* Load addresses for entering compatibility mode and re-entering long mode */
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leaq XpaEnterCompatMode(%rip), %rax
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leaq XpaEnterLongMode(%rip), %rbx
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/* Push the 32-bit code segment selector and the target address for a far jump */
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pushq $GDT_R0_CMCODE
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pushq %rax
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/* Perform a far return to switch to 32-bit compatibility mode */
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lretq
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XpaEnterCompatMode:
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/* Enter 32-bit compatibility mode */
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.code32
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/* Store the PageMap pointer on the stack for future use */
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pushl %ecx
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/* Set the stack segment to the 32-bit data segment selector */
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movl $GDT_R0_DATA, %eax
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movl %eax, %ss
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/* Disable PGE and PCIDE to ensure all TLB entries will be flushed */
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movl %cr4, %eax
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andl $~(CR4_PGE | CR4_PCIDE), %eax
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movl %eax, %cr4
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/* Temporarily disable paging */
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movl %ebp, %eax
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andl $~CR0_PG, %eax
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movl %eax, %cr0
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/* Disable Long Mode as prerequisite for enabling 5-level paging */
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movl $X86_MSR_EFER, %ecx
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rdmsr
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andl $~X86_MSR_EFER_LME, %eax
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wrmsr
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/* Transition to 5-level paging (PML5/LA57) */
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movl %cr4, %eax
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orl $CR4_LA57, %eax
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movl %eax, %cr4
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/* Restore the PageMap pointer from the stack and load it into CR3 */
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popl %ecx
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movl %ecx, %cr3
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/* Re-enable Long Mode */
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movl $X86_MSR_EFER, %ecx
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rdmsr
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orl $X86_MSR_EFER_LME, %eax
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wrmsr
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/* Restore CR0 with paging enabled and flush the instruction pipeline */
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movl %ebp, %cr0
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call XpaFlushInstructions
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XpaFlushInstructions:
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/* Push the 64-bit code segment selector and the target address for a far jump */
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pushl $GDT_R0_CODE
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pushl %ebx
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/* Perform a far return to switch to 64-bit long mode */
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lretl
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XpaEnterLongMode:
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/* Enter 64-bit long mode */
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.code64
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/* Restore the stack pointer and non-volatile registers */
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movq XpaRegisterSaveArea(%rip), %rsp
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movq XpaRegisterSaveArea+8(%rip), %rbp
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movq XpaRegisterSaveArea+0x10(%rip), %rax
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movq XpaRegisterSaveArea+0x18(%rip), %rbx
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/* Restore the original CR4 register with LA57 bit set */
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orq $CR4_LA57, %rax
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movq %rax, %cr4
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/* Return to the caller */
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retq
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/* Data section for saving registers and temporary GDT */
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XpaRegisterSaveArea: .quad 0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000
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XpaTemporaryGdtSize: .short ArEnableExtendedPhysicalAddressingEnd - XpaTemporaryGdtDesc - 1
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XpaTemporaryGdtBase: .quad 0x0000000000000000
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XpaTemporaryGdtDesc: .quad 0x0000000000000000, 0x00CF9A000000FFFF, 0x00AF9A000000FFFF, 0x00CF92000000FFFF
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.global ArEnableExtendedPhysicalAddressingEnd
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ArEnableExtendedPhysicalAddressingEnd:
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14
xtoskrnl/ar/i686/boot.S
Normal file
14
xtoskrnl/ar/i686/boot.S
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@ -0,0 +1,14 @@
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/**
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* PROJECT: ExectOS
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* COPYRIGHT: See COPYING.md in the top level directory
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* FILE: xtoskrnl/ar/i686/boot.S
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* DESCRIPTION: i686-specific boot code for setting up the low-level CPU environment
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* DEVELOPERS: Aiken Harris <harraiken91@gmail.com>
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*/
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#include <amd64/asmsup.h>
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.altmacro
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.text
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