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Implement HlInvalidateTlbEntry(), HlReadModelSpecificRegister() and HlWriteModelSpecificRegister() routines
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This commit is contained in:
Rafal Kupiec 2022-12-27 23:19:33 +01:00
parent 938cd175c8
commit f46615f92c
Signed by: belliash
GPG Key ID: 4E829243E0CFE6B4
4 changed files with 166 additions and 8 deletions
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13
sdk/xtdk/amd64/hlfuncs.h
View File

@ -30,6 +30,10 @@ XTCDECL
VOID
HlHalt();
XTCDECL
VOID
HlInvalidateTlbEntry(IN PVOID Address);
XTCDECL
UCHAR
HlIoPortInByte(IN USHORT Port);
@ -61,6 +65,10 @@ XTCDECL
ULONG_PTR
HlReadControlRegister(IN USHORT ControlRegister);
XTCDECL
ULONGLONG
HlReadModelSpecificRegister(IN ULONG Register);
XTCDECL
VOID
HlSetInterruptFlag();
@ -70,4 +78,9 @@ VOID
HlWriteControlRegister(IN USHORT ControlRegister,
IN UINT_PTR Value);
XTCDECL
VOID
HlWriteModelSpecificRegister(IN ULONG Register,
IN ULONGLONG Value);
#endif /* __XTDK_AMD64_HLFUNCS_H */

13
sdk/xtdk/i686/hlfuncs.h
View File

@ -30,6 +30,10 @@ XTCDECL
VOID
HlHalt();
XTCDECL
VOID
HlInvalidateTlbEntry(IN PVOID Address);
XTCDECL
UCHAR
HlIoPortInByte(IN USHORT Port);
@ -61,6 +65,10 @@ XTCDECL
ULONG_PTR
HlReadControlRegister(IN USHORT ControlRegister);
XTCDECL
ULONGLONG
HlReadModelSpecificRegister(IN ULONG Register);
XTCDECL
VOID
HlSetInterruptFlag();
@ -70,4 +78,9 @@ VOID
HlWriteControlRegister(IN USHORT ControlRegister,
IN UINT_PTR Value);
XTCDECL
VOID
HlWriteModelSpecificRegister(IN ULONG Register,
IN ULONGLONG Value);
#endif /* __XTDK_I686_HLFUNCS_H */

73
xtoskrnl/hl/amd64/cpufunc.c
View File

@ -75,11 +75,28 @@ HlCpuId(IN OUT PCPUID_REGISTERS Registers)
XTCDECL
VOID
HlHalt()
{
while(TRUE)
{
asm volatile("hlt");
}
/**
* Invalidates the TLB (Translation Lookaside Buffer) for specified virtual address.
*
* @param Address
* Suuplies a virtual address whose associated TLB entry will be invalidated.
*
* @return This routine does not return any value.
*
* @since XT 1.0
*/
XTCDECL
VOID
HlInvalidateTlbEntry(IN PVOID Address)
{
asm volatile("invlpg (%0)"
:
: "b"(Address)
: "memory");
}
/**
@ -280,6 +297,30 @@ HlReadControlRegister(IN USHORT ControlRegister)
return Value;
}
/**
* Reads a 64-bit value from the requested Model Specific Register (MSR).
*
* @param Register
* Supplies the MSR to read.
*
* @return This routine returns the 64-bit MSR value.
*
* @since XT 1.0
*/
XTCDECL
ULONGLONG
HlReadModelSpecificRegister(IN ULONG Register)
{
ULONG Low, High;
asm volatile("rdmsr"
: "=a"(Low),
"=d"(High)
: "c"(Register));
return ((ULONGLONG)High << 32) | Low;
}
/**
* Instructs the processor to set the interrupt flag.
*
@ -352,3 +393,31 @@ HlWriteControlRegister(IN USHORT ControlRegister,
break;
}
}
/**
* Writes a 64-bit value to the requested Model Specific Register (MSR).
*
* @param Register
* Supplies the MSR register to write.
*
* @param Value
* Supplies the 64-bit value to write.
*
* @return This routine does not return any value.
*
* @since XT 1.0
*/
XTCDECL
VOID
HlWriteModelSpecificRegister(IN ULONG Register,
IN ULONGLONG Value)
{
ULONG Low = Value & 0xFFFFFFFF;
ULONG High = Value >> 32;
asm volatile("wrmsr"
:
: "c"(Register),
"a"(Low),
"d"(High));
}

67
xtoskrnl/hl/i686/cpufunc.c
View File

@ -75,11 +75,28 @@ HlCpuId(IN OUT PCPUID_REGISTERS Registers)
XTCDECL
VOID
HlHalt()
{
while(TRUE)
{
asm volatile("hlt");
}
/**
* Invalidates the TLB (Translation Lookaside Buffer) for specified virtual address.
*
* @param Address
* Suuplies a virtual address whose associated TLB entry will be invalidated.
*
* @return This routine does not return any value.
*
* @since XT 1.0
*/
XTCDECL
VOID
HlInvalidateTlbEntry(PVOID Address)
{
asm volatile("invlpg (%0)"
:
: "b"(Address)
: "memory");
}
/**
@ -274,6 +291,28 @@ HlReadControlRegister(IN USHORT ControlRegister)
return Value;
}
/**
* Reads a 64-bit value from the requested Model Specific Register (MSR).
*
* @param Register
* Supplies the MSR to read.
*
* @return This routine returns the 64-bit MSR value.
*
* @since XT 1.0
*/
XTCDECL
ULONGLONG
HlReadModelSpecificRegister(IN ULONG Register)
{
ULONGLONG Value;
asm volatile("rdmsr"
: "=A" (Value)
: "c" (Register));
return Value;
}
/**
* Instructs the processor to set the interrupt flag.
*
@ -339,3 +378,27 @@ HlWriteControlRegister(IN USHORT ControlRegister,
break;
}
}
/**
* Writes a 64-bit value to the requested Model Specific Register (MSR).
*
* @param Register
* Supplies the MSR register to write.
*
* @param Value
* Supplies the 64-bit value to write.
*
* @return This routine does not return any value.
*
* @since XT 1.0
*/
XTCDECL
VOID
HlWriteModelSpecificRegister(IN ULONG Register,
IN ULONGLONG Value)
{
asm volatile("wrmsr"
:
: "c" (Register),
"A" (Value));
}