82 Commits

Author	SHA1	Message	Date
PerikiyoXD	289b1bdebc	Rework _CPU_FEATURES structure	2023-11-27 22:04:31 +01:00
PerikiyoXD	323c173abe	Merge branch 'master' into prcb-cpu-features	2023-11-27 19:11:34 +01:00
Rafal Kupiec	4ca4e298f0	Add more PIC/APIC related definitions	2023-11-26 23:35:14 +01:00
PerikiyoXD	73c768ba0e	Merge branch 'master' into prcb-cpu-features	2023-11-26 18:53:01 +01:00
Rafal Kupiec	14a966043e	Add missing Interrupt request level definitions	2023-11-25 18:50:59 +01:00
Rafal Kupiec	0e6bf984a5	Add APIC vector definitions	2023-11-25 18:33:01 +01:00
Rafal Kupiec	55cc62f5a0	Rename KIRQL to KRUNLEVEL type	2023-11-25 00:32:55 +01:00
PerikiyoXD	a270c08dcf	feat: Add CPU vendor and features identification ... Add functionality to identify the CPU vendor and features using the CPUID instruction. The CPU vendor information is stored in the Processor Control Block (PRCB), including the vendor name and a corresponding enumeration. CPU features are also retrieved and stored in the PRCB. Previously, the CPU vendor was not properly stored in the PRCB, caused by a missing type cast. Using Rtl functions to copy the CPU vendor name to the PRCB. Details: - Introduced functions `ArpSetCpuVendor` and `ArpSetCpuFeatures` to set CPU vendor and features, respectively. - Modified `ArpIdentifyProcessor` to call the new functions for vendor and features identification. - Added `CPU_FEATURES` structure to `KPROCESSOR_CONTROL_BLOCK` structure to store CPU features. Tests: - Tested x86_64 on QEMU. Verified that the CPU vendor and features are correctly identified and stored in the PRCB.	2023-11-23 23:26:39 +01:00
belliash	a3c28cee73	Initial XTLDR APIC support, finds and maps base APIC address for kernel	2023-11-20 15:18:22 +01:00
belliash	83c0accc5f	Update EFLAGS masks	2023-11-09 16:12:24 +01:00
belliash	641b34b119	Fixes in i686 version of KepInitializeThreadContext()	2023-11-08 16:06:01 +01:00
belliash	91ce0f9947	Compensate missing return address, which is a 4-byte on i686 and an 8-byte on amd64	2023-11-05 20:07:13 +01:00
belliash	f05a262da2	Cleanup XTDK and XTOSKRNL headers	2023-10-29 09:58:47 +01:00
belliash	798e4c1d22	Cleanup MM subsystem headers	2023-10-29 00:52:05 +02:00
belliash	600c86949b	Cleanup RTL subsystem headers	2023-10-29 00:14:01 +02:00
belliash	d920cae481	Fix build by defining more routines used by XTLDR	2023-10-28 23:41:52 +02:00
belliash	ad15c55a39	Cleanup AR subsystem headers	2023-10-28 23:35:34 +02:00
belliash	358b20f1a1	Reorder routines	2023-04-04 22:35:06 +02:00
belliash	e6b64b741a	Initialize thread context for i686	2023-03-15 23:05:18 +01:00
belliash	3afbc7e419	Introduce SIMD save area in place of FN/FX and use anonymous union inside FX_SAVE_AREA structure	2023-03-15 22:19:18 +01:00
belliash	a8fa702b05	Unify KSWITCH_FRAME naming with AMD64	2023-03-15 19:15:31 +01:00
belliash	10ccf67e8e	Add missing forward declarations	2023-03-14 22:50:32 +01:00
belliash	cec8a13e4c	Add context control flags and thread frames for i686 architecture	2023-03-14 22:47:32 +01:00
belliash	70795ae57a	Add EFLAGS and THREAD_ENVIRONMENT_BLOCK for x86	2023-03-05 18:11:57 +01:00
belliash	c5a9253ea8	Implement ArLoadLocalDescriptorTable() routine	2023-03-02 23:04:36 +01:00
belliash	870a6680b0	Add thread information block	2023-03-01 00:14:06 +01:00
belliash	3d42fcc0f5	Add KSWITCH_FRAME definition for i686 architecture	2023-03-01 00:03:20 +01:00
belliash	ef23acc3bc	Add Deferred Procedure Call (DPC) and processor power state related structures	2023-02-27 19:58:47 +01:00
belliash	e41de62dab	Implement ArYieldProcessor() routine	2023-02-27 17:28:20 +01:00
belliash	c8428241dd	Add missing headers containing forward references of MM routines	2023-02-20 22:22:32 +01:00
belliash	b1c2b209e3	Implement RtlGetStackLimits() routine	2023-02-15 20:12:58 +01:00
belliash	18a39f95bc	Add floating save area structure definitions	2023-02-15 20:07:17 +01:00
belliash	2e790bd9b2	Add pages related macros and definitions	2023-02-13 23:01:20 +01:00
belliash	e94cb2d3a7	Processor identification structures	2023-02-10 17:14:12 +01:00
belliash	e645cf664c	Set process and thread information in processor control block	2023-02-09 17:30:24 +01:00
belliash	9132c47cd9	Initial process and thread related structures	2023-02-08 23:40:58 +01:00
belliash	a32e18b237	Implement ArReadFSDualWord() routine	2023-02-07 23:19:22 +01:00
belliash	5eaf7d63a3	Initialize Page Attribute Table	2023-02-05 00:14:34 +01:00
belliash	f37722b6e6	Distinguish ProcessorBlock and ProcessorControlBlock	2023-02-03 19:28:03 +01:00
belliash	269214ed34	Another improvements to GDT	2023-02-03 18:00:37 +01:00
belliash	dc1a94b982	This is 'Processor Block'	2023-02-01 22:02:07 +01:00
belliash	21fbe6febe	Add IDT related definitions	2023-02-01 20:14:10 +01:00
belliash	5bbda188c6	IDT access levels and gate types	2023-02-01 00:51:13 +01:00
belliash	9a1e9b1084	Define TSS offsets	2023-01-30 23:43:10 +01:00
belliash	a761d3125a	Architecture specific initialization prior to processor structures initialization	2023-01-30 20:34:05 +01:00
belliash	6f068513cd	Initial processor block initialization	2023-01-30 19:07:05 +01:00
belliash	ce4e590347	Add missing forward declaration of ArInitializeProcessor() routine	2023-01-29 00:57:06 +01:00
belliash	900e71459a	Add missing x86 descriptor sizes	2023-01-29 00:54:36 +01:00
belliash	27e2fdf4f2	Introduce architecture library as new kernel subsystem and move selected routines into new subsystem	2023-01-28 10:34:55 +01:00
belliash	e94e50b5d9	Implement HlLoadInterruptDescriptorTable() intrinsics for loading IDT	2023-01-26 20:08:57 +01:00