15 Commits

Include renames

Author	SHA1	Message	Date
belliash	f36b59c961	Store processor identities in system info structure	2024-06-07 20:19:56 +02:00
belliash	4212453cf5	Fix APIC initialization code	2024-06-06 16:49:08 +02:00
belliash	ef65bceccd	Initialize legacy PIC and mask all interrupts	2024-06-05 16:08:54 +02:00
belliash	b061c87fc9	Fix routines with no prototype using XTAPI calling convention compiler warnings	2024-06-04 21:41:16 +02:00
belliash	8a4caba26f	Fix routine with no prototype using XTAPI calling convention compiler warning	2024-06-04 21:39:10 +02:00
belliash	94a40501d4	Mask APIC ICR0 and disable APIC interrupts for initialization time by raising APIC TPR	2024-05-24 23:39:06 +02:00
belliash	c34b6ff6c1	Take CPU number from processor block	2024-05-08 21:59:18 +02:00
belliash	f66e9aea9e	Store CPU number and mask interrupts in processor block	2024-05-07 16:21:38 +02:00
belliash	ac0b8ab36a	Allow to specify CPU number when initializing (A)PIC	2024-05-07 16:16:49 +02:00
belliash	40e0dd8c5e	Mask LVTERR first to prevent local APIC errors	2024-05-05 15:24:17 +02:00
belliash	c70d2e2afa	Routines with no prototype cannot use XTAPI calling convention	2024-02-20 16:37:57 +01:00
belliash	77bc796769	Implement HlClearApicErrors() and HlSendEoi() routines, change HlDisableLegacyPic() calling convention	2024-02-09 15:11:14 +01:00
belliash	31b8cd8d3d	Update HlDisablePic() description	2023-11-29 22:43:57 +01:00
Jozef Nagy	c8a54e602b	Disable legacy 8259 PIC before enabling APIC ... Reviewed-on: #5 Reviewed-by: Rafal Kupiec <belliash@noreply.codingworkshop.git> Co-authored-by: Jozef Nagy <schkwve@gmail.com> Co-committed-by: Jozef Nagy <schkwve@gmail.com>	2023-11-29 20:07:16 +01:00
belliash	9aafa63617	Move CPU and PIC support into common for i686 and amd64 place	2023-11-29 18:26:46 +01:00