Added 8259 PIC support #5
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Reference: xt-sys/exectos#5
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This PR adds multiple routines to use the legacy 8259 PIC.
Purpose
In order to enable the APIC, the PIC must be properly disabled with masked IRQs.
This is accomplished by calling
HlInitializePic(), which initializes the PIC and masks off every IRQ, and afterwards callingHlDisablePic(), which disables the PIC fully.Incase APIC is not present on the host system (CPUID returns with APIC bit set to 0), it is possible to use the 8259 PIC instead, by not calling
HlDisablePic().Proposed changes
HlInitializePic(VOID)HlSetMaskIrqPic(UINT Irq)HlClearMaskIrqPic(UINT Irq)HlDisablePic(VOID)HlWritePic(UCHAR Register, UCHAR Value)HlIoPortWait(VOID)@ -90,6 +90,25 @@#define COMPORT_REG_MSR 0x06 /* Modem Status Register */#define COMPORT_REG_SR 0x07 /* Scratch Register *//* 8259 PIC ports */Does any other platform than x86 and x86_64 support 8259 PIC? If not, this should be architecture specific.
@ -93,0 +94,4 @@#define PIC_MASTER_COMMAND 0xA0#define PIC_MASTER_DATA 0xA1#define PIC_SLAVE_COMMAND 0x20#define PIC_SLAVE_DATA 0x21I think Master and Slave (PIC1 and PIC2) I/O port addresses are swapped.
@ -146,0 +155,4 @@*/XTCDECLVOIDHlIoPortWait(VOID)Do you think this function might be useful anywhere else, or could we just call
HlIoPortOutByte(0x80, 0x00);directly as currently it is used only inHlWritePic()?@ -11,0 +26,4 @@/* Master PIC Vector offset */HlWritePic(PIC_MASTER_DATA, 0x20);/* Slave PIC Vector offset */What do you think about putting an empty line before each comment? In my opinion it is easy to read, if comment says what does below block of code do and each block ends up with an empty line.
@ -11,0 +40,4 @@HlWritePic(PIC_SLAVE_DATA, PIC_ICW4_8086);/* Mask all IRQs by default */for (UCHAR Irq = 0; Irq < 16; Irq++)Do we need to mask all IRQs if we finally disable PIC and use APIC? Do we want to support PIC as a failover?
I have not found any mention of IRQs being explicitly masked or unmasked in any documents, so I masked them so the kernel doesn't get interrupted when the IRQ isn't ready to be served yet (in the case that PIC is indeed used as a failsafe).
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