Refactor MMU for multi-paging support and add 5-Level paging #16
@ -43,14 +43,13 @@ XtpDeterminePagingLevel(IN CONST PWCHAR Parameters)
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/* Query CPUID */
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ArCpuId(&CpuRegisters);
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// TODO: Uncomment the following code when LA57 support is implemented in the bootloader
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// /* Check if eXtended Physical Addressing (XPA) is enabled and if LA57 is supported by the CPU */
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// if((CpuRegisters.Ecx & CPUID_FEATURES_ECX_LA57) &&
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// !(XtLdrProtocol->BootUtil.GetBooleanParameter(Parameters, L"NOXPA")))
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// {
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// /* Enable LA57 (PML5) */
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// return 4;
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// }
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/* Check if eXtended Physical Addressing (XPA) is enabled and if LA57 is supported by the CPU */
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if((CpuRegisters.Ecx & CPUID_FEATURES_ECX_LA57) &&
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!(XtLdrProtocol->BootUtil.GetBooleanParameter(Parameters, L"NOXPA")))
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{
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/* Enable LA57 (PML5) */
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return 5;
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}
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}
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/* Disable LA57 and use PML4 by default */
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@ -213,6 +212,9 @@ EFI_STATUS
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XtEnablePaging(IN PXTBL_PAGE_MAPPING PageMap)
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{
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EFI_STATUS Status;
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EFI_PHYSICAL_ADDRESS TrampolineAddress;
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PXT_TRAMPOLINE_ENTRY TrampolineEntry;
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ULONG_PTR TrampolineSize;
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/* Build page map */
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Status = XtLdrProtocol->Memory.BuildPageMap(PageMap, (PageMap->PageMapLevel > 4) ? MM_P5E_LA57_BASE : MM_PXE_BASE);
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@ -232,6 +234,29 @@ XtEnablePaging(IN PXTBL_PAGE_MAPPING PageMap)
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return Status;
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}
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/* Check the configured page map level to set the LA57 state accordingly */
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if(PageMap->PageMapLevel == 5)
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{
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/* Set the address of the trampoline code below 1MB */
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TrampolineAddress = MM_TRAMPOLINE_ADDRESS;
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/* Calculate the size of the trampoline code */
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TrampolineSize = (ULONG_PTR)ArEnableExtendedPhysicalAddressingEnd - (ULONG_PTR)ArEnableExtendedPhysicalAddressing;
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/* Allocate pages for the trampoline */
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Status = XtLdrProtocol->Memory.AllocatePages(AllocateAddress, EFI_SIZE_TO_PAGES(TrampolineSize), &TrampolineAddress);
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if(Status != STATUS_EFI_SUCCESS)
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{
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/* Failed to allocate memory for trampoline code */
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XtLdrProtocol->Debug.Print(L"Failed to allocate memory for trampoline code (Status code: %zX)\n", Status);
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return Status;
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}
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/* Set the trampoline entry point and copy its code into the allocated buffer */
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TrampolineEntry = (PXT_TRAMPOLINE_ENTRY)(UINT_PTR)TrampolineAddress;
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RtlCopyMemory(TrampolineEntry, ArEnableExtendedPhysicalAddressing, TrampolineSize);
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}
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/* Exit EFI Boot Services */
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XtLdrProtocol->Debug.Print(L"Exiting EFI boot services\n");
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Status = XtLdrProtocol->Util.ExitBootServices();
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@ -247,18 +272,19 @@ XtEnablePaging(IN PXTBL_PAGE_MAPPING PageMap)
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{
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/* Enable Linear Address 57-bit (LA57) extension */
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XtLdrProtocol->Debug.Print(L"Enabling Linear Address 57-bit (LA57)\n");
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/* Execute the trampoline to enable LA57 and write PML5 to CR3 */
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TrampolineEntry((UINT64)PageMap->PtePointer);
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}
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else
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{
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/* Disable Linear Address 57-bit (LA57) extension */
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XtLdrProtocol->Debug.Print(L"Disabling Linear Address 57-bit (LA57)\n");
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}
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/* Write PML4 to CR3 */
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/* Write PML4 to CR3 and enable paging */
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ArWriteControlRegister(3, (UINT_PTR)PageMap->PtePointer);
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/* Enable paging */
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ArWriteControlRegister(0, ArReadControlRegister(0) | CR0_PG);
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}
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/* Return success */
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return STATUS_EFI_SUCCESS;
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@ -29,9 +29,15 @@ typedef struct _XT_FRAMEBUFFER_PROTOCOL
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/* EFI XT Loader Protocol */
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EXTERN PXTBL_LOADER_PROTOCOL XtLdrProtocol;
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/* XTOS trampoline end address to calculate trampoline size */
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EXTERN PVOID ArEnableExtendedPhysicalAddressingEnd[];
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/* XTOS kernel entry point */
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typedef VOID (XTAPI *PXT_ENTRY_POINT)(IN PKERNEL_INITIALIZATION_BLOCK BootParameters);
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/* XTOS trampoline entry point */
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typedef VOID (*PXT_TRAMPOLINE_ENTRY)(UINT64 PageMap);
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/* XTOS boot protocol related routines forward references */
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XTCDECL
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EFI_STATUS
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