Refactor MMU for multi-paging support and add 5-Level paging #16

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harraiken merged 35 commits from harraiken_mm into master 2025-08-23 20:03:56 +02:00

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harraiken commented 2025-08-21 10:43:24 +02:00

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This pull request introduces a major architectural refactoring of the Memory Management Unit (MMU) to support multiple paging modes within a single kernel, adds full support for 5-level paging (LA57) on AMD64, and fixes a critical address calculation bug.

Architectural refactoring

1. A CMMPAGEMAP_ROUTINES structure has been introduced, containing function pointers for essential PTE manipulations (ClearPte, PteValid, SetPteCaching, SetPte). This allows the high-level MMU code to operate on an abstraction, while the low-level, mode-specific implementation is determined at runtime.
2. Dynamic paging mode selection:
   • On i686, the kernel now detects at boot whether PAE is enabled (CR4.PAE). Based on this, it assigns either MmpPml2Routines (for legacy 32-bit, 2-level paging) or MmpPml3Routines (for PAE, 3-level paging) to the global MmpPageMapRoutines pointer. This enables a single kernel binary to run on systems both with and without PAE.
   • On AMD64, a similar mechanism detects if 5-level paging is active (CR4.LA57) and selects between MmpPml4Routines (4-level) and MmpPml5Routines (5-level).
3. The PTE structures for i686 have been refactored. MMPTE is now a union that can represent both MMPML2_PTE (non-PAE) and MMPML3_PTE (PAE) formats, simplifying code that needs to handle both.

AMD64: 5-Level paging (LA57 / PML5) implementation

1. A new assembly routine, ArEnableExtendedPhysicalAddressing, is introduced. This code runs from a low-memory trampoline (< 1MB) to safely transition the CPU into 5-level paging mode. This involves temporarily entering 32-bit compatibility mode to set CR4.LA57, as required by the AMD64 architecture, and then re-enabling long mode.
2. XTLDR now maps the trampoline code, and upon exiting EFI Boot Services, executes it to enable LA57 before loading the kernel's new PML5 page table into CR3.
3. The page table setup logic now correctly handles self-mapping for the PML5 table, which is essential for the kernel's operation.

Critical bug fix: AMD64 MMU base address overflow

The previous MM_PTE_LA57_BASE address (0xFFFFF68000000000ULL) was too high. When calculating PTE addresses for high virtual memory regions, adding the virtual address offset resulted in a 64-bit integer overflow, leading to page faults at incorrect, non-canonical addresses. The new MM_PTE_LA57_BASE is 0xFFFF000000000000ULL, which prevents the overflow and ensures correct address translation for the entire 57-bit address space.

Code consolidation and cleanup

1. Paging-related global variables (like base addresses and VA bit width) have been consolidated into a central MmpPageMapInfo structure. This structure is initialized at boot by MmInitializePageMapSupport based on the detected paging mode, cleaning up global state and improving code organization.
2. The MmPageMapLevel global has been removed, as this information is now contained within the MmpPageMapInfo structure.
3. Low-level page mapping functions have been moved from init.c to new, dedicated pmap.c files for each architecture.

This pull request introduces a major architectural refactoring of the Memory Management Unit (MMU) to support multiple paging modes within a single kernel, adds full support for 5-level paging (LA57) on AMD64, and fixes a critical address calculation bug. ## Architectural refactoring 1. A CMMPAGEMAP_ROUTINES structure has been introduced, containing function pointers for essential PTE manipulations (ClearPte, PteValid, SetPteCaching, SetPte). This allows the high-level MMU code to operate on an abstraction, while the low-level, mode-specific implementation is determined at runtime. 2. Dynamic paging mode selection: - On i686, the kernel now detects at boot whether PAE is enabled (CR4.PAE). Based on this, it assigns either MmpPml2Routines (for legacy 32-bit, 2-level paging) or MmpPml3Routines (for PAE, 3-level paging) to the global MmpPageMapRoutines pointer. This enables a single kernel binary to run on systems both with and without PAE. - On AMD64, a similar mechanism detects if 5-level paging is active (CR4.LA57) and selects between MmpPml4Routines (4-level) and MmpPml5Routines (5-level). 3. The PTE structures for i686 have been refactored. MMPTE is now a union that can represent both MMPML2_PTE (non-PAE) and MMPML3_PTE (PAE) formats, simplifying code that needs to handle both. ## AMD64: 5-Level paging (LA57 / PML5) implementation 1. A new assembly routine, ArEnableExtendedPhysicalAddressing, is introduced. This code runs from a low-memory trampoline (< 1MB) to safely transition the CPU into 5-level paging mode. This involves temporarily entering 32-bit compatibility mode to set CR4.LA57, as required by the AMD64 architecture, and then re-enabling long mode. 2. XTLDR now maps the trampoline code, and upon exiting EFI Boot Services, executes it to enable LA57 before loading the kernel's new PML5 page table into CR3. 3. The page table setup logic now correctly handles self-mapping for the PML5 table, which is essential for the kernel's operation. ## Critical bug fix: AMD64 MMU base address overflow The previous MM_PTE_LA57_BASE address (0xFFFFF68000000000ULL) was too high. When calculating PTE addresses for high virtual memory regions, adding the virtual address offset resulted in a 64-bit integer overflow, leading to page faults at incorrect, non-canonical addresses. The new MM_PTE_LA57_BASE is 0xFFFF000000000000ULL, which prevents the overflow and ensures correct address translation for the entire 57-bit address space. ## Code consolidation and cleanup 1. Paging-related global variables (like base addresses and VA bit width) have been consolidated into a central MmpPageMapInfo structure. This structure is initialized at boot by MmInitializePageMapSupport based on the detected paging mode, cleaning up global state and improving code organization. 2. The MmPageMapLevel global has been removed, as this information is now contained within the MmpPageMapInfo structure. 3. Low-level page mapping functions have been moved from init.c to new, dedicated pmap.c files for each architecture.

harraiken added 35 commits 2025-08-21 10:43:24 +02:00

Use __asm__ to comply with disabled GNU extensions e8771dfc5b

Merge branch 'master' into harraiken_mm 8a23cc444f

Rename MM_LA57_SHIFT to MM_P5I_SHIFT for consistency e57985da8d

Add definitions for 5-level paging and refactor constants 3ca6d04f6b

Separate types for legacy (PML2) and PAE (PML3) paging 7e08dc286e

Update forward declarations for PML2/PML3 types 22f81a106b

Adapt i686 memory mapping to new PML3 types f85fe31b38

Prepare for architecture-specific paging initialization 5768d4bba6

Define page map information structure for both supported architectures 1dcd3fceed

Consolidate paging-related globals into MmpPageMapInfo 6a330e38f2

Remove PageMapLevel from the loader information block 8491e5fed1

Implement page map info initialization de2973ac42

Relocate page mapping helpers and add PML5 support 0ed59f223c

Introduce architecture-specific page map routines f77f2bbf92

Assign page map routines 720d525b95

Implement PML2/PML3 page table routines 57193eecc0

Refactor hardware memory mapping to use page map routine callbacks 1e11acee72

Fix type usage in XtpMapHardwareMemoryPool c3ece4f317

Implement PTE manipulation functions for AMD64 architecture f30d3df5b3

Implement MmpSetPteCaching function for AMD64 architecture a9dd1eaacd

Align parameters in PTE manipulation functions 017b8603d5

Temporarily disable LA57 paging d602038858

Correct VA masking in AMD64 page mapping functions c409400cbf

Implement PML5 self-mapping b639bf3077

Implement PML5 support in XtpMapHardwareMemoryPool 91a5db2ee4

Update and correct CR4 bit definitions 1a0bc7f65f

Expand CR4, MSR, and EFER register definitions ebae8c655c

Add trampoline to enable 5-level paging 2468d80078

Extract trampoline code into a separate file c4a7df6f38

Expose ArEnableExtendedPhysicalAddressing function in XTDK 4a7ea6009d

Map the physical page for trampoline code 9f6121e9b2

Allow specifying an allocation type when allocating pages 88b3a57962

Resolve build issues caused by the last commit d1b14fccdd

Enable LA57 by invoking the trampoline code 1ef2560ef6

Adjust LA57 base addresses to prevent overflow a84ef21571

harraiken merged commit 0b40a3fb10 into master 2025-08-23 20:03:56 +02:00

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belliash (Rafal Kupiec) harraiken (Aiken Harris) oscwllm (OSCW Agent)

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Reference: xt-sys/exectos#16