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Refactor MMU for multi-paging support and add 5-Level paging #16

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harraiken wants to merge 35 commits from harraiken_mm into master
pull from: harraiken_mm
merge into: xt-sys:master
Conversation 0 Commits 35 Files Changed 42 +9 -10
1 changed files with 9 additions and 10 deletions
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11
xtldr/arch/amd64/memory.c
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@ -338,21 +338,20 @@ BlpSelfMapPml(IN PXTBL_PAGE_MAPPING PageMap,
/* Check page map level */ /* Check page map level */
if(PageMap->PageMapLevel == 5) if(PageMap->PageMapLevel == 5)
{ {
/* Self-mapping for PML5 is not supported */ /* Calculate PML index based on provided self map address for PML5 */
BlDebugPrint(L"PML5 self-mapping not supported yet!\n"); PmlIndex = (SelfMapAddress >> MM_P5I_SHIFT) & 0x1FF;
return STATUS_EFI_UNSUPPORTED;
} }
else else
{ {
/* Calculate PML index based on provided self map address */ /* Calculate PML index based on provided self map address for PML4 */
PmlIndex = (SelfMapAddress >> MM_PXI_SHIFT) & 0x1FF; PmlIndex = (SelfMapAddress >> MM_PXI_SHIFT) & 0x1FF;
}
/* Add self-mapping for PML4 */ /* Add self-mapping */
RtlZeroMemory(&PmlBase[PmlIndex], sizeof(HARDWARE_PTE)); RtlZeroMemory(&PmlBase[PmlIndex], sizeof(HARDWARE_PTE));
PmlBase[PmlIndex].PageFrameNumber = (UINT_PTR)PageMap->PtePointer / EFI_PAGE_SIZE; PmlBase[PmlIndex].PageFrameNumber = (UINT_PTR)PageMap->PtePointer / EFI_PAGE_SIZE;
PmlBase[PmlIndex].Valid = 1; PmlBase[PmlIndex].Valid = 1;
PmlBase[PmlIndex].Writable = 1; PmlBase[PmlIndex].Writable = 1;
}
/* Return success */ /* Return success */
return STATUS_EFI_SUCCESS; return STATUS_EFI_SUCCESS;