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Refactor MMU for multi-paging support and add 5-Level paging #16

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harraiken wants to merge 35 commits from harraiken_mm into master
pull from: harraiken_mm
merge into: xt-sys:master
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1 changed files with 8 additions and 7 deletions
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15
xtldr/modules/xtos_o/amd64/memory.c
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@ -43,13 +43,14 @@ XtpDeterminePagingLevel(IN CONST PWCHAR Parameters)
/* Query CPUID */
ArCpuId(&CpuRegisters);
/* Check if eXtended Physical Addressing (XPA) is enabled and if LA57 is supported by the CPU */
if((CpuRegisters.Ecx & CPUID_FEATURES_ECX_LA57) &&
!(XtLdrProtocol->BootUtil.GetBooleanParameter(Parameters, L"NOXPA")))
{
/* Enable LA57 (PML5) */
return 5;
}
// TODO: Uncomment the following code when LA57 support is implemented in the bootloader
// /* Check if eXtended Physical Addressing (XPA) is enabled and if LA57 is supported by the CPU */
// if((CpuRegisters.Ecx & CPUID_FEATURES_ECX_LA57) &&
// !(XtLdrProtocol->BootUtil.GetBooleanParameter(Parameters, L"NOXPA")))
// {
// /* Enable LA57 (PML5) */
// return 4;
// }
}
/* Disable LA57 and use PML4 by default */