xtoskrnl/includes/amd64/mmi.h

@@ -22,6 +22,10 @@ VOID
 MmZeroPages(IN PVOID Address,
             IN ULONG Size);
 
+XTAPI
+VOID
+MmpClearPte(PHARDWARE_PTE PtePointer);
+
 XTAPI
 BOOLEAN
 MmpGetExtendedPhysicalAddressingStatus(VOID);
@@ -50,4 +54,20 @@ XTAPI
 VOID
 MmpInitializeArchitecture(VOID);
 
+XTAPI
+BOOLEAN
+MmpPteValid(PHARDWARE_PTE PtePointer);
+
+XTAPI
+VOID
+MmpSetPte(PHARDWARE_PTE PtePointer,
+          PFN_NUMBER PageFrameNumber,
+          BOOLEAN Writable);
+
+XTAPI
+VOID
+MmpSetPteCaching(PHARDWARE_PTE PtePointer,
+                 BOOLEAN CacheDisable,
+                 BOOLEAN WriteThrough);
+
 #endif /* __XTOSKRNL_AMD64_MMI_H */

xtoskrnl/mm/amd64/globals.c

@@ -11,16 +11,16 @@
 
 /* Page mapping routines for systems using 4-level paging (PML4) */
 CMMPAGEMAP_ROUTINES MmpPml4Routines = {
-    // .ClearPte = MmpClearPte,
+    .ClearPte = MmpClearPte,
-    // .PteValid = MmpPml2PteValid,
+    .PteValid = MmpPteValid,
-    // .SetPteCaching = MmpSetPml2PteCaching,
+    .SetPteCaching = MmpSetPteCaching,
-    // .SetPte = MmpSetPml2Pte,
+    .SetPte = MmpSetPte,
 };
 
 /* Page mapping routines for systems using 5-level paging (PML5) */
 CMMPAGEMAP_ROUTINES MmpPml5Routines = {
-    // .ClearPte = MmpClearPte,
+    .ClearPte = MmpClearPte,
-    // .PteValid = MmpPml3PteValid,
+    .PteValid = MmpPteValid,
-    // .SetPteCaching = MmpSetPml3PteCaching,
+    .SetPteCaching = MmpSetPteCaching,
-    // .SetPte = MmpSetPml3Pte,
+    .SetPte = MmpSetPte,
 };

xtoskrnl/mm/amd64/pmap.c

@@ -9,6 +9,27 @@
 #include <xtos.h>
 
 
+/**
+ * Clears the contents of a page table entry (PTE).
+ *
+ * @param PtePointer
+ *        Pointer to the page table entry (PTE) to be cleared.
+ *
+ * @return This routine does not return any value.
+ *
+ * @since XT 1.0
+ */
+XTAPI
+VOID
+MmpClearPte(PHARDWARE_PTE PtePointer)
+{
+    PtePointer->CacheDisable = 0;
+    PtePointer->PageFrameNumber = 0;
+    PtePointer->Valid = 0;
+    PtePointer->Writable = 0;
+    PtePointer->WriteThrough = 0;
+}
+
 /**
  * Checks if eXtended Physical Addressing (XPA) is enabled.
  *
@@ -123,3 +144,47 @@ MmpGetPxeAddress(PVOID Address)
     Offset = (((ULONGLONG)Address >> MM_PXI_SHIFT) << MM_PTE_SHIFT);
     return (PMMPXE)(MmpPageMapInfo.PxeBase + Offset);
 }
+
+/**
+ * Checks whether the given page table entry (PTE) is valid.
+ *
+ * @param PtePointer
+ *        Pointer to the page table entry (PTE) to check.
+ *
+ * @return Returns TRUE if the entry is valid, FALSE otherwise.
+ *
+ * @since XT 1.0
+ */
+XTAPI
+BOOLEAN
+MmpPteValid(PHARDWARE_PTE PtePointer)
+{
+    return (BOOLEAN)PtePointer->Valid;
+}
+
+/**
+ * Sets a page table entry (PTE) with the specified physical page and access flags.
+ *
+ * @param PtePointer
+ *        Pointer to the page table entry (PTE) to set.
+ *
+ * @param PageFrameNumber
+ *        Physical frame number to map.
+ *
+ * @param Writable
+ *        Indicates whether the page should be writable.
+ *
+ * @return This routine does not return any value.
+ *
+ * @since XT 1.0
+ */
+XTAPI
+VOID
+MmpSetPte(PHARDWARE_PTE PtePointer,
+          PFN_NUMBER PageFrameNumber,
+          BOOLEAN Writable)
+{
+    PtePointer->PageFrameNumber = PageFrameNumber;
+    PtePointer->Valid = 1;
+    PtePointer->Writable = Writable;
+}