Add CPU features and fix CPU vendor #2
@@ -190,81 +190,89 @@ typedef enum _CPUID_FEATURES
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} CPUID_FEATURES, *PCPUID_FEATURES;
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} CPUID_FEATURES, *PCPUID_FEATURES;
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Ghost marked this conversation as resolved
Outdated
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/* CPU features, as reported by CPUID instruction */
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/* CPU features, as reported by CPUID instruction */
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typedef struct _CPU_FEATURES {
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typedef union _CPU_FEATURES
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union {
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{
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struct {
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UINT64 Value;
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BOOLEAN SSE3 : 1;
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union
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belliash
commented
It is not guaranteed that enum has unsigned underlying type. It is not guaranteed that enum has unsigned underlying type.
Ghost
commented
You pointed the struct in this case, was this a mis-comment? You pointed the struct in this case, was this a mis-comment?
belliash
commented
No, it's not a mistake. BOOLEAN is defined as enum. No, it's not a mistake. BOOLEAN is defined as enum.
Ghost
commented
May we define May we define `BOOLEAN as enum : BYTE`?
https://learn.microsoft.com/en-us/windows/win32/winprog/windows-data-types
Ghost
commented
Swapped all BOOLEAN on the structure with BYTE Swapped all BOOLEAN on the structure with BYTE
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BOOLEAN PCLMUL : 1;
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{
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BOOLEAN DTES64 : 1;
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UINT32 Ecx;
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BOOLEAN MONITOR : 1;
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UINT32 ExtendedFeatures;
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BOOLEAN DS_CPL : 1;
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struct
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BOOLEAN VMX : 1;
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{
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BOOLEAN SMX : 1;
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BYTE SSE3 : 1;
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BOOLEAN EST : 1;
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BYTE PCLMUL : 1;
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BOOLEAN TM2 : 1;
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BYTE DTES64 : 1;
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BOOLEAN SSSE3 : 1;
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BYTE MONITOR : 1;
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BOOLEAN CID : 1;
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BYTE DS_CPL : 1;
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BOOLEAN SDBG : 1;
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BYTE VMX : 1;
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BOOLEAN FMA : 1;
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BYTE SMX : 1;
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BOOLEAN CX16 : 1;
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BYTE EST : 1;
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BOOLEAN XTPR : 1;
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BYTE TM2 : 1;
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BOOLEAN PDCM : 1;
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BYTE SSSE3 : 1;
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BOOLEAN Reserved1 : 1; // Bit 16 is reserved
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BYTE CID : 1;
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BOOLEAN PCID : 1;
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BYTE SDBG : 1;
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BOOLEAN DCA : 1;
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BYTE FMA : 1;
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BOOLEAN SSE4_1 : 1;
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BYTE CX16 : 1;
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BOOLEAN SSE4_2 : 1;
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BYTE XTPR : 1;
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BOOLEAN X2APIC : 1;
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BYTE PDCM : 1;
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BOOLEAN MOVBE : 1;
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BYTE Reserved4 : 1; // Bit 16 is reserved
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BOOLEAN POPCNT : 1;
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BYTE PCID : 1;
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BOOLEAN TSC_DEADLINE : 1;
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BYTE DCA : 1;
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BOOLEAN AES : 1;
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BYTE SSE4_1 : 1;
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BOOLEAN XSAVE : 1;
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BYTE SSE4_2 : 1;
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BOOLEAN OSXSAVE : 1;
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BYTE X2APIC : 1;
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BOOLEAN AVX : 1;
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BYTE MOVBE : 1;
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BOOLEAN F16C : 1;
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BYTE POPCNT : 1;
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BOOLEAN RDRAND : 1;
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BYTE TSC_DEADLINE : 1;
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BOOLEAN HYPERVISOR : 1;
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BYTE AES : 1;
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BYTE XSAVE : 1;
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BYTE OSXSAVE : 1;
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BYTE AVX : 1;
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BYTE F16C : 1;
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BYTE RDRAND : 1;
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BYTE HYPERVISOR : 1;
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};
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};
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};
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UINT32 ExtendedFeatures;
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union
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};
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{
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union {
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UINT32 Edx;
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struct {
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UINT32 Features;
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BOOLEAN FPU : 1;
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struct
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BOOLEAN VME : 1;
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{
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BOOLEAN DE : 1;
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BYTE FPU : 1;
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BOOLEAN PSE : 1;
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BYTE VME : 1;
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BOOLEAN TSC : 1;
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BYTE DE : 1;
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BOOLEAN MSR : 1;
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BYTE PSE : 1;
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BOOLEAN PAE : 1;
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BYTE TSC : 1;
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BOOLEAN MCE : 1;
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BYTE MSR : 1;
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BOOLEAN CX8 : 1;
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BYTE PAE : 1;
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BOOLEAN APIC : 1;
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BYTE MCE : 1;
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BOOLEAN Reserved2 : 1; // Bit 10 is reserved
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BYTE CX8 : 1;
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BOOLEAN SEP : 1;
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BYTE APIC : 1;
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BOOLEAN MTRR : 1;
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BYTE Reserved1 : 1; // Bit 10 is reserved
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BOOLEAN PGE : 1;
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BYTE SEP : 1;
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BOOLEAN MCA : 1;
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BYTE MTRR : 1;
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BOOLEAN CMOV : 1;
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BYTE PGE : 1;
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BOOLEAN PAT : 1;
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BYTE MCA : 1;
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BOOLEAN PSE36 : 1;
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BYTE CMOV : 1;
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BOOLEAN PSN : 1;
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BYTE PAT : 1;
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BOOLEAN CLFLUSH : 1;
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BYTE PSE36 : 1;
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BOOLEAN Reserved3 : 1; // Bit 20 is reserved
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BYTE PSN : 1;
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BOOLEAN DS : 1;
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BYTE CLFLUSH : 1;
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BOOLEAN ACPI : 1;
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BYTE Reserved2 : 1; // Bit 20 is reserved
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BOOLEAN MMX : 1;
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BYTE DS : 1;
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BOOLEAN FXSR : 1;
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BYTE ACPI : 1;
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BOOLEAN SSE : 1;
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BYTE MMX : 1;
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BOOLEAN SSE2 : 1;
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BYTE FXSR : 1;
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belliash
commented
Any reason for using UINT64 here? Any reason for using UINT64 here?
Ghost
commented
I've specifically added that to access the whole value AsUINT64, maybe it's unnecesary right now, but added it as a plus. I took some inspiration from this code, that does the same: I've specifically added that to access the whole value AsUINT64, maybe it's unnecesary right now, but added it as a plus. I took some inspiration from this code, that does the same:
xtchain/binaries/x86_64-w64-mingw32/include/winhvplatformdefs.h:29
(look for typedef union WHV_CAPABILITY_FEATURES)
Ghost
commented
Swapped all BOOLEAN on the structure with BYTE Swapped all BOOLEAN on the structure with BYTE
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BOOLEAN SS : 1;
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BYTE SSE : 1;
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BOOLEAN HTT : 1;
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BYTE SSE2 : 1;
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BOOLEAN TM : 1;
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BYTE SS : 1;
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BOOLEAN Reserved4 : 1; // Bit 30 is reserved
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BYTE HTT : 1;
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BOOLEAN PBE : 1;
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BYTE TM : 1;
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BYTE Reserved3 : 1; // Bit 30 is reserved
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BYTE PBE : 1;
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};
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};
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};
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UINT64 Features;
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};
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} CPU_FEATURES, *PCPU_FEATURES;
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} CPU_FEATURES, *PCPU_FEATURES;
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/* CPUID requests */
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/* CPUID requests */
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@@ -141,76 +141,89 @@ typedef enum _CPUID_FEATURES
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} CPUID_FEATURES, *PCPUID_FEATURES;
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} CPUID_FEATURES, *PCPUID_FEATURES;
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Ghost marked this conversation as resolved
Outdated
belliash
commented
UINT, or maybe something smaller if just one bit used. UINT, or maybe something smaller if just one bit used.
Ghost
commented
Using BYTE instead of unsigned int for the bitfield Using BYTE instead of unsigned int for the bitfield
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/* CPU features, as reported by CPUID instruction */
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/* CPU features, as reported by CPUID instruction */
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typedef struct _CPU_FEATURES {
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typedef union _CPU_FEATURES
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union {
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{
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struct {
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UINT64 Value;
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BOOLEAN SSE3 : 1;
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union
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belliash
commented
It is not guaranteed that enum has unsigned underlying type. It is not guaranteed that enum has unsigned underlying type.
Ghost
commented
You pointed the struct in this case, was this a mis-comment? You pointed the struct in this case, was this a mis-comment?
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BOOLEAN PCLMUL : 1;
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{
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BOOLEAN DTES64 : 1;
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UINT32 Ecx;
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BOOLEAN MONITOR : 1;
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UINT32 ExtendedFeatures;
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BOOLEAN DS_CPL : 1;
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struct
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BOOLEAN VMX : 1;
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{
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BOOLEAN SMX : 1;
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BYTE SSE3 : 1;
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BOOLEAN EST : 1;
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BYTE PCLMUL : 1;
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BOOLEAN TM2 : 1;
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BYTE DTES64 : 1;
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BOOLEAN SSSE3 : 1;
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BYTE MONITOR : 1;
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BOOLEAN CID : 1;
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BYTE DS_CPL : 1;
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BOOLEAN SDBG : 1;
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BYTE VMX : 1;
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BOOLEAN FMA : 1;
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BYTE SMX : 1;
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BOOLEAN CX16 : 1;
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BYTE EST : 1;
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BOOLEAN XTPR : 1;
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BYTE TM2 : 1;
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BOOLEAN PDCM : 1;
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BYTE SSSE3 : 1;
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BOOLEAN Reserved1 : 1; // Bit 16 is reserved
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BYTE CID : 1;
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BOOLEAN PCID : 1;
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BYTE SDBG : 1;
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BOOLEAN DCA : 1;
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BYTE FMA : 1;
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BOOLEAN SSE4_1 : 1;
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BYTE CX16 : 1;
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BOOLEAN SSE4_2 : 1;
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BYTE XTPR : 1;
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BOOLEAN X2APIC : 1;
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BYTE PDCM : 1;
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BOOLEAN MOVBE : 1;
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BYTE Reserved1 : 1; // Bit 16 is reserved
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BOOLEAN POPCNT : 1;
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BYTE PCID : 1;
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BOOLEAN TSC_DEADLINE : 1;
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BYTE DCA : 1;
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BOOLEAN AES : 1;
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BYTE SSE4_1 : 1;
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BOOLEAN XSAVE : 1;
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BYTE SSE4_2 : 1;
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BOOLEAN OSXSAVE : 1;
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BYTE X2APIC : 1;
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BOOLEAN AVX : 1;
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BYTE MOVBE : 1;
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BOOLEAN F16C : 1;
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BYTE POPCNT : 1;
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BOOLEAN RDRAND : 1;
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BYTE TSC_DEADLINE : 1;
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BOOLEAN HYPERVISOR : 1;
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BYTE AES : 1;
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BOOLEAN FPU : 1;
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BYTE XSAVE : 1;
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BOOLEAN VME : 1;
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BYTE OSXSAVE : 1;
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BOOLEAN DE : 1;
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BYTE AVX : 1;
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BOOLEAN PSE : 1;
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BYTE F16C : 1;
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BOOLEAN TSC : 1;
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BYTE RDRAND : 1;
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BOOLEAN MSR : 1;
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BYTE HYPERVISOR : 1;
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BOOLEAN PAE : 1;
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};
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BOOLEAN MCE : 1;
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};
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BOOLEAN CX8 : 1;
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union
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BOOLEAN APIC : 1;
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{
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BOOLEAN Reserved2 : 1; // Bit 10 is reserved
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UINT32 Edx;
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BOOLEAN SEP : 1;
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UINT32 Features;
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BOOLEAN MTRR : 1;
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struct
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BOOLEAN PGE : 1;
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{
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BOOLEAN MCA : 1;
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BYTE FPU : 1;
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BOOLEAN CMOV : 1;
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BYTE VME : 1;
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BOOLEAN PAT : 1;
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BYTE DE : 1;
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BOOLEAN PSE36 : 1;
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BYTE PSE : 1;
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BOOLEAN PSN : 1;
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BYTE TSC : 1;
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BOOLEAN CLFLUSH : 1;
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BYTE MSR : 1;
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BOOLEAN Reserved3 : 1; // Bit 20 is reserved
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BYTE PAE : 1;
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BOOLEAN DS : 1;
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BYTE MCE : 1;
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BOOLEAN ACPI : 1;
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BYTE CX8 : 1;
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BOOLEAN MMX : 1;
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BYTE APIC : 1;
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BOOLEAN FXSR : 1;
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BYTE Reserved2 : 1; // Bit 10 is reserved
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BOOLEAN SSE : 1;
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BYTE SEP : 1;
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BOOLEAN SSE2 : 1;
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BYTE MTRR : 1;
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BOOLEAN SS : 1;
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BYTE PGE : 1;
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BOOLEAN HTT : 1;
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BYTE MCA : 1;
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BOOLEAN TM : 1;
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BYTE CMOV : 1;
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BOOLEAN Reserved4 : 1; // Bit 30 is reserved
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BYTE PAT : 1;
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BOOLEAN PBE : 1;
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BYTE PSE36 : 1;
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BYTE PSN : 1;
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BYTE CLFLUSH : 1;
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belliash
commented
Any reason for using UINT64 here? Any reason for using UINT64 here?
Ghost
commented
I've specifically added that to access the whole value I've specifically added that to access the whole value `AsUINT64`, maybe it's unnecesary right now, but added it as a plus. I took some inspiration from this code, that does the same:
xtchain/binaries/x86_64-w64-mingw32/include/winhvplatformdefs.h:29
(look for `typedef union WHV_CAPABILITY_FEATURES`)
belliash
commented
I didn't notice the difference between i686 and amd64. In one case it is a structure containing 2 unions. Here we got 1 bit structure. Does it mean, that CPUID returns different data across archs? I didn't notice the difference between i686 and amd64. In one case it is a structure containing 2 unions. Here we got 1 bit structure. Does it mean, that CPUID returns different data across archs?
Ghost
commented
This is a small regression on local commits, I'll push the final structure. This is a small regression on local commits, I'll push the final structure.
Ghost
commented
Fixed on last commit. Fixed on last commit.
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BYTE Reserved3 : 1; // Bit 20 is reserved
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BYTE DS : 1;
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BYTE ACPI : 1;
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BYTE MMX : 1;
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BYTE FXSR : 1;
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BYTE SSE : 1;
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BYTE SSE2 : 1;
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BYTE SS : 1;
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BYTE HTT : 1;
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BYTE TM : 1;
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BYTE Reserved4 : 1; // Bit 30 is reserved
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BYTE PBE : 1;
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};
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};
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};
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UINT64 AsUINT64;
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};
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} CPU_FEATURES, *PCPU_FEATURES;
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} CPU_FEATURES, *PCPU_FEATURES;
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Ghost marked this conversation as resolved
Outdated
belliash
commented
IMHO this should go to PROCESSOR_CONTROL_BLOCK. IMHO this should go to PROCESSOR_CONTROL_BLOCK.
Ghost
commented
Moved to PROCESSOR_CONTROL_BLOCK Moved to PROCESSOR_CONTROL_BLOCK
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/* CPUID requests */
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/* CPUID requests */
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UINT, or maybe something smaller if just one bit used.
Using BYTE instead of unsigned int for the bitfield