277 lines
7.7 KiB
C
277 lines
7.7 KiB
C
/**
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* PROJECT: ExectOS
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* COPYRIGHT: See COPYING.md in the top level directory
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* FILE: sdk/xtdk/amd64/mmtypes.h
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* DESCRIPTION: Memory management data structures for AMD64 architecture
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* DEVELOPERS: Rafal Kupiec <belliash@codingworkshop.eu.org>
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*/
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#ifndef __XTDK_AMD64_MMTYPES_H
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#define __XTDK_AMD64_MMTYPES_H
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#include <xtbase.h>
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#include <mmtypes.h>
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/* Pages related definitions */
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#define MM_PAGE_MASK (MM_PAGE_SIZE - 1)
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#define MM_PAGE_SHIFT 12L
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#define MM_PAGE_SIZE 4096
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/* Page directory and page base addresses for 4-level paging */
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#define MM_PTE_BASE 0xFFFFF68000000000ULL
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#define MM_PDE_BASE 0xFFFFF6FB40000000ULL
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#define MM_PPE_BASE 0xFFFFF6FB7DA00000ULL
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#define MM_PXE_BASE 0xFFFFF6FB7DBED000ULL
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/* Page directory and page base addresses for 5-level paging */
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#define MM_PTE_LA57_BASE 0xFFFF000000000000ULL
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#define MM_PDE_LA57_BASE 0xFFFF010000000000ULL
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#define MM_PPE_LA57_BASE 0xFFFF010800000000ULL
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#define MM_PXE_LA57_BASE 0xFFFF010840000000ULL
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#define MM_P5E_LA57_BASE 0xFFFF010840200000ULL
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/* PTE shift values */
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#define MM_PTE_SHIFT 3
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#define MM_PTI_SHIFT 12
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#define MM_PDI_SHIFT 21
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#define MM_PPI_SHIFT 30
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#define MM_PXI_SHIFT 39
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#define MM_P5I_SHIFT 48
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/* Number of PTEs per page */
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#define MM_PTE_PER_PAGE 512
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#define MM_PDE_PER_PAGE 512
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#define MM_PPE_PER_PAGE 512
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#define MM_PXE_PER_PAGE 512
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/* Minimum number of physical pages needed by the system */
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#define MM_MINIMUM_PHYSICAL_PAGES 2048
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/* Default number of secondary colors */
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#define MM_DEFAULT_SECONDARY_COLORS 64
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/* Number of HAL allocation descriptors */
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#define MM_HARDWARE_ALLOCATION_DESCRIPTORS 64
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/* Kernel HAL heap initial start address */
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#define MM_HARDWARE_HEAP_START_ADDRESS ((PVOID)(((ULONG_PTR)MM_HARDWARE_VA_START) + 1024 * 1024))
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/* HAL memory pool virtual address start */
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#define MM_HARDWARE_VA_START 0xFFFFFFFFFFC00000ULL
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/* Maximum physical address used by HAL allocations */
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#define MM_MAXIMUM_PHYSICAL_ADDRESS 0x00000000FFFFFFFFULL
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/* Trampoline code address */
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#define MM_TRAMPOLINE_ADDRESS 0x80000
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/* Page size enumeration list */
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typedef enum _PAGE_SIZE
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{
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Size4K,
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Size2M,
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Size1G
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} PAGE_SIZE, *PPAGE_SIZE;
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/* Page Table Entry structure definition */
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typedef struct _HARDWARE_PTE
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{
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ULONGLONG Valid:1;
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ULONGLONG Writable:1;
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ULONGLONG Owner:1;
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ULONGLONG WriteThrough:1;
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ULONGLONG CacheDisable:1;
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ULONGLONG Accessed:1;
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ULONGLONG Dirty:1;
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ULONGLONG LargePage:1;
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ULONGLONG Global:1;
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ULONGLONG CopyOnWrite:1;
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ULONGLONG Prototype:1;
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ULONGLONG Reserved1:1;
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ULONGLONG PageFrameNumber:36;
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ULONGLONG Reserved2:4;
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ULONGLONG SoftwareWsIndex:11;
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ULONGLONG NoExecute:1;
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} HARDWARE_PTE, *PHARDWARE_PTE;
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/* Page map information structure definition */
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typedef struct _MMPAGEMAP_INFO
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{
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BOOLEAN Xpa;
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ULONGLONG PteBase;
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ULONGLONG PdeBase;
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ULONGLONG PpeBase;
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ULONGLONG PxeBase;
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ULONGLONG P5eBase;
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ULONG VaBits;
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} MMPAGEMAP_INFO, *PMMPAGEMAP_INFO;
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/* A Page Table Entry on AMD64 system */
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typedef struct _MMPTE_HARDWARE
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{
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ULONGLONG Valid:1;
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ULONGLONG Writable:1;
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ULONGLONG Owner:1;
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ULONGLONG WriteThrough:1;
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ULONGLONG CacheDisable:1;
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ULONGLONG Accessed:1;
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ULONGLONG Dirty:1;
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ULONGLONG LargePage:1;
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ULONGLONG Global:1;
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ULONGLONG CopyOnWrite:1;
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ULONGLONG Prototype:1;
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ULONGLONG Write:1;
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ULONGLONG PageFrameNumber:36;
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ULONGLONG Reserved1:2;
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ULONGLONG SoftwareWsIndex:11;
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ULONGLONG NoExecute:1;
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} MMPTE_HARDWARE, *PMMPTE_HARDWARE;
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/* A Page Table Entry on AMD64 system with large pages */
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typedef struct _MMPTE_HARDWARE_LARGEPAGE
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{
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ULONGLONG Valid:1;
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ULONGLONG Write:1;
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ULONGLONG Owner:1;
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ULONGLONG WriteThrough:1;
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ULONGLONG CacheDisable:1;
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ULONGLONG Accessed:1;
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ULONGLONG Dirty:1;
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ULONGLONG LargePage:1;
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ULONGLONG Global:1;
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ULONGLONG CopyOnWrite:1;
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ULONGLONG Prototype:1;
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ULONGLONG Reserved1:1;
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ULONGLONG PAT:1;
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ULONGLONG Reserved2:8;
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ULONGLONG PageFrameNumber:19;
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ULONGLONG Reserved3:24;
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} MMPTE_HARDWARE_LARGEPAGE, *PMMPTE_HARDWARE_LARGEPAGE;
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/* Page Table Entry list structure definition */
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typedef struct _MMPTE_LIST
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{
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ULONGLONG Valid:1;
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ULONGLONG OneEntry:1;
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ULONGLONG Reserved1:3;
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ULONGLONG Protection:5;
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ULONGLONG Prototype:1;
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ULONGLONG Transition:1;
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ULONGLONG Reserved2:20;
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ULONGLONG NextEntry:32;
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} MMPTE_LIST, *PMMPTE_LIST;
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/* Page Table Entry prototype structure definition */
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typedef struct _MMPTE_PROTOTYPE
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{
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ULONGLONG Valid:1;
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ULONGLONG Reserved1:7;
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ULONGLONG ReadOnly:1;
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ULONGLONG Reserved2:1;
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ULONGLONG Prototype:1;
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ULONGLONG Protection:5;
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LONGLONG ProtoAddress:48;
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} MMPTE_PROTOTYPE, *PMMPTE_PROTOTYPE;
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/* Software Page Table Entry structure definition */
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typedef struct _MMPTE_SOFTWARE
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{
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ULONGLONG Valid:1;
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ULONGLONG PageFileLow:4;
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ULONGLONG Protection:5;
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ULONGLONG Prototype:1;
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ULONGLONG Transition:1;
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ULONGLONG UsedPageTableEntries:10;
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ULONGLONG Reserved:10;
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ULONGLONG PageFileHigh:32;
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} MMPTE_SOFTWARE, *PMMPTE_SOFTWARE;
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/* Page Table Entry subsection structure definition */
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typedef struct _MMPTE_SUBSECTION
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{
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ULONGLONG Valid:1;
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ULONGLONG Reserved1:4;
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ULONGLONG Protection:5;
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ULONGLONG Prototype:1;
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ULONGLONG Reserved2:5;
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LONGLONG SubsectionAddress:48;
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} MMPTE_SUBSECTION, *PMMPTE_SUBSECTION;
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/* Page Table Entry transition structure definition */
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typedef struct _MMPTE_TRANSITION
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{
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ULONGLONG Valid:1;
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ULONGLONG Write:1;
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ULONGLONG Owner:1;
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ULONGLONG WriteThrough:1;
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ULONGLONG CacheDisable:1;
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ULONGLONG Protection:5;
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ULONGLONG Prototype:1;
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ULONGLONG Transition:1;
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ULONGLONG PageFrameNumber:36;
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ULONGLONG Unused:16;
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} MMPTE_TRANSITION, *PMMPTE_TRANSITION;
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/* Page Table Entry structure definition */
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typedef union _MMPTE
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{
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ULONGLONG Long;
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HARDWARE_PTE Flush;
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MMPTE_HARDWARE Hardware;
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MMPTE_PROTOTYPE Prototype;
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MMPTE_SOFTWARE Software;
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MMPTE_TRANSITION Transition;
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MMPTE_SUBSECTION Subsection;
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MMPTE_LIST List;
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} MMPTE, *PMMPTE;
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/* Page Frame Number structure definition */
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typedef struct _MMPFN
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{
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union
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{
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PFN_NUMBER Flink;
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ULONG WsIndex;
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PKEVENT Event;
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XTSTATUS ReadStatus;
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SINGLE_LIST_ENTRY NextStackPfn;
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} u1;
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PMMPTE PteAddress;
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union
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{
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PFN_NUMBER Blink;
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ULONG_PTR ShareCount;
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} u2;
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union
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{
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MMPFNENTRY e1;
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struct
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{
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USHORT ShortFlags;
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USHORT ReferenceCount;
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} e2;
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} u3;
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union
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{
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MMPTE OriginalPte;
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LONG AweReferenceCount;
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};
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union
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{
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ULONG_PTR EntireFrame;
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struct
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{
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ULONG_PTR PteFrame:58;
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ULONG_PTR InPageError:1;
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ULONG_PTR VerifierAllocation:1;
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ULONG_PTR AweAllocation:1;
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ULONG_PTR LockCharged:1;
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ULONG_PTR KernelStack:1;
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ULONG_PTR MustBeCached:1;
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};
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} u4;
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} MMPFN, *PMMPFN;
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#endif /* __XTDK_AMD64_MMTYPES_H */
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