58 Commits

Author	SHA1	Message	Date
Aiken Harris	c4a7df6f38	Extract trampoline code into a separate file	2025-08-20 20:20:35 +02:00
Aiken Harris	2468d80078	Add trampoline to enable 5-level paging	2025-08-20 00:20:10 +02:00
Aiken Harris	e8771dfc5b	Use __asm__ to comply with disabled GNU extensions	2025-08-15 00:32:56 +02:00
Aiken Harris	2ea306097d	Resolve compilation errors due to renamed CPUID requests	2025-08-10 17:10:01 +02:00
Aiken Harris	ff41b0d4f7	Fix incorrect TSS descriptor limit according to architecture specification	2025-07-28 18:25:47 +02:00
Rafal Kupiec	740df726e9	Implement ArInterruptsEnabled() routine	2024-05-17 23:19:25 +02:00
Rafal Kupiec	5591e1b377	Fix ArGetCpuFlags() routine	2024-05-17 23:16:16 +02:00
Rafal Kupiec	9f1a4f0ced	Compose the AMD family and model IDs according to the AMD CPUID manual, section 2	2024-05-14 19:39:07 +02:00
Rafal Kupiec	2a8cc7397e	Implement ArGetCpuFlags() routine	2024-05-14 16:26:02 +02:00
Rafal Kupiec	38b0b2ac7d	Use correct stack when using preallocated processor structures	2024-05-08 15:57:24 +02:00
Rafal Kupiec	3c3a756771	Allow to initialize CPU with allocated processor structures	2024-05-08 00:02:47 +02:00
Rafal Kupiec	2c384d780f	Fix storing CPU vendor name in PRCB	2024-05-06 20:01:19 +02:00
Rafal Kupiec	cf0d23b6fe	Correct a typo causing page fault during int handling after switching to new kernel stack	2024-05-06 16:47:12 +02:00
Rafal Kupiec	22693a48d3	Rework trap handling assembly code	2024-04-23 15:07:08 +02:00
Rafal Kupiec	3aa0413756	Use common routine to set runlevel	2024-04-19 23:52:21 +02:00
Rafal Kupiec	28c89986fb	Tweaks to AMD64 architecture support	2024-04-19 23:37:39 +02:00
Rafal Kupiec	92ee74b494	Rework trap handling to access registers	2024-04-19 16:52:37 +02:00
Rafal Kupiec	cf408519ad	Initialize AMD64 segments properly	2024-04-17 20:02:27 +02:00
Rafal Kupiec	7011d456e9	Fix loading CS segment for AMD64 architecture	2024-04-17 16:48:18 +02:00
Rafal Kupiec	4b2d8ded72	No parameters are expected, explicitly	2024-02-20 16:55:12 +01:00
Rafal Kupiec	7727888087	Implement ArFlushTlb() routine	2024-02-04 23:43:38 +01:00
Rafal Kupiec	9ce841e957	Implement memory barriers	2024-02-04 22:10:37 +01:00
Rafal Kupiec	d17b06a180	Register interrupt handlers once the APIC initialization is done	2023-11-28 14:20:23 +01:00
Rafal Kupiec	ba6e68e1b5	Fix a bug that caused overwritting a value read from CR8 with a default value	2023-11-26 00:33:46 +01:00
Rafal Kupiec	55cc62f5a0	Rename KIRQL to KRUNLEVEL type	2023-11-25 00:32:55 +01:00
belliash	71d0608643	Implement ArGetStackPointer() routine	2023-11-19 00:09:16 +01:00
belliash	ccd0514416	Implement more CPU-related routines	2023-11-15 14:52:18 +01:00
belliash	c5a9253ea8	Implement ArLoadLocalDescriptorTable() routine	2023-03-02 23:04:36 +01:00
belliash	dfae0b4727	Implement ArSetGdtEntryBase() routine	2023-03-02 22:51:57 +01:00
belliash	e41de62dab	Implement ArYieldProcessor() routine	2023-02-27 17:28:20 +01:00
belliash	d427ca20fb	Always include xtos.h in kernel sources	2023-02-20 00:21:52 +01:00
belliash	d72002187d	Partially implement ArpIdentifyProcessor()	2023-02-10 17:23:47 +01:00
belliash	e645cf664c	Set process and thread information in processor control block	2023-02-09 17:30:24 +01:00
belliash	47f399e987	Set current process and thread in processor control block	2023-02-09 00:02:45 +01:00
belliash	75c519a70c	Use more generic name for this macro use pointer used behind it will point to kernel debugger after it gets initialized	2023-02-07 19:37:44 +01:00
belliash	67768ae7a3	Mark ArpIdentifyProcessor() as unimplemented	2023-02-06 16:15:24 +01:00
belliash	385f0e6de0	Not all AMD64 CPUs support large pages and global pages, unfortunately	2023-02-05 22:14:47 +01:00
belliash	911903d0eb	Add missing routine description	2023-02-05 10:08:49 +01:00
belliash	d6aac59199	Let kernel initialize stack on it's own without relying on boot loader	2023-02-05 09:55:59 +01:00
belliash	0b743a5f26	Add stub routine for identifying processor	2023-02-05 00:42:30 +01:00
belliash	c6cadbd655	Initialize MXCSR register	2023-02-05 00:30:12 +01:00
belliash	5eaf7d63a3	Initialize Page Attribute Table	2023-02-05 00:14:34 +01:00
belliash	55cdae7c83	Initialize AMD64 processor registers	2023-02-04 23:40:03 +01:00
belliash	f181215341	Initialize segment registers	2023-02-04 00:17:07 +01:00
belliash	b90f37dad4	Fill in Interrupt Descriptor Table (IDT)	2023-02-03 18:40:10 +01:00
belliash	269214ed34	Another improvements to GDT	2023-02-03 18:00:37 +01:00
belliash	a49d0804ce	Add trap handlers for both i686 and amd64	2023-02-02 23:31:32 +01:00
belliash	404f2f85c6	Cleanup the Interrupt Stack Table	2023-02-01 23:47:57 +01:00
belliash	7fc1f04cd0	TSS entry is already put into GDT table, just initialize it	2023-02-01 23:37:12 +01:00
belliash	cbd21ced39	Use a size of the structure, not a pointer	2023-02-01 22:38:36 +01:00