Add support for I/O APIC controllers and interrupt override handling

Co-authored-by: Pedro Valadés <perikiyoxd@gmail.com>
Co-committed-by: Pedro Valadés <perikiyoxd@gmail.com>

CMakeLists.txt

@@ -55,6 +55,9 @@ add_definitions(-D__XTOS__)
 add_definitions(-DXTOS_SOURCE_DIR="${EXECTOS_SOURCE_DIR}")
 add_definitions(-DXTOS_BINARY_DIR="${EXECTOS_BINARY_DIR}")
 
+# Add assembler flags
+add_compiler_asmflags(-D__XTOS_ASSEMBLER__)
+
 # Compute __FILE__ definition
 file(RELATIVE_PATH _PATH_PREFIX ${EXECTOS_BINARY_DIR} ${EXECTOS_SOURCE_DIR})
 add_compiler_flags(-D__RELFILE__="&__FILE__[__FILE__[0] == '.' ? sizeof \\\"${_PATH_PREFIX}\\\" - 1 : sizeof XTOS_SOURCE_DIR]")

README.md

@@ -53,8 +53,9 @@ implement any environment subsystem to support applications that are strictly wr
  * NT drivers compatibility layer
 
 # Requirements
-ExectOS is in very early development stage, thus its requirements have been not specified yet. However according to its
-design, it requires a modern EFI enabled hardware. It is not possible currently to boot ExectOS on a legacy BIOS.
+ExectOS is currently in a very early stage of development, so its specific requirements are not fully defined yet.
+However, based on the current design, it requires modern EFI hardware. You cannot boot ExectOS on a legacy BIOS
+right now, but there are plans to add BIOS support in the future.
 
 # Source structure
 | Directory        | Description                                                  |

boot/bootsect/CMakeLists.txt

@@ -1,6 +1,8 @@
 # XT Boot Sector
 PROJECT(BOOTSECT)
 
+add_definitions("-DARCH_ESP_SOURCE=\\\"${ARCH}/cpu.S\\\"")
+
 # Compile boot sectors
 compile_bootsector(mbrboot ${BOOTSECT_SOURCE_DIR}/mbrboot.S 0x7C00 Start)
 compile_bootsector(espboot ${BOOTSECT_SOURCE_DIR}/espboot.S 0x7C00 Start)

boot/bootsect/amd64/cpu.S

@@ -0,0 +1,144 @@
+/**
+ * PROJECT:         ExectOS
+ * COPYRIGHT:       See COPYING.md in the top level directory
+ * FILE:            boot/bootsect/amd64/cpu.S
+ * DESCRIPTION:     Low-level support for CPU initialization
+ * DEVELOPERS:      Aiken Harris <harraiken91@gmail.com>
+ */
+
+
+BuildPageMap:
+    /* Generate page map for first 1GB of memory */
+    pushaw
+    pushw %es
+    cld
+    movw $(0x1000 / 16), %ax
+    movw %ax, %es
+    xorw %di, %di
+    movl $(0x2000 | 0x07), %eax
+    stosl
+    xorl %eax, %eax
+    movw $1021, %cx
+    rep stosl
+    movw $(0x2000 / 16), %ax
+    movw %ax, %es
+    xorw %di, %di
+    movl $(0x3000 | 0x07), %eax
+    stosl
+    xorl %eax, %eax
+    movw $1021, %cx
+    rep stosl
+    movw $(0x3000 / 16), %ax
+    movw %ax, %es
+    xorw %di, %di
+    movw $512, %cx
+    movl $0x00000083, %eax
+.BuildPageMapLoop:
+    /* Identity map 512 pages of 2MB */
+    movl %eax, %es:(%di)
+    addl $2097152, %eax
+    addw $0x08, %di
+    loop .BuildPageMapLoop
+    popw %es
+    popaw
+    ret
+
+InitializeCpu:
+    /* Check if CPU supports CPUID, long mode and PAE */
+    pushal
+    pushfl
+    popl %eax
+    movl %eax, %ebx
+    xorl $0x00200000, %eax
+    pushl %eax
+    popfl
+    pushfl
+    popl %eax
+    cmpl %ebx, %eax
+    je CpuUnsupported
+    movl $0x01, %eax
+    cpuid
+    testl $0x40, %edx
+    jz CpuUnsupported
+    movl $0x80000000, %eax
+    cpuid
+    cmpl $0x80000000, %eax
+    jbe CpuUnsupported
+    movl $0x80000001, %eax
+    cpuid
+    testl $0x20000000, %edx
+    jz CpuUnsupported
+    popal
+    call LoadGdt
+    ret
+
+LoadGdt:
+    /* Load Global Descriptor Table */
+    lgdt .GdtPointer
+    ret
+
+RunStage2:
+    /* Switch to long mode and pass control to Stage 2 */
+    call BuildPageMap
+    call ParseExecutableHeader
+    xorl %edx, %edx
+    pushl %edx
+    pushl %eax
+    cli
+    xorw %ax, %ax
+    movw %ax, %ds
+    movw %ax, %es
+    movw %ax, %fs
+    movw %ax, %gs
+    movw %ax, %ss
+    movl %cr4, %eax
+    orl $0x00A0, %eax
+    movl %eax, %cr4
+    movl $0x00001000, %eax
+    movl %eax, %cr3
+    movl $0xC0000080, %ecx
+    rdmsr
+    orl $0x00000100, %eax
+    wrmsr
+    movl %cr0, %eax
+    orl $0x80000001, %eax
+    movl %eax, %cr0
+    ljmp $0x10, $.Stage2LongMode
+.code64
+.Stage2LongMode:
+    /* Set segments and stack, then jump to Stage 2 */
+    movw $0x18, %ax
+    movw %ax, %ds
+    movw %ax, %es
+    movw %ax, %ss
+    xorw %ax, %ax
+    movw %ax, %fs
+    movw %ax, %gs
+    popq %rax
+    xorq %rbx, %rbx
+    xorq %rcx, %rcx
+    xorq %rdx, %rdx
+    xorq %rsi, %rsi
+    xorq %rdi, %rdi
+    xorq %rbp, %rbp
+    jmp *%rax
+
+.code16
+.GdtDescriptor:
+    /* Global Descriptor Table */
+    .quad 0x0000000000000000
+    .quad 0x0000000000000000
+    .quad 0x00AF9A000000FFFF
+    .quad 0x00CF92000000FFFF
+    .quad 0x00009E000000FFFF
+    .quad 0x000092000000FFFF
+    .quad 0x00CF9B000000FFFF
+
+.GdtPointer:
+    /* Pointer to Global Descriptor Table */
+    .word .GdtPointer - .GdtDescriptor - 1
+    .long .GdtDescriptor
+
+.Stage2FileName:
+    /* Name of Stage 2 executable file */
+    .ascii "BOOTX64 EFI"

boot/bootsect/espboot.S

@@ -121,15 +121,15 @@ VerifyBiosParameterBlock:
     ja FsError
 
 ReadExtraCode:
-    /* Read second VBR sector with extra boot code */
+    /* Read second VBR sector with extra boot code (3 sectors starting from sector 2) */
     movl HiddenSectors - Start(%bp), %eax
     addl $0x02, %eax
-    movw $0x01, %cx
+    movw $0x03, %cx
     xorw %bx, %bx
     movw %bx, %es
     movw $0x7E00, %bx
     call ReadSectors
-    jmp StartSectors
+    jmp StartExtraCode
 
 ReadSectors:
     /* Check for extended BIOS functions and use it only if available */
@@ -139,18 +139,22 @@ ReadSectors:
     movw $0x55AA, %bx
     movb DriveNumber - Start(%bp), %dl
     int $0x13
-    jc ReadCHS
+    jc .ReadCHS
     cmpw $0xAA55, %bx
-    jne ReadCHS
+    jne .ReadCHS
     testb $0x01, %cl
-    jz ReadCHS
+    jz .ReadCHS
 
     /* Verify drive size and determine whether to use CHS or LBA */
     cmpl %edi, %eax
-    jnb ReadLBA
+    jnb .ReadLBA
 
-ReadCHS:
+.ReadCHS:
     /* Read sectors using CHS */
+    popal
+
+.CHSLoop:
+    /* Read sector by sector using CHS */
     pushw %cx
     pushal
     xorl %edx, %edx
@@ -176,11 +180,11 @@ ReadCHS:
     movw %es, %dx
     addw $0x20, %dx
     movw %dx, %es
-    loop ReadCHS
+    loop .CHSLoop
     popw %es
     ret
 
-ReadLBA:
+.ReadLBA:
     /* Prepare DAP packet and read sectors using LBA */
     popal
     pushw %cx
@@ -209,19 +213,19 @@ ReadLBA:
     movw %dx, %es
     popw %bx
     subw %si, %cx
-    jnz ReadLBA
+    jnz .ReadLBA
     popw %es
     ret
 
 DiskError:
     /* Display disk error message and reboot */
-    movw $msgDiskError, %si
+    movw $.MsgDiskError, %si
     call Print
     jmp Reboot
 
 FsError:
     /* Display FS error message and reboot */
-    movw $msgFsError, %si
+    movw $.MsgFsError, %si
     call Print
     jmp Reboot
 
@@ -229,48 +233,297 @@ Print:
     /* Simple routine to print messages */
     lodsb
     orb     %al, %al
-    jz      DonePrint
+    jz      .DonePrint
     movb    $0x0E, %ah
     movw    $0x07, %bx
     int     $0x10
     jmp     Print
-DonePrint:
+.DonePrint:
     retw
 
 Reboot:
     /* Display a message, wait for a key press and reboot */
-    movw $msgAnyKey, %si
+    movw $.MsgAnyKey, %si
     call Print
     xorw %ax, %ax
     int $0x16
     int $0x19
 
-msgAnyKey:
-    .ascii "Press any key to restart\r\n"
+.MsgAnyKey:
+    .ascii "Press any key to restart...\r\n\0"
 
-msgDiskError:
-    .ascii "Disk error\r\n"
+.MsgDiskError:
+    .ascii "Disk error!\r\n\0"
 
-msgFsError:
-    .ascii "File system error\r\n"
+.MsgFsError:
+    .ascii "File system error!\r\n\0"
 
 /* Fill the rest of the VBR with zeros and add VBR signature at the end */
 .fill (510 - (. - Start)), 1, 0
 .word 0xAA55
 
 
-StartSectors:
-    /* Print message */
-    movw $msgUnavailable, %si
+StartExtraCode:
+    /* Load XTLDR file from disk */
+    call LoadStage2
+
+    /* Enable A20 gate */
+    call EnableA20
+
+    /* Call architecture specific initialization code */
+    call InitializeCpu
+
+    /* Jump to Stage2 */
+    call RunStage2
+
+Clear8042:
+    /* Clear 8042 PS/2 buffer */
+    nop
+    nop
+    nop
+    nop
+    inb $0x64, %al
+    cmpb $0xff, %al
+    je .Clear8042_Done
+    testb $0x02, %al
+    jnz Clear8042
+.Clear8042_Done:
+    ret
+
+EnableA20:
+    /* Enable A20 gate */
+    pushaw
+    call Clear8042
+    movb $0xD1, %al
+    outb %al, $0x64
+    call Clear8042
+    movb $0xDF, %al
+    outb %al, $0x60
+    call Clear8042
+    movb $0xFF, %al
+    outb %al, $0x64
+    call Clear8042
+    popaw
+    ret
+
+FindFatEntry:
+    /* Find a file or directory in the FAT table */
+    pushw %bx
+    pushw %cx
+    pushw %dx
+    pushw %si
+    pushw %di
+.FindFatCluster:
+    /* Find FAT32 cluster holding the entry */
+    cmp $0x0FFFFFF8, %eax
+    jae .FindEntryFail
+    pushl %eax
+    movw $0x0200, %bx
+    movw %bx, %es
+    call ReadCluster
+    popl %eax
+    movb SectorsPerCluster - Start(%bp), %cl
+    shlw $0x04, %cx
+    xorw %di, %di
+.FindEntryLoop:
+    /* Find the entry */
+    movb %es:(%di), %al
+    cmpb $0x00, %al
+    je .FindEntryFail
+    cmpb $0xE5, %al
+    je .FindSkipEntry
+    movb %es:0x0B(%di), %ah
+    cmpb $0x0F, %ah
+    je .FindSkipEntry
+    pushw %di
+    pushw %si
+    pushw %cx
+    movw $0x0B, %cx
+    repe cmpsb
+    popw %cx
+    popw %si
+    popw %di
+    jnz .FindSkipEntry
+    movw %es:0x1A(%di), %ax
+    movw %es:0x14(%di), %dx
+    shll $0x10, %edx
+    orl %edx, %eax
+    clc
+    jmp .FindEntryDone
+.FindSkipEntry:
+    /* Skip to the next entry */
+    addw $0x20, %di
+    decw %cx
+    jnz .FindEntryLoop
+    call GetFatEntry
+    jmp .FindFatCluster
+.FindEntryFail:
+    /* Error, file/directory not found */
+    stc
+.FindEntryDone:
+    /* Clean up the stack */
+    popw %di
+    popw %si
+    popw %dx
+    popw %cx
+    popw %bx
+    ret
+
+GetFatEntry:
+    /* Get FAT32 sector and offset from FAT table */
+    shll $0x02, %eax
+    movl %eax, %ecx
+    xorl %edx, %edx
+    movzwl BytesPerSector - Start(%bp), %ebx
+    pushl %ebx
+    divl %ebx
+    movzwl ReservedSectors - Start(%bp), %ebx
+    addl %ebx, %eax
+    movl HiddenSectors - Start(%bp), %ebx
+    addl %ebx, %eax
+    popl %ebx
+    decl %ebx
+    andl %ebx, %ecx
+    movzwl ExtendedFlags - Start(%bp), %ebx
+    andw $0x0F, %bx
+    jz LoadFatSector
+    cmpb FatCopies - Start(%bp), %bl
+    jae FsError
+    pushl %eax
+    movl BigSectorsPerFat - Start(%bp), %eax
+    mull %ebx
+    popl %edx
+    addl %edx, %eax
+
+LoadFatSector:
+    /* Load FAT32 sector from disk */
+    pushl %ecx
+    movw $0x9000, %bx
+    movw %bx, %es
+    cmpl %esi, %eax
+    je .LoadFatSectorDone
+    movl %eax, %esi
+    xorw %bx, %bx
+    movw $0x01, %cx
+    call ReadSectors
+.LoadFatSectorDone:
+    /* Clean up the stack */
+    popl %ecx
+    movl %es:(%ecx), %eax
+    andl $0x0FFFFFFF, %eax
+    ret
+
+LoadStage2:
+    /* Load Stage2 executable, first find file in the path */
+    movl $0xFFFFFFFF, %esi
+    pushl %esi
+    movl 0x7C2C, %eax
+    movw $.EfiDirName, %si
+    call FindFatEntry
+    jc Stage2NotLoaded
+    movw $.BootDirName, %si
+    call FindFatEntry
+    jc Stage2NotLoaded
+    movw $.Stage2FileName, %si
+    call FindFatEntry
+    jc Stage2NotLoaded
+    popl %esi
+    /* Load XTLDR file from disk */
+    cmpl $0x02, %eax
+    jb FileNotFound
+    cmpl $0x0FFFFFF8, %eax
+    jae FileNotFound
+    movw $(0xF800 / 16), %bx
+    movw %bx, %es
+.LoadStage2Loop:
+    /* Load file data from disk */
+    pushl %eax
+    xorw %bx, %bx
+    pushw %es
+    call ReadCluster
+    popw %es
+    xorw %bx, %bx
+    movb SectorsPerCluster - Start(%bp), %bl
+    shlw $0x05, %bx
+    movw %es, %ax
+    addw %bx, %ax
+    movw %ax, %es
+    popl %eax
+    pushw %es
+    call GetFatEntry
+    popw %es
+    cmpl $0x0FFFFFF8, %eax
+    jb .LoadStage2Loop
+    ret
+
+ParseExecutableHeader:
+    /* Parse Stage2 PE/COFF executable header */
+    pushw %es
+    movw $(0xF800 / 16), %ax
+    movw %ax, %es
+    movl %es:60, %eax
+    addl $(4 + 20), %eax
+    movl %es:16(%eax), %eax
+    addl $0xF800, %eax
+    popw %es
+    ret
+
+ReadCluster:
+    /* Read FAT32 cluster from disk */
+    decl %eax
+    decl %eax
+    xorl %edx, %edx
+    movzbl SectorsPerCluster - Start(%bp), %ebx
+    mull %ebx
+    pushl %eax
+    xorl %edx, %edx
+    movzbl FatCopies - Start(%bp), %eax
+    mull BigSectorsPerFat - Start(%bp)
+    movzwl ReservedSectors - Start(%bp), %ebx
+    addl %ebx, %eax
+    addl HiddenSectors - Start(%bp), %eax
+    popl %ebx
+    addl %ebx, %eax
+    xorw %bx, %bx
+    movzbw SectorsPerCluster - Start(%bp), %cx
+    call ReadSectors
+    ret
+
+/* Include architecture specific code */
+.include ARCH_ESP_SOURCE
+
+CpuUnsupported:
+    /* Display CPU unsupported message and reboot */
+    popal
+    movw $.MsgCpuUnsupported, %si
     call Print
+    jmp Reboot
 
-    /* Wait for key press and reboot */
-    xorw %ax, %ax
-    int $0x16
-    int $0x19
+FileNotFound:
+    /* Display XTLDR not found message and reboot */
+    movw $.MsgXtLdrNotFound, %si
+    call Print
+    jmp Reboot
 
-msgUnavailable:
-    .ascii "XTLDR requires EFI-based system!\r\nPress any key to restart\r\n"
+Stage2NotLoaded:
+    /* Clean up the stack and display XTLDR not found message and reboot */
+    popl %esi
+    jmp FileNotFound
 
-/* Fill the rest of the extra VBR with zeros */
-.fill (1024 - (. - Start)), 1, 0
+.BootDirName:
+    /* Boot directory name */
+    .ascii "BOOT       "
+
+.EfiDirName:
+    /* EFI directory name */
+    .ascii "EFI        "
+
+.MsgCpuUnsupported:
+    .ascii "CPU not supported!\r\n\0"
+
+.MsgXtLdrNotFound:
+    .ascii "XTLDR Stage2 not found!\r\n\0"
+
+/* Fill the rest of the extra VBR with zeros and add signature */
+.fill (2043 - (. - Start)), 1, 0
+.ascii "XTLDR"

boot/bootsect/i686/cpu.S

@@ -0,0 +1,124 @@
+/**
+ * PROJECT:         ExectOS
+ * COPYRIGHT:       See COPYING.md in the top level directory
+ * FILE:            boot/bootsect/i686/cpu.S
+ * DESCRIPTION:     Low-level support for CPU initialization
+ * DEVELOPERS:      Aiken Harris <harraiken91@gmail.com>
+ */
+
+
+BuildPageMap:
+    /* Generate page map for first 16MB of memory */
+    pushaw
+    pushw %es
+    cld
+    movw $(0x1000 >> 0x04), %ax
+    movw %ax, %es
+    xorw %di, %di
+    movl $(0x2000 | 0x03), %eax
+    stosl
+    movl $(0x3000 | 0x03), %eax
+    stosl
+    movl $(0x4000 | 0x03), %eax
+    stosl
+    movl $(0x5000 | 0x03), %eax
+    stosl
+    xorl %eax, %eax
+    movw $(1024 - 4), %cx
+    rep stosl
+    movl $0x00000003, %eax
+    movl $4, %edx
+    movw $(0x2000 >> 0x04), %bx
+.BuildPageMapLoop:
+    /* Identity map 1024 pages of 4KB */
+    movw %bx, %es
+    xorw %di, %di
+    pushl %edx
+    movw $1024, %cx
+.FillPageMapTable:
+    /* Fill the page table */
+    movl %eax, %es:(%di)
+    addl $4096, %eax
+    addw $0x04, %di
+    loop .FillPageMapTable
+    popl %edx
+    addw $(0x1000 >> 0x04), %bx
+    decl %edx
+    jnz .BuildPageMapLoop
+    popw %es
+    popaw
+    ret
+
+InitializeCpu:
+    /* Check if CPU supports CPUID */
+    pushal
+    pushfl
+    popl %eax
+    movl %eax, %ebx
+    xorl $0x00200000, %eax
+    pushl %eax
+    popfl
+    pushfl
+    popl %eax
+    cmpl %ebx, %eax
+    je CpuUnsupported
+    popal
+    call LoadGdt
+    ret
+
+LoadGdt:
+    /* Load Global Descriptor Table */
+    lgdt .GdtPointer
+    ret
+
+RunStage2:
+    /* Switch to protected mode and pass control to Stage 2 */
+    call BuildPageMap
+    call ParseExecutableHeader
+    pushl %eax
+    cli
+    movl %cr0, %eax
+    orl $0x01, %eax
+    movl %eax, %cr0
+    ljmp $0x08, $.Stage2ProtectedMode
+.code32
+.Stage2ProtectedMode:
+    /* Set segments and stack, then jump to Stage 2 */
+    movw $0x10, %ax
+    movw %ax, %ds
+    movw %ax, %es
+    movw %ax, %ss
+    xorw %ax, %ax
+    movw %ax, %fs
+    movw %ax, %gs
+    popl %eax
+    xorl %ebx, %ebx
+    xorl %ecx, %ecx
+    xorl %edx, %edx
+    xorl %esi, %esi
+    xorl %edi, %edi
+    xorl %ebp, %ebp
+    movl $0x1000, %ebx
+    movl %ebx, %cr3
+    movl %cr0, %ebx
+    orl $0x80000000, %ebx
+    movl %ebx, %cr0
+    jmp *%eax
+
+.code16
+.GdtDescriptor:
+    /* Global Descriptor Table */
+    .quad 0x0000000000000000
+    .quad 0x00CF9A000000FFFF
+    .quad 0x00CF92000000FFFF
+    .quad 0x00009E000000FFFF
+    .quad 0x000092000000FFFF
+
+.GdtPointer:
+    /* Pointer to Global Descriptor Table */
+    .word .GdtPointer - .GdtDescriptor - 1
+    .long .GdtDescriptor
+
+.Stage2FileName:
+    /* Name of Stage 2 executable file */
+    .ascii "BOOTIA32EFI"

boot/bootsect/mbrboot.S

@@ -4,6 +4,7 @@
  * FILE:            boot/bootsect/amd64/mbrboot.S
  * DESCRIPTION:     XT Boot Loader MBR boot code
  * DEVELOPERS:      Rafal Kupiec <belliash@codingworkshop.eu.org>
+ *                  Aiken Harris <aiken@codingworkshop.eu.org>
  */
 
 .text
@@ -41,7 +42,7 @@ RealStart:
     movw %ax, %ss
 
     /* Print welcome message */
-    leaw msgXtosBoot, %si
+    leaw .MsgXtosBoot, %si
     call Print
 
     /* Get BIOS boot drive and partition table offset */
@@ -90,19 +91,19 @@ PartitionFound:
 
 InvalidSignature:
     /* Invalid signature error */
-    leaw msgInvalidSignature, %si
+    leaw .MsgInvalidSignature, %si
     call Print
     jmp HaltSystem
 
 PartitionNotFound:
     /* Active partition not found error */
-    leaw msgPartitionNotFound, %si
+    leaw .MsgPartitionNotFound, %si
     call Print
     jmp HaltSystem
 
 VbrReadFail:
     /* VBR read failed error */
-    leaw msgVbrReadFail, %si
+    leaw .MsgVbrReadFail, %si
     call Print
     jmp HaltSystem
 
@@ -136,16 +137,16 @@ DonePrint:
     /* Storage for the LBA start */
     .long 0
 
-msgInvalidSignature:
+.MsgInvalidSignature:
     .asciz "Invalid partition signature!"
 
-msgPartitionNotFound:
+.MsgPartitionNotFound:
     .asciz "Bootable partition not found!"
 
-msgVbrReadFail:
+.MsgVbrReadFail:
     .asciz "VBR read failed!"
 
-msgXtosBoot:
+.MsgXtosBoot:
     .asciz "Starting XTOS boot loader...\r\n"
 
 /* Fill the rest of the MBR with zeros and add MBR signature at the end */

boot/xtldr/CMakeLists.txt

@@ -16,6 +16,7 @@ list(APPEND LIBXTLDR_SOURCE
 # Specify list of source code files
 list(APPEND XTLDR_SOURCE
     ${XTLDR_SOURCE_DIR}/arch/${ARCH}/memory.cc
+    ${XTLDR_SOURCE_DIR}/biosutil.cc
     ${XTLDR_SOURCE_DIR}/bootutil.cc
     ${XTLDR_SOURCE_DIR}/config.cc
     ${XTLDR_SOURCE_DIR}/console.cc
@@ -38,6 +39,9 @@ add_executable(xtldr ${XTLDR_SOURCE})
 # Add linker libraries
 target_link_libraries(xtldr libxtos)
 
+# Add linker options
+target_link_options(xtldr PRIVATE /ALIGN:512)
+
 # Set proper binary name and install target
 if(ARCH STREQUAL "i686")
 	set(BINARY_NAME "bootia32")
@@ -49,5 +53,6 @@ set_install_target(xtldr efi/boot)
 
 # Set loader entrypoint and subsystem
 set_entrypoint(xtldr "BlStartXtLoader")
+set_imagebase(xtldr ${BASEADDRESS_XTLDR})
 set_linker_map(xtldr TRUE)
 set_subsystem(xtldr efi_application)

boot/xtldr/arch/amd64/memory.cc

@@ -28,13 +28,12 @@ EFI_STATUS
 Memory::BuildPageMap(IN PXTBL_PAGE_MAPPING PageMap,
                      IN ULONG_PTR SelfMapAddress)
 {
-    PLIST_ENTRY ListEntry, ModulesList, ModulesListEntry;
-    PXTBL_MEMORY_MAPPING Mapping;
+    PLIST_ENTRY ModulesList, ModulesListEntry;
     PXTBL_MODULE_INFO ModuleInfo;
     EFI_PHYSICAL_ADDRESS Address;
-    PVOID LoaderBase;
     ULONGLONG LoaderSize;
     EFI_STATUS Status;
+    PVOID LoaderBase;
 
     /* Allocate pages for the Page Map */
     Status = AllocatePages(AllocateAnyPages, 1, &Address);
@@ -44,6 +43,14 @@ Memory::BuildPageMap(IN PXTBL_PAGE_MAPPING PageMap,
         return Status;
     }
 
+    /* Add new memory mapping for the page map itself */
+    Status = MapVirtualMemory(PageMap, (ULONGLONG)NULLPTR, Address, 1, LoaderMemoryData);
+    if(Status != STATUS_EFI_SUCCESS)
+    {
+        /* Memory mapping failure */
+        return Status;
+    }
+
     /* Assign and zero-fill memory used by page mappings */
     PageMap->PtePointer = (PVOID)(UINT_PTR)Address;
     RTL::Memory::ZeroMemory(PageMap->PtePointer, EFI_PAGE_SIZE);
@@ -57,7 +64,7 @@ Memory::BuildPageMap(IN PXTBL_PAGE_MAPPING PageMap,
     }
 
     /* Map the trampoline code area */
-    Status = MapVirtualMemory(PageMap, (PVOID)MM_TRAMPOLINE_ADDRESS,(PVOID)MM_TRAMPOLINE_ADDRESS,
+    Status = MapVirtualMemory(PageMap, MM_TRAMPOLINE_ADDRESS, MM_TRAMPOLINE_ADDRESS,
                               1, LoaderFirmwareTemporary);
     if(Status != STATUS_EFI_SUCCESS)
     {
@@ -74,7 +81,7 @@ Memory::BuildPageMap(IN PXTBL_PAGE_MAPPING PageMap,
         ModuleInfo = CONTAIN_RECORD(ModulesListEntry, XTBL_MODULE_INFO, Flink);
 
         /* Map module code */
-        Status = MapVirtualMemory(PageMap, ModuleInfo->ModuleBase, ModuleInfo->ModuleBase,
+        Status = MapVirtualMemory(PageMap, (ULONGLONG)ModuleInfo->ModuleBase, (ULONGLONG)ModuleInfo->ModuleBase,
                                   EFI_SIZE_TO_PAGES(ModuleInfo->ModuleSize), LoaderFirmwareTemporary);
 
         /* Check if mapping succeeded */
@@ -95,7 +102,7 @@ Memory::BuildPageMap(IN PXTBL_PAGE_MAPPING PageMap,
     if(LoaderBase && LoaderSize)
     {
         /* Map boot loader code as well */
-        Status = MapVirtualMemory(PageMap, LoaderBase, LoaderBase,
+        Status = MapVirtualMemory(PageMap, (ULONGLONG)LoaderBase, (ULONGLONG)LoaderBase,
                                   EFI_SIZE_TO_PAGES(LoaderSize), LoaderFirmwareTemporary);
         if(Status != STATUS_EFI_SUCCESS)
         {
@@ -109,6 +116,28 @@ Memory::BuildPageMap(IN PXTBL_PAGE_MAPPING PageMap,
         return STATUS_EFI_PROTOCOL_ERROR;
     }
 
+    /* Return success */
+    return STATUS_EFI_SUCCESS;
+}
+
+/**
+ * Iterates through the memory map and physically maps all virtual addresses to page tables.
+ *
+ * @param PageMap
+ *        Supplies a pointer to the page mapping structure.
+ *
+ * @return This routine returns a status code.
+ *
+ * @since XT 1.0
+ */
+XTCDECL
+EFI_STATUS
+Memory::CommitPageMap(IN PXTBL_PAGE_MAPPING PageMap)
+{
+    PXTBL_MEMORY_MAPPING Mapping;
+    PLIST_ENTRY ListEntry;
+    EFI_STATUS Status;
+
     /* Iterate through and map all the mappings*/
     Debug::Print(L"Mapping and dumping EFI memory:\n");
     ListEntry = PageMap->MemoryMap.Flink;
@@ -193,7 +222,7 @@ Memory::GetNextPageTable(IN PXTBL_PAGE_MAPPING PageMap,
         }
 
         /* Add new memory mapping */
-        Status = MapVirtualMemory(PageMap, NULLPTR, (PVOID)(UINT_PTR)Address, 1, LoaderMemoryData);
+        Status = MapVirtualMemory(PageMap, (ULONGLONG)NULLPTR, Address, 1, LoaderMemoryData);
         if(Status != STATUS_EFI_SUCCESS)
         {
             /* Memory mapping failure */
@@ -239,9 +268,9 @@ Memory::GetNextPageTable(IN PXTBL_PAGE_MAPPING PageMap,
 XTCDECL
 EFI_STATUS
 Memory::MapPage(IN PXTBL_PAGE_MAPPING PageMap,
-                IN ULONG_PTR VirtualAddress,
-                IN ULONG_PTR PhysicalAddress,
-                IN ULONG NumberOfPages)
+                IN ULONGLONG VirtualAddress,
+                IN ULONGLONG PhysicalAddress,
+                IN ULONGLONG NumberOfPages)
 {
     PVOID Pml1, Pml2, Pml3, Pml4, Pml5;
     SIZE_T Pml1Entry, Pml2Entry, Pml3Entry, Pml4Entry, Pml5Entry;

boot/xtldr/arch/i686/memory.cc

@@ -25,13 +25,12 @@ EFI_STATUS
 Memory::BuildPageMap(IN PXTBL_PAGE_MAPPING PageMap,
                      IN ULONG_PTR SelfMapAddress)
 {
-    PLIST_ENTRY ListEntry, ModulesList, ModulesListEntry;
     EFI_PHYSICAL_ADDRESS Address, DirectoryAddress;
+    PLIST_ENTRY ModulesList, ModulesListEntry;
     PXTBL_MODULE_INFO ModuleInfo;
-    PXTBL_MEMORY_MAPPING Mapping;
-    PVOID LoaderBase;
     ULONGLONG LoaderSize;
     EFI_STATUS Status;
+    PVOID LoaderBase;
     ULONG Index;
 
     /* Check the page map level to determine which paging structure to create */
@@ -45,6 +44,14 @@ Memory::BuildPageMap(IN PXTBL_PAGE_MAPPING PageMap,
             return Status;
         }
 
+        /* Add new memory mapping for the page map itself */
+        Status = MapVirtualMemory(PageMap, (ULONGLONG)NULLPTR, Address, 1, LoaderMemoryData);
+        if(Status != STATUS_EFI_SUCCESS)
+        {
+            /* Memory mapping failure */
+            return Status;
+        }
+
         /* Assign the allocated page to the page map and zero it out */
         PageMap->PtePointer = (PVOID)(UINT_PTR)Address;
         RTL::Memory::ZeroMemory(PageMap->PtePointer, EFI_PAGE_SIZE);
@@ -57,6 +64,14 @@ Memory::BuildPageMap(IN PXTBL_PAGE_MAPPING PageMap,
             return Status;
         }
 
+        /* Add new memory mapping for the Page Directories (PDs) */
+        Status = MapVirtualMemory(PageMap, (ULONGLONG)NULLPTR, DirectoryAddress, 4, LoaderMemoryData);
+        if(Status != STATUS_EFI_SUCCESS)
+        {
+            /* Memory mapping failure */
+            return Status;
+        }
+
         /* Zero-fill the allocated memory for the Page Directories */
         RTL::Memory::ZeroMemory((PVOID)DirectoryAddress, EFI_PAGE_SIZE * 4);
 
@@ -79,6 +94,14 @@ Memory::BuildPageMap(IN PXTBL_PAGE_MAPPING PageMap,
             return Status;
         }
 
+        /* Add new memory mapping for the page map itself */
+        Status = MapVirtualMemory(PageMap, (ULONGLONG)NULLPTR, Address, 1, LoaderMemoryData);
+        if(Status != STATUS_EFI_SUCCESS)
+        {
+            /* Memory mapping failure */
+            return Status;
+        }
+
         /* Assign the allocated page to the page map and zero it out */
         PageMap->PtePointer = (PVOID)(UINT_PTR)Address;
         RTL::Memory::ZeroMemory(PageMap->PtePointer, EFI_PAGE_SIZE);
@@ -93,8 +116,7 @@ Memory::BuildPageMap(IN PXTBL_PAGE_MAPPING PageMap,
     }
 
     /* Map the trampoline code area */
-    Status = MapVirtualMemory(PageMap, (PVOID)MM_TRAMPOLINE_ADDRESS,(PVOID)MM_TRAMPOLINE_ADDRESS,
-                              1, LoaderFirmwareTemporary);
+    Status = MapVirtualMemory(PageMap, MM_TRAMPOLINE_ADDRESS, MM_TRAMPOLINE_ADDRESS, 1, LoaderFirmwareTemporary);
     if(Status != STATUS_EFI_SUCCESS)
     {
         /* Mapping trampoline code failed */
@@ -110,7 +132,7 @@ Memory::BuildPageMap(IN PXTBL_PAGE_MAPPING PageMap,
         ModuleInfo = CONTAIN_RECORD(ModulesListEntry, XTBL_MODULE_INFO, Flink);
 
         /* Map module code */
-        Status = MapVirtualMemory(PageMap, ModuleInfo->ModuleBase, ModuleInfo->ModuleBase,
+        Status = MapVirtualMemory(PageMap, (ULONGLONG)ModuleInfo->ModuleBase, (ULONGLONG)ModuleInfo->ModuleBase,
                                   EFI_SIZE_TO_PAGES(ModuleInfo->ModuleSize), LoaderFirmwareTemporary);
 
         /* Check if mapping succeeded */
@@ -131,7 +153,7 @@ Memory::BuildPageMap(IN PXTBL_PAGE_MAPPING PageMap,
     if(LoaderBase && LoaderSize)
     {
         /* Map boot loader code as well */
-        Status = MapVirtualMemory(PageMap, LoaderBase, LoaderBase,
+        Status = MapVirtualMemory(PageMap, (ULONGLONG)LoaderBase, (ULONGLONG)LoaderBase,
                                   EFI_SIZE_TO_PAGES(LoaderSize), LoaderFirmwareTemporary);
         if(Status != STATUS_EFI_SUCCESS)
         {
@@ -145,6 +167,28 @@ Memory::BuildPageMap(IN PXTBL_PAGE_MAPPING PageMap,
         return STATUS_EFI_PROTOCOL_ERROR;
     }
 
+    /* Return success */
+    return STATUS_EFI_SUCCESS;
+}
+
+/**
+ * Iterates through the memory map and physically maps all virtual addresses to page tables.
+ *
+ * @param PageMap
+ *        Supplies a pointer to the page mapping structure.
+ *
+ * @return This routine returns a status code.
+ *
+ * @since XT 1.0
+ */
+XTCDECL
+EFI_STATUS
+Memory::CommitPageMap(IN PXTBL_PAGE_MAPPING PageMap)
+{
+    PXTBL_MEMORY_MAPPING Mapping;
+    PLIST_ENTRY ListEntry;
+    EFI_STATUS Status;
+
     /* Iterate through and map all the mappings*/
     Debug::Print(L"Mapping and dumping EFI memory:\n");
     ListEntry = PageMap->MemoryMap.Flink;
@@ -157,8 +201,9 @@ Memory::BuildPageMap(IN PXTBL_PAGE_MAPPING PageMap,
         if(Mapping->VirtualAddress)
         {
             /* Dump memory mapping */
-            Debug::Print(L"   Type=%02lu, PhysicalBase=%.8P, VirtualBase=%.8P, Pages=%llu\n", Mapping->MemoryType,
-                         Mapping->PhysicalAddress, Mapping->VirtualAddress, Mapping->NumberOfPages);
+            Debug::Print(L"   Type=%02lu, PhysicalBase=0x%.8llX, VirtualBase=0x%.8llX, Pages=%llu\n",
+                         Mapping->MemoryType, Mapping->PhysicalAddress,
+                         Mapping->VirtualAddress, Mapping->NumberOfPages);
 
             /* Map memory */
             Status = MapPage(PageMap, (UINT_PTR)Mapping->VirtualAddress,
@@ -252,7 +297,7 @@ Memory::GetNextPageTable(IN PXTBL_PAGE_MAPPING PageMap,
         }
 
         /* Add new memory mapping */
-        Status = MapVirtualMemory(PageMap, NULLPTR, (PVOID)(UINT_PTR)Address, 1, LoaderMemoryData);
+        Status = MapVirtualMemory(PageMap, (ULONGLONG)NULLPTR, Address, 1, LoaderMemoryData);
         if(Status != STATUS_EFI_SUCCESS)
         {
             /* Memory mapping failure */
@@ -313,11 +358,11 @@ Memory::GetNextPageTable(IN PXTBL_PAGE_MAPPING PageMap,
 XTCDECL
 EFI_STATUS
 Memory::MapPage(IN PXTBL_PAGE_MAPPING PageMap,
-                IN ULONG_PTR VirtualAddress,
-                IN ULONG_PTR PhysicalAddress,
-                IN ULONG NumberOfPages)
+                IN ULONGLONG VirtualAddress,
+                IN ULONGLONG PhysicalAddress,
+                IN ULONGLONG NumberOfPages)
 {
-    SIZE_T PageFrameNumber;
+    ULONGLONG PageFrameNumber;
     PVOID Pml1, Pml2, Pml3;
     SIZE_T Pml1Entry, Pml2Entry, Pml3Entry;
     PHARDWARE_LEGACY_PTE LegacyPmlTable;

boot/xtldr/biosutil.cc

@@ -0,0 +1,190 @@
+/**
+ * PROJECT:         ExectOS
+ * COPYRIGHT:       See COPYING.md in the top level directory
+ * FILE:            xtldr/biosutil.cc
+ * DESCRIPTION:     Legacy BIOS support
+ * DEVELOPERS:      Aiken Harris <harraiken91@gmail.com>
+ */
+
+#include <xtldr.hh>
+
+
+/**
+ * Clears the entire screen and moves the cursor to the top-left corner.
+ *
+ * @return This routine does not return any value.
+ *
+ * @since XT 1.0
+ */
+XTCDECL
+VOID
+BiosUtils::ClearScreen()
+{
+    VOLATILE PUSHORT VgaBuffer = (PUSHORT)0xB8000;
+    USHORT Blank;
+    UINT Index;
+
+    /* Set blank character */
+    Blank = (0x0F << 8) | L' ';
+
+    /* Fill the entire screen with blank characters */
+    for(Index = 0; Index < VgaWidth * VgaHeight; Index++)
+    {
+        VgaBuffer[Index] = Blank;
+    }
+
+    /* Reset cursor position to the top-left corner */
+    CursorX = 0;
+    CursorY = 0;
+
+    /* Update the hardware cursor position */
+    UpdateCursor();
+}
+
+/**
+ * Formats the input string and prints it out to the screen.
+ *
+ * @param Format
+ *        The formatted string that is to be written to the output.
+ *
+ * @param ...
+ *        Depending on the format string, this routine might expect a sequence of additional arguments.
+ *
+ * @return This routine does not return any value.
+ *
+ * @since XT 1.0
+ */
+XTCDECL
+VOID
+BiosUtils::Print(IN PCWSTR Format,
+                 IN ...)
+{
+    RTL_PRINT_CONTEXT PrintContext;
+    VA_LIST Arguments;
+
+    /* Initialise the print contexts */
+    PrintContext.WriteWideCharacter = PutChar;
+
+    /* Initialise the va_list */
+    VA_START(Arguments, Format);
+
+    /* Format and print the string to the stdout */
+    RTL::WideString::FormatWideString(&PrintContext, (PWCHAR)Format, Arguments);
+
+    /* Clean up the va_list */
+    VA_END(Arguments);
+}
+
+/**
+ * Writes a single wide character to the screen using legacy BIOS VGA text mode.
+ *
+ * @param Character
+ *        The wide character to be printed.
+ *
+ * @return This routine returns a status code.
+ *
+ * @since XT 1.0
+ */
+XTCDECL
+XTSTATUS
+BiosUtils::PutChar(IN WCHAR Character)
+{
+    VOLATILE PUSHORT VgaBuffer = (PUSHORT)0xB8000;
+    USHORT VgaCharacter;
+
+    /* Handle special characters */
+    if(Character == L'\n')
+    {
+        /* Move to the next line */
+        CursorX = 0;
+        CursorY++;
+    }
+    else if(Character == L'\r')
+    {
+        /* Move to the beginning of the current line */
+        CursorX = 0;
+    }
+    else
+    {
+        /* Print character and move cursor to the right */
+        VgaCharacter = (0x0F << 8) | (Character & 0xFF);
+        VgaBuffer[CursorY * VgaWidth + CursorX] = VgaCharacter;
+        CursorX++;
+    }
+
+    /* Handle moving to the next line if cursor is at the end of the line */
+    if(CursorX >= VgaWidth)
+    {
+        CursorX = 0;
+        CursorY++;
+    }
+
+    /* Handle scrolling if cursor is at the end of the screen */
+    if(CursorY >= VgaHeight)
+    {
+        ScrollScreen();
+        CursorY = VgaHeight - 1;
+    }
+
+    /* Update the hardware cursor position */
+    UpdateCursor();
+
+    /* Return success */
+    return STATUS_EFI_SUCCESS;
+}
+
+/**
+ * Scrolls the entire screen content up by one line and clears the last line.
+ *
+ * @return This routine does not return any value.
+ *
+ * @since XT 1.0
+ */
+XTCDECL
+VOID
+BiosUtils::ScrollScreen()
+{
+    VOLATILE PUSHORT VgaBuffer = (PUSHORT)0xB8000;
+    USHORT Blank;
+    UINT Index;
+
+    /* Set blank character */
+    Blank = (0x0F << 8) | L' ';
+
+    /* Move every line up by one */
+    for(Index = 0; Index < (VgaHeight - 1) * VgaWidth; Index++)
+    {
+        VgaBuffer[Index] = VgaBuffer[Index + VgaWidth];
+    }
+
+    /* Clear the last line */
+    for(Index = (VgaHeight - 1) * VgaWidth; Index < VgaHeight * VgaWidth; Index++)
+    {
+        VgaBuffer[Index] = Blank;
+    }
+}
+
+/**
+ * Updates the hardware cursor position on the screen.
+ *
+ * @return This routine does not return any value.
+ *
+ * @since XT 1.0
+ */
+XTCDECL
+VOID
+BiosUtils::UpdateCursor()
+{
+    USHORT Position;
+
+    /* Calculate cursor position */
+    Position = CursorY * VgaWidth + CursorX;
+
+    /* Send command to set the high byte of the cursor position */
+    HL::IoPort::WritePort8(0x3D4, 0x0E);
+    HL::IoPort::WritePort8(0x3D5, (UCHAR)((Position >> 8) & 0xFF));
+
+    /* Send command to set the low byte of the cursor position */
+    HL::IoPort::WritePort8(0x3D4, 0x0F);
+    HL::IoPort::WritePort8(0x3D5, (UCHAR)(Position & 0xFF));
+}

boot/xtldr/data.cc

@@ -10,6 +10,18 @@
 #include <xtldr.hh>
 
 
+/* Legacy BIOS cursor X position */
+USHORT BiosUtils::CursorX = 0;
+
+/* Legacy BIOS cursor Y position */
+USHORT BiosUtils::CursorY = 0;
+
+/* Legacy BIOS screen height */
+CONST USHORT BiosUtils::VgaHeight = 25;
+
+/* Legacy BIOS screen width */
+CONST USHORT BiosUtils::VgaWidth = 80;
+
 /* XT Boot Loader menu list */
 PLIST_ENTRY Configuration::BootMenuList = NULLPTR;
 

boot/xtldr/includes/xtldr.hh

@@ -15,6 +15,25 @@
 #include <libxtos.hh>
 
 
+class BiosUtils
+{
+    private:
+        STATIC USHORT CursorX;
+        STATIC USHORT CursorY;
+        STATIC CONST USHORT VgaHeight;
+        STATIC CONST USHORT VgaWidth;
+
+    public:
+        STATIC XTCDECL VOID ClearScreen();
+        STATIC XTCDECL VOID Print(IN PCWSTR Format,
+                                  IN ...);
+        STATIC XTCDECL XTSTATUS PutChar(IN WCHAR Character);
+
+    private:
+        STATIC XTCDECL VOID ScrollScreen();
+        STATIC XTCDECL VOID UpdateCursor();
+};
+
 class BootUtils
 {
     public:
@@ -146,6 +165,7 @@ class Memory
                                                OUT PVOID *Memory);
         STATIC XTCDECL EFI_STATUS BuildPageMap(IN PXTBL_PAGE_MAPPING PageMap,
                                                IN ULONG_PTR SelfMapAddress);
+        STATIC XTCDECL EFI_STATUS CommitPageMap(IN PXTBL_PAGE_MAPPING PageMap);
         STATIC XTCDECL EFI_STATUS FreePages(IN ULONGLONG NumberOfPages,
                                             IN EFI_PHYSICAL_ADDRESS Memory);
         STATIC XTCDECL EFI_STATUS FreePool(IN PVOID Memory);
@@ -158,15 +178,16 @@ class Memory
                                               IN SHORT PageMapLevel,
                                               IN PAGE_SIZE PageSize);
         STATIC XTCDECL EFI_STATUS MapEfiMemory(IN OUT PXTBL_PAGE_MAPPING PageMap,
-                                               IN OUT PVOID *MemoryMapAddress,
+                                               IN OUT PVOID *BaseAddress,
+                                               IN BOOLEAN IdentityMapping,
                                                IN PBL_GET_MEMTYPE_ROUTINE GetMemoryTypeRoutine);
         STATIC XTCDECL EFI_STATUS MapPage(IN PXTBL_PAGE_MAPPING PageMap,
-                                          IN ULONG_PTR VirtualAddress,
-                                          IN ULONG_PTR PhysicalAddress,
-                                          IN ULONG NumberOfPages);
+                                          IN ULONGLONG VirtualAddress,
+                                          IN ULONGLONG PhysicalAddress,
+                                          IN ULONGLONG NumberOfPages);
         STATIC XTCDECL EFI_STATUS MapVirtualMemory(IN OUT PXTBL_PAGE_MAPPING PageMap,
-                                                   IN PVOID VirtualAddress,
-                                                   IN PVOID PhysicalAddress,
+                                                   IN ULONGLONG VirtualAddress,
+                                                   IN ULONGLONG PhysicalAddress,
                                                    IN ULONGLONG NumberOfPages,
                                                    IN LOADER_MEMORY_TYPE MemoryType);
         STATIC XTCDECL PVOID PhysicalAddressToVirtual(IN PVOID PhysicalAddress,

boot/xtldr/memory.cc

@@ -314,9 +314,12 @@ Memory::InitializePageMap(OUT PXTBL_PAGE_MAPPING PageMap,
  * @param PageMap
  *        Supplies a pointer to the page mapping structure.
  *
- * @param MemoryMapAddress
+ * @param BaseAddress
  *        Supplies a virtual address, where EFI memory will be mapped.
  *
+ * @param IdentityMapping
+ *        Specifies whether EFI non-free memory should be mapped by identity or sequential mapping.
+ *
  * @param GetMemoryTypeRoutine
  *        Supplies a pointer to the routine which will be used to match EFI memory type to the OS memory type.
  *
@@ -327,19 +330,20 @@ Memory::InitializePageMap(OUT PXTBL_PAGE_MAPPING PageMap,
 XTCDECL
 EFI_STATUS
 Memory::MapEfiMemory(IN OUT PXTBL_PAGE_MAPPING PageMap,
-                     IN OUT PVOID *MemoryMapAddress,
+                     IN OUT PVOID *BaseAddress,
+                     IN BOOLEAN IdentityMapping,
                      IN PBL_GET_MEMTYPE_ROUTINE GetMemoryTypeRoutine)
 {
+    ULONGLONG MaxAddress, VirtualAddress;
     PEFI_MEMORY_DESCRIPTOR Descriptor;
     LOADER_MEMORY_TYPE MemoryType;
     PEFI_MEMORY_MAP MemoryMap;
     SIZE_T DescriptorCount;
-    PUCHAR VirtualAddress;
     EFI_STATUS Status;
     SIZE_T Index;
 
     /* Set virtual address as specified in argument */
-    VirtualAddress = (PUCHAR)*MemoryMapAddress;
+    VirtualAddress = (ULONGLONG)*BaseAddress;
 
     /* Check if custom memory type routine is specified */
     if(GetMemoryTypeRoutine == NULLPTR)
@@ -367,8 +371,37 @@ Memory::MapEfiMemory(IN OUT PXTBL_PAGE_MAPPING PageMap,
     /* Iterate through all descriptors from the memory map */
     for(Index = 0; Index < DescriptorCount; Index++)
     {
-        /* Make sure descriptor does not start beyond lowest physical page */
-        if(Descriptor->PhysicalStart <= MAXUINT_PTR)
+        /* Check page map level */
+        if(PageMap->PageMapLevel == 2)
+        {
+            /* Limit physical address to 4GB in legacy mode */
+            MaxAddress = 0xFFFFFFFF;
+        }
+        else if(PageMap->PageMapLevel == 3)
+        {
+            /* Limit physical address to 64GB in PAE mode */
+            MaxAddress = 0xFFFFFFFFFULL;
+        }
+
+        /* Check page map level */
+        if(PageMap->PageMapLevel == 2 || PageMap->PageMapLevel == 3)
+        {
+            /* Check if physical address starts beyond limit */
+            if(Descriptor->PhysicalStart >= MaxAddress)
+            {
+                /* Go to the next descriptor */
+                Descriptor = (PEFI_MEMORY_DESCRIPTOR)((PUCHAR)Descriptor + MemoryMap->DescriptorSize);
+                continue;
+            }
+
+            /* Check if memory descriptor exceeds the lowest physical page */
+            if(Descriptor->PhysicalStart + (Descriptor->NumberOfPages << EFI_PAGE_SHIFT) > MaxAddress)
+            {
+                /* Truncate memory descriptor to the lowest supported physical page */
+                Descriptor->NumberOfPages = (MaxAddress - Descriptor->PhysicalStart) >> EFI_PAGE_SHIFT;
+            }
+        }
+
         {
             /* Skip EFI reserved memory */
             if(Descriptor->Type == EfiReservedMemoryType)
@@ -378,25 +411,6 @@ Memory::MapEfiMemory(IN OUT PXTBL_PAGE_MAPPING PageMap,
                 continue;
             }
 
-            /* Check if preparing page map level 2 (non-PAE i686) */
-            if(PageMap->PageMapLevel == 2)
-            {
-                /* Check if physical address starts beyond 4GB */
-                if(Descriptor->PhysicalStart > 0xFFFFFFFF)
-                {
-                    /* Go to the next descriptor */
-                    Descriptor = (PEFI_MEMORY_DESCRIPTOR)((PUCHAR)Descriptor + MemoryMap->DescriptorSize);
-                    continue;
-                }
-
-                /* Check if memory descriptor exceeds the lowest physical page */
-                if(Descriptor->PhysicalStart + (Descriptor->NumberOfPages << EFI_PAGE_SHIFT) > MAXULONG)
-                {
-                    /* Truncate memory descriptor to the 4GB */
-                    Descriptor->NumberOfPages = (((ULONGLONG)MAXULONG + 1) - Descriptor->PhysicalStart) >> EFI_PAGE_SHIFT;
-                }
-            }
-
             /* Convert EFI memory type into XTLDR memory type */
             MemoryType = GetMemoryTypeRoutine((EFI_MEMORY_TYPE)Descriptor->Type);
 
@@ -404,22 +418,32 @@ Memory::MapEfiMemory(IN OUT PXTBL_PAGE_MAPPING PageMap,
             if(MemoryType == LoaderFirmwareTemporary)
             {
                 /* Map EFI firmware code */
-                Status = MapVirtualMemory(PageMap, (PVOID)Descriptor->PhysicalStart,
-                                          (PVOID)Descriptor->PhysicalStart, Descriptor->NumberOfPages, MemoryType);
+                Status = MapVirtualMemory(PageMap, Descriptor->PhysicalStart,
+                                          Descriptor->PhysicalStart, Descriptor->NumberOfPages, MemoryType);
             }
             else if(MemoryType != LoaderFree)
             {
-                /* Add any non-free memory mapping */
-                Status = MapVirtualMemory(PageMap, VirtualAddress, (PVOID)Descriptor->PhysicalStart,
-                                          Descriptor->NumberOfPages, MemoryType);
+                /* Check mapping strategy */
+                if(IdentityMapping)
+                {
+                    /* Add any non-free memory using identity mapping */
+                    Status = MapVirtualMemory(PageMap, Descriptor->PhysicalStart + KSEG0_BASE, Descriptor->PhysicalStart,
+                                              Descriptor->NumberOfPages, MemoryType);
+                }
+                else
+                {
+                    /* Add any non-free memory using sequential mapping */
+                    Status = MapVirtualMemory(PageMap, VirtualAddress, Descriptor->PhysicalStart,
+                                              Descriptor->NumberOfPages, MemoryType);
 
-                /* Calculate next valid virtual address */
-                VirtualAddress += Descriptor->NumberOfPages * EFI_PAGE_SIZE;
+                    /* Update virtual address */
+                    VirtualAddress = VirtualAddress + (Descriptor->NumberOfPages * MM_PAGE_SIZE);
+                }
             }
             else
             {
                 /* Map all other memory as loader free */
-                Status = MapVirtualMemory(PageMap, NULLPTR, (PVOID)Descriptor->PhysicalStart,
+                Status = MapVirtualMemory(PageMap, (ULONGLONG)NULLPTR, Descriptor->PhysicalStart,
                                           Descriptor->NumberOfPages, LoaderFree);
             }
 
@@ -436,7 +460,7 @@ Memory::MapEfiMemory(IN OUT PXTBL_PAGE_MAPPING PageMap,
     }
 
     /* Always map first page */
-    Status = MapVirtualMemory(PageMap, NULLPTR, (PVOID)0, 1, LoaderFirmwarePermanent);
+    Status = MapVirtualMemory(PageMap, (ULONGLONG)NULLPTR, 0, 1, LoaderFirmwarePermanent);
     if(Status != STATUS_EFI_SUCCESS)
     {
         /* Mapping failed */
@@ -444,7 +468,7 @@ Memory::MapEfiMemory(IN OUT PXTBL_PAGE_MAPPING PageMap,
     }
 
     /* Map BIOS ROM and VRAM */
-    Status = MapVirtualMemory(PageMap, NULLPTR, (PVOID)0xA0000, 0x60, LoaderFirmwarePermanent);
+    Status = MapVirtualMemory(PageMap, (ULONGLONG)NULLPTR, 0xA0000, 0x60, LoaderFirmwarePermanent);
     if(Status != STATUS_EFI_SUCCESS)
     {
         /* Mapping failed */
@@ -452,7 +476,7 @@ Memory::MapEfiMemory(IN OUT PXTBL_PAGE_MAPPING PageMap,
     }
 
     /* Store next valid virtual address and return success */
-    *MemoryMapAddress = VirtualAddress;
+    *BaseAddress = (PVOID)VirtualAddress;
     return STATUS_EFI_SUCCESS;
 }
 
@@ -481,13 +505,13 @@ Memory::MapEfiMemory(IN OUT PXTBL_PAGE_MAPPING PageMap,
 XTCDECL
 EFI_STATUS
 Memory::MapVirtualMemory(IN OUT PXTBL_PAGE_MAPPING PageMap,
-                         IN PVOID VirtualAddress,
-                         IN PVOID PhysicalAddress,
+                         IN ULONGLONG VirtualAddress,
+                         IN ULONGLONG PhysicalAddress,
                          IN ULONGLONG NumberOfPages,
                          IN LOADER_MEMORY_TYPE MemoryType)
 {
     PXTBL_MEMORY_MAPPING Mapping1, Mapping2, Mapping3;
-    PVOID PhysicalAddressEnd, PhysicalAddress2End;
+    ULONGLONG PhysicalAddressEnd, PhysicalAddress2End;
     PLIST_ENTRY ListEntry, MappingListEntry;
     SIZE_T NumberOfMappedPages;
     EFI_STATUS Status;
@@ -507,7 +531,7 @@ Memory::MapVirtualMemory(IN OUT PXTBL_PAGE_MAPPING PageMap,
     Mapping1->MemoryType = MemoryType;
 
     /* Calculate the end of the physical address */
-    PhysicalAddressEnd = (PVOID)((ULONG_PTR)PhysicalAddress + (NumberOfPages * EFI_PAGE_SIZE) - 1);
+    PhysicalAddressEnd = PhysicalAddress + (NumberOfPages * EFI_PAGE_SIZE) - 1;
 
     /* Iterate through all the mappings already set to insert new mapping at the correct place */
     ListEntry = PageMap->MemoryMap.Flink;
@@ -515,7 +539,7 @@ Memory::MapVirtualMemory(IN OUT PXTBL_PAGE_MAPPING PageMap,
     {
         /* Take a mapping from the list and calculate its end of physical address */
         Mapping2 = CONTAIN_RECORD(ListEntry, XTBL_MEMORY_MAPPING, ListEntry);
-        PhysicalAddress2End = (PVOID)((ULONG_PTR)Mapping2->PhysicalAddress + (Mapping2->NumberOfPages * EFI_PAGE_SIZE) - 1);
+        PhysicalAddress2End = Mapping2->PhysicalAddress + (Mapping2->NumberOfPages * EFI_PAGE_SIZE) - 1;
 
         /* Check if new mapping is a subset of an existing mapping */
         if(Mapping1->PhysicalAddress >= Mapping2->PhysicalAddress && PhysicalAddressEnd <= PhysicalAddress2End)
@@ -523,7 +547,8 @@ Memory::MapVirtualMemory(IN OUT PXTBL_PAGE_MAPPING PageMap,
             /* Make sure it's memory type is the same */
             if(Mapping1->MemoryType == Mapping2->MemoryType)
             {
-                /* It is already mapped */
+                /* Free the unused mapping structure and return success */
+                FreePool(Mapping1);
                 return STATUS_EFI_SUCCESS;
             }
         }
@@ -539,7 +564,7 @@ Memory::MapVirtualMemory(IN OUT PXTBL_PAGE_MAPPING PageMap,
             }
 
             /* Calculate number of pages for this mapping */
-            NumberOfMappedPages = ((PUCHAR)PhysicalAddress2End - (PUCHAR)PhysicalAddressEnd) / EFI_PAGE_SIZE;
+            NumberOfMappedPages = (PhysicalAddress2End - PhysicalAddressEnd) / EFI_PAGE_SIZE;
             if(NumberOfMappedPages > 0)
             {
                 /* Pages associated to the mapping, allocate memory for it */
@@ -550,18 +575,21 @@ Memory::MapVirtualMemory(IN OUT PXTBL_PAGE_MAPPING PageMap,
                     return Status;
                 }
 
-                /* Set mapping fields and insert it on the top */
-                Mapping3->PhysicalAddress = (PUCHAR)PhysicalAddressEnd + 1;
-                Mapping3->VirtualAddress = NULLPTR;
+                /* Set mapping fields */
+                Mapping3->PhysicalAddress = PhysicalAddressEnd + 1;
+                Mapping3->VirtualAddress = (ULONGLONG)NULLPTR;
                 Mapping3->NumberOfPages = NumberOfMappedPages;
                 Mapping3->MemoryType = Mapping2->MemoryType;
+
+                /* Insert new mapping in front of the list and increase page map size */
                 RTL::LinkedList::InsertHeadList(&Mapping2->ListEntry, &Mapping3->ListEntry);
+                PageMap->MapSize++;
             }
 
             /* Calculate number of pages and the end of the physical address */
             Mapping2->NumberOfPages = ((PUCHAR)PhysicalAddressEnd + 1 -
                                        (PUCHAR)Mapping2->PhysicalAddress) / EFI_PAGE_SIZE;
-            PhysicalAddress2End = (PVOID)((ULONG_PTR)Mapping2->PhysicalAddress + (Mapping2->NumberOfPages * EFI_PAGE_SIZE) - 1);
+            PhysicalAddress2End = Mapping2->PhysicalAddress + (Mapping2->NumberOfPages * EFI_PAGE_SIZE) - 1;
         }
 
         /* Check if they overlap */
@@ -586,18 +614,21 @@ Memory::MapVirtualMemory(IN OUT PXTBL_PAGE_MAPPING PageMap,
                     return Status;
                 }
 
-                /* Set mapping fields and insert it on the top */
+                /* Set mapping fields */
                 Mapping3->PhysicalAddress = Mapping1->PhysicalAddress;
-                Mapping3->VirtualAddress = NULLPTR;
+                Mapping3->VirtualAddress = (ULONGLONG)NULLPTR;
                 Mapping3->NumberOfPages = NumberOfMappedPages;
                 Mapping3->MemoryType = Mapping2->MemoryType;
+
+                /* Insert new mapping in front of the list and increase page map size */
                 RTL::LinkedList::InsertHeadList(&Mapping2->ListEntry, &Mapping3->ListEntry);
+                PageMap->MapSize++;
             }
 
             /* Calculate number of pages and the end of the physical address */
             Mapping2->NumberOfPages = ((PUCHAR)Mapping1->PhysicalAddress -
                                        (PUCHAR)Mapping2->PhysicalAddress) / EFI_PAGE_SIZE;
-            PhysicalAddress2End = (PVOID)((ULONG_PTR)Mapping2->PhysicalAddress + (Mapping2->NumberOfPages * EFI_PAGE_SIZE) - 1);
+            PhysicalAddress2End = Mapping2->PhysicalAddress + (Mapping2->NumberOfPages * EFI_PAGE_SIZE) - 1;
         }
 
         /* Check if mapping is really needed */
@@ -619,15 +650,19 @@ Memory::MapVirtualMemory(IN OUT PXTBL_PAGE_MAPPING PageMap,
             Status = FreePool(Mapping2);
             ListEntry = MappingListEntry;
 
-            /* Go to the next mapping */
+            /* Decrease page map size and go to the next mapping */
+            PageMap->MapSize--;
             continue;
         }
 
         /* Determine physical address order */
         if(Mapping2->PhysicalAddress > Mapping1->PhysicalAddress)
         {
-            /* Insert new mapping in front */
+            /* Insert new mapping in front of the list and increase page map size */
             RTL::LinkedList::InsertHeadList(Mapping2->ListEntry.Blink, &Mapping1->ListEntry);
+            PageMap->MapSize++;
+
+            /* Return success */
             return STATUS_EFI_SUCCESS;
         }
 
@@ -635,7 +670,7 @@ Memory::MapVirtualMemory(IN OUT PXTBL_PAGE_MAPPING PageMap,
         ListEntry = ListEntry->Flink;
     }
 
-    /* Insert new mapping to the list and increase page map size */
+    /* Insert new mapping to the tail of the list and increase page map size */
     RTL::LinkedList::InsertTailList(&PageMap->MemoryMap, &Mapping1->ListEntry);
     PageMap->MapSize++;
 

boot/xtldr/modules/pecoff/pecoff.cc

@@ -729,11 +729,11 @@ PeCoff::RelocateLoadedImage(IN PPECOFF_IMAGE_CONTEXT Image)
     }
     else
     {
-        /* Check if loaded 32-bit PE32 image should be relocated */
         /* Set relocation data directory and image base address */
         DataDirectory = &Image->PeHeader->OptionalHeader32.DataDirectory[PECOFF_IMAGE_DIRECTORY_ENTRY_BASERELOC];
         ImageBase = Image->PeHeader->OptionalHeader32.ImageBase;
 
+        /* Check if loaded 32-bit PE32 image should be relocated */
         if(Image->PeHeader->OptionalHeader32.NumberOfRvaAndSizes <= PECOFF_IMAGE_DIRECTORY_ENTRY_BASERELOC ||
         DataDirectory->VirtualAddress == 0 || DataDirectory->Size < sizeof(PECOFF_IMAGE_BASE_RELOCATION))
         {

boot/xtldr/modules/xtos_o/amd64/memory.cc

@@ -10,6 +10,49 @@
 #include <xtos.hh>
 
 
+XTCDECL
+EFI_STATUS
+Xtos::BuildPageMap(IN PXTBL_PAGE_MAPPING PageMap)
+{
+    EFI_STATUS Status;
+
+    /* Build page map */
+    Status = XtLdrProtocol->Memory.BuildPageMap(PageMap, (PageMap->PageMapLevel > 4) ? MM_P5E_LA57_BASE : MM_PXE_BASE);
+    if(Status != STATUS_EFI_SUCCESS)
+    {
+        /* Failed to build page map */
+        XtLdrProtocol->Debug.Print(L"Failed to build page map (Status code: %zX)\n", Status);
+        return Status;
+    }
+
+    /* Map memory for hardware layer */
+    Status = MapHardwareMemoryPool(PageMap);
+    if(Status != STATUS_EFI_SUCCESS)
+    {
+        /* Failed to map memory for hardware layer */
+        XtLdrProtocol->Debug.Print(L"Failed to map memory for hardware leyer (Status code: %zX)\n", Status);
+        return Status;
+    }
+
+    /* Return success */
+    return STATUS_EFI_SUCCESS;
+}
+
+/**
+ * Determines the appropriate EFI memory mapping strategy for the AMD64 architecture.
+ *
+ * @return This routine returns TRUE, what results in an identity mapping.
+ *
+ * @since XT 1.0
+ */
+XTCDECL
+BOOLEAN
+Xtos::DetermineMappingStrategy()
+{
+    /* Use an identity mapping strategy */
+    return TRUE;
+}
+
 /**
  * Determines the appropriate paging level (PML) for the AMD64 architecture.
  *
@@ -76,24 +119,6 @@ Xtos::EnablePaging(IN PXTBL_PAGE_MAPPING PageMap)
     ULONG_PTR TrampolineSize;
     PVOID TrampolineCode;
 
-    /* Build page map */
-    Status = XtLdrProtocol->Memory.BuildPageMap(PageMap, (PageMap->PageMapLevel > 4) ? MM_P5E_LA57_BASE : MM_PXE_BASE);
-    if(Status != STATUS_EFI_SUCCESS)
-    {
-        /* Failed to build page map */
-        XtLdrProtocol->Debug.Print(L"Failed to build page map (Status code: %zX)\n", Status);
-        return Status;
-    }
-
-    /* Map memory for hardware layer */
-    Status = MapHardwareMemoryPool(PageMap);
-    if(Status != STATUS_EFI_SUCCESS)
-    {
-        /* Failed to map memory for hardware layer */
-        XtLdrProtocol->Debug.Print(L"Failed to map memory for hardware leyer (Status code: %zX)\n", Status);
-        return Status;
-    }
-
     /* Check the configured page map level to set the LA57 state accordingly */
     if(PageMap->PageMapLevel == 5)
     {
@@ -173,6 +198,7 @@ Xtos::MapHardwareMemoryPool(IN PXTBL_PAGE_MAPPING PageMap)
     PHARDWARE_PTE P5eBase, PdeBase, PpeBase, PxeBase;
     EFI_PHYSICAL_ADDRESS Address;
     EFI_STATUS Status;
+    ULONG Index;
 
     if(PageMap->PageMapLevel == 5)
     {
@@ -190,6 +216,9 @@ Xtos::MapHardwareMemoryPool(IN PXTBL_PAGE_MAPPING PageMap)
                 return Status;
             }
 
+            /* Map hardware memory */
+            XtLdrProtocol->Memory.MapVirtualMemory(PageMap, (ULONGLONG)NULLPTR, Address, 1, LoaderMemoryData);
+
             /* Zero fill memory used by P5E */
             XtLdrProtocol->Memory.ZeroMemory((PVOID)Address, EFI_PAGE_SIZE);
 
@@ -224,6 +253,9 @@ Xtos::MapHardwareMemoryPool(IN PXTBL_PAGE_MAPPING PageMap)
             return Status;
         }
 
+        /* Map hardware memory */
+        XtLdrProtocol->Memory.MapVirtualMemory(PageMap, (ULONGLONG)NULLPTR, Address, 1, LoaderMemoryData);
+
         /* Zero fill memory used by PXE */
         XtLdrProtocol->Memory.ZeroMemory((PVOID)Address, EFI_PAGE_SIZE);
 
@@ -252,6 +284,9 @@ Xtos::MapHardwareMemoryPool(IN PXTBL_PAGE_MAPPING PageMap)
             return Status;
         }
 
+        /* Map hardware memory */
+        XtLdrProtocol->Memory.MapVirtualMemory(PageMap, (ULONGLONG)NULLPTR, Address, 1, LoaderMemoryData);
+
         /* Zero fill memory used by PPE */
         XtLdrProtocol->Memory.ZeroMemory((PVOID)Address, EFI_PAGE_SIZE);
 
@@ -270,7 +305,7 @@ Xtos::MapHardwareMemoryPool(IN PXTBL_PAGE_MAPPING PageMap)
     }
 
     /* Loop through 2 PDE entries */
-    for(UINT Index = 0 ; Index < 2 ; Index++)
+    for(Index = 0 ; Index < 2 ; Index++)
     {
         /* Check if PDE entry already exists */
         if(!PdeBase[((MM_HARDWARE_VA_START >> MM_PDI_SHIFT) & 0x1FF) + Index].Valid)
@@ -283,6 +318,9 @@ Xtos::MapHardwareMemoryPool(IN PXTBL_PAGE_MAPPING PageMap)
                 return Status;
             }
 
+            /* Map hardware memory */
+            XtLdrProtocol->Memory.MapVirtualMemory(PageMap, (ULONGLONG)NULLPTR, Address, 1, LoaderMemoryData);
+
             /* Zero fill memory used by PDE */
             XtLdrProtocol->Memory.ZeroMemory((PVOID)Address, EFI_PAGE_SIZE);
 

boot/xtldr/modules/xtos_o/i686/memory.cc

@@ -9,6 +9,62 @@
 #include <xtos.hh>
 
 
+XTCDECL
+EFI_STATUS
+Xtos::BuildPageMap(IN PXTBL_PAGE_MAPPING PageMap)
+{
+    ULONG_PTR SelfMapAddress;
+    EFI_STATUS Status;
+
+    /* Initialize self map address */
+    if(PageMap->PageMapLevel == 3)
+    {
+        /* For PML3 (PAE) use PTE base address */
+        SelfMapAddress = MM_PTE_BASE;
+    }
+    else
+    {
+        /* For PML2 (PAE disabled) use legacy PDE base address */
+        SelfMapAddress = MM_PDE_LEGACY_BASE;
+    }
+
+    /* Build page map */
+    Status = XtLdrProtocol->Memory.BuildPageMap(PageMap, SelfMapAddress);
+    if(Status != STATUS_EFI_SUCCESS)
+    {
+        /* Failed to build page map */
+        XtLdrProtocol->Debug.Print(L"Failed to build page map (Status code: %zX)\n", Status);
+        return Status;
+    }
+
+    /* Map memory for hardware layer */
+    Status = MapHardwareMemoryPool(PageMap);
+    if(Status != STATUS_EFI_SUCCESS)
+    {
+        /* Failed to map memory for hardware layer */
+        XtLdrProtocol->Debug.Print(L"Failed to map memory for hardware layer (Status code: %zX)\n", Status);
+        return Status;
+    }
+
+    /* Return success */
+    return STATUS_EFI_SUCCESS;
+}
+
+/**
+ * Determines the appropriate EFI memory mapping strategy for the i686 architecture.
+ *
+ * @return This routine returns FALSE, what results in a sequential mapping.
+ *
+ * @since XT 1.0
+ */
+XTCDECL
+BOOLEAN
+Xtos::DetermineMappingStrategy()
+{
+    /* Use a sequential mapping strategy */
+    return FALSE;
+}
+
 /**
  * Determines the appropriate paging level (PML) for the i686 architecture.
  *
@@ -60,24 +116,6 @@ Xtos::EnablePaging(IN PXTBL_PAGE_MAPPING PageMap)
 {
     EFI_STATUS Status;
 
-    /* Build page map */
-    Status = XtLdrProtocol->Memory.BuildPageMap(PageMap, MM_PTE_BASE);
-    if(Status != STATUS_EFI_SUCCESS)
-    {
-        /* Failed to build page map */
-        XtLdrProtocol->Debug.Print(L"Failed to build page map (Status code: %zX)\n", Status);
-        return Status;
-    }
-
-    /* Map memory for hardware layer */
-    Status = MapHardwareMemoryPool(PageMap);
-    if(Status != STATUS_EFI_SUCCESS)
-    {
-        /* Failed to map memory for hardware layer */
-        XtLdrProtocol->Debug.Print(L"Failed to map memory for hardware layer (Status code: %zX)\n", Status);
-        return Status;
-    }
-
     /* Exit EFI Boot Services */
     XtLdrProtocol->Debug.Print(L"Exiting EFI boot services\n");
     Status = XtLdrProtocol->Utils.ExitBootServices();
@@ -145,6 +183,9 @@ Xtos::MapHardwareMemoryPool(IN PXTBL_PAGE_MAPPING PageMap)
     /* Zero fill allocated memory */
     XtLdrProtocol->Memory.ZeroMemory((PVOID)Address, EFI_PAGE_SIZE);
 
+    /* Map hardware memory */
+    XtLdrProtocol->Memory.MapVirtualMemory(PageMap, (ULONGLONG)NULLPTR, Address, 1, LoaderMemoryData);
+
     /* Check if PAE is enabled (3-level paging) */
     if(PageMap->PageMapLevel == 3)
     {

boot/xtldr/modules/xtos_o/includes/xtos.hh

@@ -38,7 +38,9 @@ class Xtos
                                                           IN PVOID PhysicalAddress,
                                                           IN UINT NumberOfPages,
                                                           IN LOADER_MEMORY_TYPE MemoryType);
+        STATIC XTCDECL EFI_STATUS BuildPageMap(IN PXTBL_PAGE_MAPPING PageMap);
         STATIC XTCDECL LOADER_MEMORY_TYPE ConvertEfiMemoryType(IN EFI_MEMORY_TYPE EfiMemoryType);
+        STATIC XTCDECL BOOLEAN DetermineMappingStrategy();
         STATIC XTCDECL ULONG DeterminePagingLevel(IN CONST PWCHAR Parameters);
         STATIC XTCDECL EFI_STATUS EnablePaging(IN PXTBL_PAGE_MAPPING PageMap);
         STATIC XTCDECL VOID GetDisplayInformation(OUT PSYSTEM_RESOURCE_FRAMEBUFFER FrameBufferResource,
@@ -46,10 +48,13 @@ class Xtos
                                                   IN PULONG_PTR FrameBufferSize,
                                                   IN PXTBL_FRAMEBUFFER_MODE_INFORMATION FrameBufferModeInfo);
         STATIC XTCDECL EFI_STATUS GetMemoryDescriptorList(IN PXTBL_PAGE_MAPPING PageMap,
-                                                          IN PVOID *VirtualAddress,
+                                                          IN EFI_PHYSICAL_ADDRESS PhysicalBase,
+                                                          IN PVOID VirtualBase,
                                                           OUT PLIST_ENTRY MemoryDescriptorList);
         STATIC XTCDECL EFI_STATUS GetSystemResourcesList(IN PXTBL_PAGE_MAPPING PageMap,
-                                                         IN PVOID *VirtualAddress,
+                                                         IN EFI_PHYSICAL_ADDRESS PhysicalBase,
+                                                         IN PVOID VirtualBase,
+                                                         IN PVOID FrameBufferVirtualBase,
                                                          OUT PLIST_ENTRY SystemResourcesList);
         STATIC XTCDECL EFI_STATUS GetVirtualAddress(IN PLIST_ENTRY MemoryMappings,
                                                     IN PVOID PhysicalAddress,

boot/xtldr/modules/xtos_o/xtos.cc

@@ -191,56 +191,52 @@ Xtos::GetDisplayInformation(OUT PSYSTEM_RESOURCE_FRAMEBUFFER FrameBufferResource
 XTCDECL
 EFI_STATUS
 Xtos::GetMemoryDescriptorList(IN PXTBL_PAGE_MAPPING PageMap,
-                              IN PVOID *VirtualAddress,
+                              IN EFI_PHYSICAL_ADDRESS PhysicalBase,
+                              IN PVOID VirtualBase,
                               OUT PLIST_ENTRY MemoryDescriptorList)
 {
-    EFI_PHYSICAL_ADDRESS Address;
-    EFI_STATUS Status;
-    ULONGLONG Pages;
-
-    Pages = (ULONGLONG)EFI_SIZE_TO_PAGES((PageMap->MapSize + 1) * sizeof(LOADER_MEMORY_DESCRIPTOR));
-
-    Status = XtLdrProtocol->Memory.AllocatePages(AllocateAnyPages, Pages, &Address);
-    if(Status != STATUS_EFI_SUCCESS)
-    {
-        return Status;
-    }
-
-    Status = XtLdrProtocol->Memory.MapVirtualMemory(PageMap, *VirtualAddress, (PVOID)Address, Pages, LoaderMemoryData);
-    if(Status != STATUS_EFI_SUCCESS)
-    {
-        XtLdrProtocol->Memory.FreePages(Address, Pages);
-        return Status;
-    }
-
-    PVOID PhysicalBase = (PVOID)Address;
-
+    PLOADER_MEMORY_DESCRIPTOR Descriptor;
+    PXTBL_MEMORY_MAPPING MemoryMapping;
     PLIST_ENTRY ListEntry;
+
+    /* Initialize the descriptor pointer to the start of the allocated physical buffer */
+    Descriptor = (PLOADER_MEMORY_DESCRIPTOR)PhysicalBase;
+
+    /* Get the first entry from the internal boot loader memory map */
     ListEntry = PageMap->MemoryMap.Flink;
+
+    /* Iterate through the internal memory map and populate the loader descriptor list */
     while(ListEntry != &PageMap->MemoryMap)
     {
-        PXTBL_MEMORY_MAPPING MemoryMapping = CONTAIN_RECORD(ListEntry, XTBL_MEMORY_MAPPING, ListEntry);
-        PLOADER_MEMORY_DESCRIPTOR MemoryDescriptor = (PLOADER_MEMORY_DESCRIPTOR)Address;
+        /* Retrieve the internal memory mapping record from the current list entry */
+        MemoryMapping = CONTAIN_RECORD(ListEntry, XTBL_MEMORY_MAPPING, ListEntry);
 
-        MemoryDescriptor->MemoryType = MemoryMapping->MemoryType;
-        MemoryDescriptor->BasePage = (UINT_PTR)MemoryMapping->PhysicalAddress / EFI_PAGE_SIZE;
-        MemoryDescriptor->PageCount = MemoryMapping->NumberOfPages;
+        /* Transfer memory type and address information to the kernel descriptor */
+        Descriptor->MemoryType = MemoryMapping->MemoryType;
+        Descriptor->BasePage = (UINT_PTR)(MemoryMapping->PhysicalAddress / EFI_PAGE_SIZE);
+        Descriptor->PageCount = (ULONG)MemoryMapping->NumberOfPages;
 
-        XtLdrProtocol->LinkedList.InsertTail(MemoryDescriptorList, &MemoryDescriptor->ListEntry);
+        /* Link the entry */
+        XtLdrProtocol->LinkedList.InsertTail(MemoryDescriptorList, &Descriptor->ListEntry);
 
-        Address = Address + sizeof(LOADER_MEMORY_DESCRIPTOR);
+        /* Move to the next slot in the allocated buffer */
+        Descriptor++;
         ListEntry = ListEntry->Flink;
     }
 
-    XtLdrProtocol->Memory.PhysicalListToVirtual(PageMap, MemoryDescriptorList, PhysicalBase, *VirtualAddress);
+    /* Convert all physical link pointers in the list to their corresponding virtual addresses */
+    XtLdrProtocol->Memory.PhysicalListToVirtual(PageMap, MemoryDescriptorList, (PVOID)PhysicalBase, VirtualBase);
 
+    /* Return success */
     return STATUS_EFI_SUCCESS;
 }
 
 XTCDECL
 EFI_STATUS
 Xtos::GetSystemResourcesList(IN PXTBL_PAGE_MAPPING PageMap,
-                             IN PVOID *VirtualAddress,
+                             IN EFI_PHYSICAL_ADDRESS PhysicalBase,
+                             IN PVOID VirtualBase,
+                             IN PVOID FrameBufferVirtualBase,
                              OUT PLIST_ENTRY SystemResourcesList)
 {
     XTSTATUS Status;
@@ -251,39 +247,18 @@ Xtos::GetSystemResourcesList(IN PXTBL_PAGE_MAPPING PageMap,
     PXTBL_FRAMEBUFFER_PROTOCOL FrameBufProtocol;
     XTBL_FRAMEBUFFER_MODE_INFORMATION FbModeInfo;
     EFI_PHYSICAL_ADDRESS FbAddress;
+    EFI_PHYSICAL_ADDRESS OriginalPhysicalBase;
     ULONG_PTR FbSize;
-    UINT FrameBufferPages;
     PSYSTEM_RESOURCE_FRAMEBUFFER FrameBufferResource;
     PSYSTEM_RESOURCE_ACPI AcpiResource;
-    ULONGLONG Pages;
-    EFI_PHYSICAL_ADDRESS Address;
-    PVOID PhysicalBase, VirtualBase;
 
-    Pages = (ULONGLONG)EFI_SIZE_TO_PAGES(sizeof(SYSTEM_RESOURCE_ACPI) + sizeof(SYSTEM_RESOURCE_FRAMEBUFFER));
-
-    Status = XtLdrProtocol->Memory.AllocatePages(AllocateAnyPages, Pages, &Address);
-    if(Status != STATUS_EFI_SUCCESS)
-    {
-        return Status;
-    }
-    Status = XtLdrProtocol->Memory.MapVirtualMemory(PageMap, *VirtualAddress, (PVOID)Address, Pages, LoaderFirmwarePermanent);
-    if(Status != STATUS_EFI_SUCCESS)
-    {
-        XtLdrProtocol->Memory.FreePages(Address, Pages);
-        return Status;
-    }
-
-    PhysicalBase = (PVOID)Address;
-    VirtualBase = *VirtualAddress;
-
-    /* Calculate next valid virtual address */
-    *VirtualAddress = (PUINT8)*VirtualAddress + (Pages * EFI_PAGE_SIZE);
-
-    AcpiResource = (PSYSTEM_RESOURCE_ACPI)Address;
+    /* Save original physical base */
+    OriginalPhysicalBase = PhysicalBase;
 
+    AcpiResource = (PSYSTEM_RESOURCE_ACPI)PhysicalBase;
     XtLdrProtocol->Memory.ZeroMemory(AcpiResource, sizeof(SYSTEM_RESOURCE_ACPI));
 
-    /* Load FrameBuffer protocol */
+    /* Load ACPI protocol */
     Status = XtLdrProtocol->Protocol.Open(&ProtocolHandle, (PVOID*)&AcpiProtocol, &AcpiGuid);
     if(Status != STATUS_EFI_SUCCESS)
     {
@@ -302,13 +277,11 @@ Xtos::GetSystemResourcesList(IN PXTBL_PAGE_MAPPING PageMap,
 
     XtLdrProtocol->LinkedList.InsertTail(SystemResourcesList, &AcpiResource->Header.ListEntry);
 
-    /* Close FrameBuffer protocol */
-    XtLdrProtocol->Protocol.Close(&ProtocolHandle, &FrameBufGuid);
-
-    Address = Address + sizeof(SYSTEM_RESOURCE_ACPI);
-
-    FrameBufferResource = (PSYSTEM_RESOURCE_FRAMEBUFFER)Address;
+    /* Close ACPI protocol */
+    XtLdrProtocol->Protocol.Close(&ProtocolHandle, &AcpiGuid);
 
+    PhysicalBase = PhysicalBase + sizeof(SYSTEM_RESOURCE_ACPI);
+    FrameBufferResource = (PSYSTEM_RESOURCE_FRAMEBUFFER)PhysicalBase;
     XtLdrProtocol->Memory.ZeroMemory(FrameBufferResource, sizeof(SYSTEM_RESOURCE_FRAMEBUFFER));
 
     /* Load FrameBuffer protocol */
@@ -329,26 +302,16 @@ Xtos::GetSystemResourcesList(IN PXTBL_PAGE_MAPPING PageMap,
         return Status;
     }
 
-    /* Calculate pages needed to map framebuffer */
-    FrameBufferPages = EFI_SIZE_TO_PAGES(FbSize);
-
-    /* Rewrite framebuffer address by using virtual address */
-    FrameBufferResource->Header.VirtualAddress = *VirtualAddress;
-
-    /* Map frame buffer memory */
-    XtLdrProtocol->Memory.MapVirtualMemory(PageMap, FrameBufferResource->Header.VirtualAddress,
-                                           FrameBufferResource->Header.PhysicalAddress,
-                                           FrameBufferPages, LoaderFirmwarePermanent);
-
-    /* Close FrameBuffer protocol */
+    /* Assign the pre-mapped virtual address to the resource block */
+    FrameBufferResource->Header.VirtualAddress = FrameBufferVirtualBase;
     XtLdrProtocol->Protocol.Close(&ProtocolHandle, &FrameBufGuid);
 
-    *VirtualAddress = (PUINT8)*VirtualAddress + (FrameBufferPages * EFI_PAGE_SIZE);
-
     XtLdrProtocol->LinkedList.InsertTail(SystemResourcesList, &FrameBufferResource->Header.ListEntry);
 
-    XtLdrProtocol->Memory.PhysicalListToVirtual(PageMap, SystemResourcesList, PhysicalBase, VirtualBase);
+    /* Convert list pointers to virtual */
+    XtLdrProtocol->Memory.PhysicalListToVirtual(PageMap, SystemResourcesList, (PVOID)OriginalPhysicalBase, VirtualBase);
 
+    /* Return success */
     return STATUS_EFI_SUCCESS;
 }
 
@@ -389,7 +352,7 @@ Xtos::InitializeApicBase(IN PXTBL_PAGE_MAPPING PageMap)
     }
 
     /* Map APIC base address */
-    XtLdrProtocol->Memory.MapVirtualMemory(PageMap, (PVOID)APIC_BASE, ApicBaseAddress, 1, LoaderFirmwarePermanent);
+    XtLdrProtocol->Memory.MapVirtualMemory(PageMap, APIC_BASE, (ULONGLONG)ApicBaseAddress, 1, LoaderFirmwarePermanent);
     return STATUS_EFI_SUCCESS;
 }
 
@@ -409,34 +372,100 @@ Xtos::InitializeApicBase(IN PXTBL_PAGE_MAPPING PageMap)
 XTCDECL
 EFI_STATUS
 Xtos::InitializeLoaderBlock(IN PXTBL_PAGE_MAPPING PageMap,
-                            IN PVOID *VirtualAddress,
+                            IN OUT PVOID *VirtualAddress,
                             IN PXTBL_BOOT_PARAMETERS Parameters)
 {
+    EFI_PHYSICAL_ADDRESS FbPhysicalAddress, PhysicalBlock, PhysicalDescriptor, PhysicalResources;
+    PVOID FbVirtualAddress, VirtualBlock, VirtualResources, VirtualDescriptor;
+    UINT BlockPages, DescriptorPages, FbPages, ParametersSize, ResourcesPages;
+    XTBL_FRAMEBUFFER_MODE_INFORMATION FbModeInfo;
+    PXTBL_FRAMEBUFFER_PROTOCOL FrameBufProtocol;
     PKERNEL_INITIALIZATION_BLOCK LoaderBlock;
-    EFI_PHYSICAL_ADDRESS Address;
+    EFI_HANDLE ProtocolHandle;
     EFI_STATUS Status;
-    UINT BlockPages;
-    UINT ParametersSize;
+    ULONG_PTR FbSize;
+
+    EFI_GUID FrameBufGuid = XT_FRAMEBUFFER_PROTOCOL_GUID;
+
+    /* Initialize Framebuffer information */
+    FbPhysicalAddress = 0;
+    FbSize = 0;
+    FbVirtualAddress = NULLPTR;
+    FbPages = 0;
 
     /* Calculate size of parameters */
     ParametersSize = (XtLdrProtocol->WideString.Length(Parameters->Parameters, 0) + 1) * sizeof(WCHAR);
 
     /* Calculate number of pages needed for initialization block */
     BlockPages = EFI_SIZE_TO_PAGES(sizeof(KERNEL_INITIALIZATION_BLOCK) + ParametersSize);
+    ResourcesPages = EFI_SIZE_TO_PAGES(sizeof(SYSTEM_RESOURCE_ACPI) + sizeof(SYSTEM_RESOURCE_FRAMEBUFFER));
 
-    /* Allocate memory for kernel initialization block */
-    Status = XtLdrProtocol->Memory.AllocatePages(AllocateAnyPages, BlockPages, &Address);
+    /* Query Framebuffer size for allocation */
+    if(XtLdrProtocol->Protocol.Open(&ProtocolHandle, (PVOID*)&FrameBufProtocol, &FrameBufGuid) == STATUS_EFI_SUCCESS)
+    {
+        /* Get FrameBuffer information */
+        FrameBufProtocol->GetDisplayInformation(&FbPhysicalAddress, &FbSize, &FbModeInfo);
+        XtLdrProtocol->Protocol.Close(&ProtocolHandle, &FrameBufGuid);
+    }
+    FbPages = EFI_SIZE_TO_PAGES(FbSize);
+
+    /* Precommit page map to allocate memory */
+    XtLdrProtocol->Memory.CommitPageMap(PageMap);
+
+    /* Calculate number of pages needed for memory descriptor list */
+    DescriptorPages = EFI_SIZE_TO_PAGES(PageMap->MapSize * sizeof(LOADER_MEMORY_DESCRIPTOR) * 2);
+
+    /* Allocate memory for the kernel initialization block and boot parameters */
+    Status = XtLdrProtocol->Memory.AllocatePages(AllocateAnyPages, BlockPages, &PhysicalBlock);
     if(Status != STATUS_EFI_SUCCESS)
     {
-        /* Memory allocation failure */
+        /* Memory allocation failure, return status code */
         return Status;
     }
 
-    /* Initialize and zero-fill kernel initialization block */
-    LoaderBlock = (PKERNEL_INITIALIZATION_BLOCK)(UINT_PTR)Address;
-    XtLdrProtocol->Memory.ZeroMemory(LoaderBlock, sizeof(KERNEL_INITIALIZATION_BLOCK) + ParametersSize);
+    /* Allocate memory for the system resources data structures */
+    Status = XtLdrProtocol->Memory.AllocatePages(AllocateAnyPages, ResourcesPages, &PhysicalResources);
+    if(Status != STATUS_EFI_SUCCESS)
+    {
+        /* Memory allocation failure, return status code */
+        return Status;
+    }
+
+    /* Allocate memory for the memory descriptor list */
+    Status = XtLdrProtocol->Memory.AllocatePages(AllocateAnyPages, DescriptorPages, &PhysicalDescriptor);
+    if(Status != STATUS_EFI_SUCCESS)
+    {
+        /* Memory allocation failure, return status code */
+        return Status;
+    }
+
+    /* Map the Kernel Initialization Block into virtual memory and advance the virtual address pointer */
+    VirtualBlock = *VirtualAddress;
+    XtLdrProtocol->Memory.MapVirtualMemory(PageMap, (ULONGLONG)VirtualBlock, PhysicalBlock, BlockPages, LoaderSystemBlock);
+    *VirtualAddress = (PUINT8)*VirtualAddress + (BlockPages * EFI_PAGE_SIZE);
+
+    /* Map the system resources physical memory into virtual address space and update the allocation pointer */
+    VirtualResources = *VirtualAddress;
+    XtLdrProtocol->Memory.MapVirtualMemory(PageMap, (ULONGLONG)VirtualResources, PhysicalResources, ResourcesPages, LoaderFirmwarePermanent);
+    *VirtualAddress = (PUINT8)*VirtualAddress + (ResourcesPages * EFI_PAGE_SIZE);
+
+    /* Check if a framebuffer was detected and requires memory mapping */
+    if(FbPages > 0)
+    {
+        /* Map the framebuffer physical memory range into virtual address space */
+        FbVirtualAddress = *VirtualAddress;
+        XtLdrProtocol->Memory.MapVirtualMemory(PageMap, (ULONGLONG)FbVirtualAddress, FbPhysicalAddress, FbPages, LoaderFirmwarePermanent);
+        *VirtualAddress = (PUINT8)*VirtualAddress + (FbPages * EFI_PAGE_SIZE);
+    }
+
+    /* Map the allocated physical memory for memory descriptors into the virtual address space */
+    VirtualDescriptor = *VirtualAddress;
+    XtLdrProtocol->Memory.MapVirtualMemory(PageMap, (ULONGLONG)VirtualDescriptor, PhysicalDescriptor, DescriptorPages, LoaderMemoryData);
+    *VirtualAddress = (PUINT8)*VirtualAddress + (DescriptorPages * EFI_PAGE_SIZE);
 
     /* Set basic loader block properties */
+    XtLdrProtocol->Memory.ZeroMemory((PVOID)PhysicalBlock, sizeof(KERNEL_INITIALIZATION_BLOCK) + ParametersSize);
+    LoaderBlock = (PKERNEL_INITIALIZATION_BLOCK)PhysicalBlock;
     LoaderBlock->BlockSize = sizeof(KERNEL_INITIALIZATION_BLOCK);
     LoaderBlock->BlockVersion = INITIALIZATION_BLOCK_VERSION;
     LoaderBlock->ProtocolVersion = BOOT_PROTOCOL_VERSION;
@@ -450,24 +479,33 @@ Xtos::InitializeLoaderBlock(IN PXTBL_PAGE_MAPPING PageMap,
     LoaderBlock->FirmwareInformation.EfiFirmware.EfiRuntimeServices = NULLPTR;
 
     /* Copy parameters to kernel initialization block */
-    LoaderBlock->KernelParameters = (PWCHAR)((UINT_PTR)*VirtualAddress + sizeof(KERNEL_INITIALIZATION_BLOCK));
+    LoaderBlock->KernelParameters = (PWCHAR)((UINT_PTR)VirtualBlock + sizeof(KERNEL_INITIALIZATION_BLOCK));
     XtLdrProtocol->Memory.CopyMemory((PVOID)((UINT_PTR)LoaderBlock + sizeof(KERNEL_INITIALIZATION_BLOCK)),
-                  Parameters->Parameters,
-                  ParametersSize);
+                                     Parameters->Parameters, ParametersSize);
 
-    /* Map kernel initialization block */
-    XtLdrProtocol->Memory.MapVirtualMemory(PageMap, *VirtualAddress, (PVOID)LoaderBlock,
-                                           BlockPages, LoaderSystemBlock);
-
-    /* Calculate next valid virtual address */
-    *VirtualAddress = (PUINT8)*VirtualAddress + (BlockPages * EFI_PAGE_SIZE);
+    /* Commit mappings */
+    XtLdrProtocol->Memory.CommitPageMap(PageMap);
 
+    /* Initialize system resources list */
     XtLdrProtocol->LinkedList.InitializeHead(&LoaderBlock->SystemResourcesListHead);
-    GetSystemResourcesList(PageMap, VirtualAddress, &LoaderBlock->SystemResourcesListHead);
+    Status = GetSystemResourcesList(PageMap, PhysicalResources, VirtualResources, FbVirtualAddress, &LoaderBlock->SystemResourcesListHead);
+    if(Status != STATUS_EFI_SUCCESS)
+    {
+        /* Failed to initialize system resources list, return status code */
+        return Status;
+    }
 
     /* Initialize memory descriptor list */
     XtLdrProtocol->LinkedList.InitializeHead(&LoaderBlock->MemoryDescriptorListHead);
-    GetMemoryDescriptorList(PageMap, VirtualAddress, &LoaderBlock->MemoryDescriptorListHead);
+    Status = GetMemoryDescriptorList(PageMap, PhysicalDescriptor, VirtualDescriptor, &LoaderBlock->MemoryDescriptorListHead);
+    if(Status != STATUS_EFI_SUCCESS)
+    {
+        /* Failed to initialize memory descriptor list, return status code */
+        return Status;
+    }
+
+    /* Set boot image size */
+    LoaderBlock->BootImageSize = (PFN_NUMBER)(((ULONGLONG)*VirtualAddress - KSEG0_BASE) / EFI_PAGE_SIZE);
 
     /* Return success */
     return STATUS_EFI_SUCCESS;
@@ -607,11 +645,12 @@ Xtos::RunBootSequence(IN PEFI_FILE_HANDLE BootDir,
     PXTBL_FRAMEBUFFER_PROTOCOL FrameBufProtocol;
     PPECOFF_IMAGE_CONTEXT ImageContext = NULLPTR;
     PEFI_LOADED_IMAGE_PROTOCOL ImageProtocol;
-    PVOID VirtualAddress, VirtualMemoryArea;
+    PVOID VirtualAddress;
     PXT_ENTRY_POINT KernelEntryPoint;
     EFI_HANDLE ProtocolHandle;
     EFI_STATUS Status;
     XTBL_PAGE_MAPPING PageMap;
+    BOOLEAN IdentityMapping;
 
     /* Initialize XTOS startup sequence */
     XtLdrProtocol->Debug.Print(L"Initializing XTOS startup sequence\n");
@@ -628,19 +667,30 @@ Xtos::RunBootSequence(IN PEFI_FILE_HANDLE BootDir,
     /* Close FrameBuffer protocol */
     XtLdrProtocol->Protocol.Close(&ProtocolHandle, &FrameBufGuid);
 
+    /* Determine whether to use a sequential or an identity mapping strategy */
+    IdentityMapping = DetermineMappingStrategy();
+
     /* Set base virtual memory area for the kernel mappings */
-    VirtualMemoryArea = (PVOID)KSEG0_BASE;
-    VirtualAddress = (PVOID)(KSEG0_BASE + KSEG0_KERNEL_BASE);
+    VirtualAddress = (PVOID)(KSEG0_BASE);
 
     /* Initialize virtual memory mappings */
     XtLdrProtocol->Memory.InitializePageMap(&PageMap, DeterminePagingLevel(Parameters->Parameters), Size4K);
 
-    Status = XtLdrProtocol->Memory.MapEfiMemory(&PageMap, &VirtualMemoryArea, NULLPTR);
+    /* Map all EFI memory regions */
+    Status = XtLdrProtocol->Memory.MapEfiMemory(&PageMap, &VirtualAddress, IdentityMapping, NULLPTR);
     if(Status != STATUS_EFI_SUCCESS)
     {
+        /* Mapping failed */
         return Status;
     }
 
+    /* Check mapping strategy */
+    if(IdentityMapping)
+    {
+        /* Adjust virtual address to skip the identity-mapped physical range */
+        VirtualAddress = (PVOID)((ULONGLONG)VirtualAddress + 0x800000000);
+    }
+
     /* Load the kernel */
     Status = LoadModule(BootDir, Parameters->KernelFile, VirtualAddress, LoaderSystemCode, &ImageContext);
     if(Status != STATUS_EFI_SUCCESS)
@@ -650,8 +700,8 @@ Xtos::RunBootSequence(IN PEFI_FILE_HANDLE BootDir,
     }
 
     /* Add kernel image memory mapping */
-    Status = XtLdrProtocol->Memory.MapVirtualMemory(&PageMap, ImageContext->VirtualAddress,
-                                                    ImageContext->PhysicalAddress, ImageContext->ImagePages,
+    Status = XtLdrProtocol->Memory.MapVirtualMemory(&PageMap, (ULONGLONG)ImageContext->VirtualAddress,
+                                                    (ULONGLONG)ImageContext->PhysicalAddress, ImageContext->ImagePages,
                                                     LoaderSystemCode);
     if(Status != STATUS_EFI_SUCCESS)
     {
@@ -670,6 +720,14 @@ Xtos::RunBootSequence(IN PEFI_FILE_HANDLE BootDir,
         return Status;
     }
 
+    /* Build page map */
+    Status = BuildPageMap(&PageMap);
+    if(Status != STATUS_EFI_SUCCESS)
+    {
+        XtLdrProtocol->Debug.Print(L"Failed to build page map (Status code: %zX)\n", Status);
+        return Status;
+    }
+
     /* Store virtual address of kernel initialization block for future kernel call */
     KernelParameters = (PKERNEL_INITIALIZATION_BLOCK)VirtualAddress;
 

boot/xtldr/protocol.cc

@@ -1054,6 +1054,7 @@ Protocol::InstallXtLoaderProtocol()
     LoaderProtocol.Memory.AllocatePages = Memory::AllocatePages;
     LoaderProtocol.Memory.AllocatePool = Memory::AllocatePool;
     LoaderProtocol.Memory.BuildPageMap = Memory::BuildPageMap;
+    LoaderProtocol.Memory.CommitPageMap = Memory::CommitPageMap;
     LoaderProtocol.Memory.CompareMemory = RTL::Memory::CompareMemory;
     LoaderProtocol.Memory.CopyMemory = RTL::Memory::CopyMemory;
     LoaderProtocol.Memory.FreePages = Memory::FreePages;

boot/xtldr/xtldr.cc

@@ -236,6 +236,15 @@ BlStartXtLoader(IN EFI_HANDLE ImageHandle,
     PWCHAR Modules;
     EFI_STATUS Status;
 
+    /* Check if system is EFI-based and provided parameters are valid */
+    if(ImageHandle == NULLPTR || SystemTable == NULLPTR)
+    {
+        /* Invalid parameters, print error message using BIOS calls and hang */
+        BiosUtils::ClearScreen();
+        BiosUtils::Print(L"XTLDR requires EFI-based system!");
+        for(;;);
+    }
+
     /* Initialize XTLDR and */
     XtLoader::InitializeBootLoader(ImageHandle, SystemTable);
 

configure.ps1

@@ -4,48 +4,41 @@
 # DESCRIPTION: Project configuration script for preparing the build environment
 # DEVELOPERS:  Aiken Harris <harraiken91@gmail.com>
 
-
 # Check XTchain
 if (-not $env:XTCVER) {
-    Write-Host "XTChain not detected or corrupted!"
+    Write-Error "XTChain not detected or corrupted!"
     exit 1
 }
 
-# Set target architecture
-if ($env:TARGET) {
-    $ARCH = $env:TARGET
-} else {
-    $ARCH = "amd64"
-}
+# Set target architecture defaulting to amd64
+$ARCH = if ($env:TARGET) { $env:TARGET } else { "amd64" }
 
-# Set target build type
-if (-not $env:BUILD_TYPE) {
-    $env:BUILD_TYPE = "DEBUG"
-}
+# Set target build type defaulting to Debug
+$env:BUILD_TYPE = if ($env:BUILD_TYPE -in @("Debug", "Release")) { $env:BUILD_TYPE } else { "Debug" }
 
 # Set variables
-$EXECTOS_SOURCE_DIR = (Get-Location).Path
-$EXECTOS_BINARY_DIR = "build-$($ARCH)-$($env:BUILD_TYPE.ToLower())"
+$EXECTOS_SOURCE_DIR = $PSScriptRoot
+$EXECTOS_BINARY_DIR = Join-Path $EXECTOS_SOURCE_DIR "build-$ARCH-$($env:BUILD_TYPE.ToLower())"
 
-# Create directories if needed
-if ($EXECTOS_SOURCE_DIR -eq (Get-Location).Path) {
-    Write-Host "Creating directories in $EXECTOS_BINARY_DIR"
+# Create build directory
+if (-not (Test-Path $EXECTOS_BINARY_DIR)) {
+    Write-Host "Creating build directory: $EXECTOS_BINARY_DIR"
     New-Item -ItemType Directory -Path $EXECTOS_BINARY_DIR -Force | Out-Null
-    Set-Location -Path $EXECTOS_BINARY_DIR
 }
 
+Set-Location $EXECTOS_BINARY_DIR
+
 # Delete old cache
-Remove-Item -Path "CMakeCache.txt" -ErrorAction SilentlyContinue
-Remove-Item -Path "host-tools/CMakeCache.txt" -ErrorAction SilentlyContinue
+Remove-Item "CMakeCache.txt", "host-tools/CMakeCache.txt" -ErrorAction SilentlyContinue
 
 # Configure project using CMake
-& cmake -G Ninja -DARCH:STRING=$($ARCH) -DBUILD_TYPE:STRING=$($env:BUILD_TYPE) $EXECTOS_SOURCE_DIR
+& cmake -G Ninja "-DARCH:STRING=$ARCH" "-DBUILD_TYPE:STRING=$($env:BUILD_TYPE)" $EXECTOS_SOURCE_DIR
 
 # Check if configuration succeeded
 if ($LASTEXITCODE -ne 0) {
-    Write-Host "Configure script failed."
+    Write-Error "Configure script failed."
     exit 1
-} else {
-    "$($ARCH)" | Out-File -Encoding ASCII -NoNewline build.arch
-    Write-Host "Configure script completed. Enter '$EXECTOS_BINARY_DIR' directory and execute 'xbuild' to build ExectOS."
 }
+
+$ARCH | Out-File -Encoding ASCII -NoNewline "build.arch"
+Write-Host "Configure completed. Run 'xbuild' to build ExectOS."

sdk/CMakeLists.txt

@@ -1 +1,3 @@
+add_subdirectory("xtadk")
+
 set_sdk_target("xtdk/" "include")

sdk/cmake/baseaddress/amd64.cmake

@@ -1,2 +1,3 @@
 # Set base addresses for all modules
+set(BASEADDRESS_XTLDR    0x000000000000F800)
 set(BASEADDRESS_XTOSKRNL 0x0000000140000000)

sdk/cmake/baseaddress/i686.cmake

@@ -1,2 +1,3 @@
 # Set base addresses for all modules
+set(BASEADDRESS_XTLDR    0x0000F800)
 set(BASEADDRESS_XTOSKRNL 0x00400000)

sdk/cmake/functions.cmake

@@ -59,16 +59,102 @@ function(add_module_linker_flags MODULE FLAGS)
     set_module_property(${MODULE} LINK_FLAGS ${FLAGS})
 endfunction()
 
+# This function compiles XT Assembly Development Kit
+function(generate_xtadk TARGET_NAME SOURCE_FILES)
+    # Define the absolute destination path for the generated header file
+    set(HEADER_OUTPUT "${EXECTOS_BINARY_DIR}/sdk/includes/${TARGET_NAME}.h")
+    get_filename_component(HEADER_OUTPUT_DIRECTORY "${HEADER_OUTPUT}" DIRECTORY)
+
+    # Tokenize global CXX flags into a list to ensure correct argument expansion
+    separate_arguments(COMPILER_FLAGS NATIVE_COMMAND "${CMAKE_CXX_FLAGS}")
+
+    # Resolve and tokenize build-configuration specific flags
+    string(TOUPPER "${CMAKE_BUILD_TYPE}" BUILD_TYPE)
+    if(BUILD_TYPE)
+        separate_arguments(BUILD_TYPE_SPECIFIC_FLAGS NATIVE_COMMAND "${CMAKE_CXX_FLAGS_${BUILD_TYPE}}")
+    endif()
+
+    # Retrieve compiler definitions, include paths, and options
+    get_directory_property(COMPILE_DEFINITIONS COMPILE_DEFINITIONS)
+    get_directory_property(INCLUDE_DIRECTORIES INCLUDE_DIRECTORIES)
+    get_directory_property(COMPILE_OPTIONS COMPILE_OPTIONS)
+
+    # Initialize the final compiler argument list
+    set(COMPILER_ARGUMENTS "")
+    list(APPEND COMPILER_ARGUMENTS ${COMPILER_FLAGS} ${BUILD_TYPE_SPECIFIC_FLAGS})
+
+    # Transform definitions into MSVC-style
+    foreach(DEFINITION ${COMPILE_DEFINITIONS})
+        list(APPEND COMPILER_ARGUMENTS "/D${DEFINITION}")
+    endforeach()
+
+    # Transform include paths into MSVC-style
+    foreach(INCLUDE_PATH ${INCLUDE_DIRECTORIES})
+        list(APPEND COMPILER_ARGUMENTS "/I${INCLUDE_PATH}")
+    endforeach()
+
+    # Append all supplemental compiler options
+    list(APPEND COMPILER_ARGUMENTS ${COMPILE_OPTIONS})
+    set(COLLECTED_ASSEMBLY_OUTPUTS "")
+
+    # Iterate through each source file to create individual assembly generation rules
+    foreach(SOURCE_FILE_PATH ${SOURCE_FILES})
+        # Extract the base filename
+        get_filename_component(FILENAME_WITHOUT_EXTENSION "${SOURCE_FILE_PATH}" NAME_WE)
+
+        # Define the unique output path for the intermediate assembly file
+        set(CURRENT_ASSEMBLY_OUTPUT "${CMAKE_CURRENT_BINARY_DIR}/${FILENAME_WITHOUT_EXTENSION}.S")
+        list(APPEND COLLECTED_ASSEMBLY_OUTPUTS "${CURRENT_ASSEMBLY_OUTPUT}")
+        get_filename_component(CURRENT_ASSEMBLY_DIRECTORY "${CURRENT_ASSEMBLY_OUTPUT}" DIRECTORY)
+
+        # Execute the compiler to generate assembly code
+        add_custom_command(
+            OUTPUT "${CURRENT_ASSEMBLY_OUTPUT}"
+            COMMAND ${CMAKE_COMMAND} -E make_directory "${CURRENT_ASSEMBLY_DIRECTORY}"
+            COMMAND ${CMAKE_CXX_COMPILER}
+                ${COMPILER_ARGUMENTS}
+                /c /FAs /Fa${CURRENT_ASSEMBLY_OUTPUT}
+                -- ${SOURCE_FILE_PATH}
+            DEPENDS "${SOURCE_FILE_PATH}"
+            COMMENT "Generating XTADK Assembly: ${FILENAME_WITHOUT_EXTENSION}"
+            VERBATIM
+            COMMAND_EXPAND_LISTS
+        )
+    endforeach()
+
+    # Aggregate all generated assembly units into a single consolidated XTADK header
+    add_custom_command(
+        OUTPUT "${HEADER_OUTPUT}"
+        COMMAND ${CMAKE_COMMAND} -E make_directory "${HEADER_OUTPUT_DIRECTORY}"
+        COMMAND xtadkgen ${COLLECTED_ASSEMBLY_OUTPUTS} -O "${HEADER_OUTPUT}"
+        DEPENDS ${COLLECTED_ASSEMBLY_OUTPUTS}
+        COMMENT "Generating XTADK header: ${TARGET_NAME}"
+        VERBATIM
+    )
+
+    # Establish the generation target and expose the header directory via an interface library
+    add_custom_target(${TARGET_NAME}_gen DEPENDS "${HEADER_OUTPUT}")
+    add_library(${TARGET_NAME} INTERFACE)
+    add_dependencies(${TARGET_NAME} ${TARGET_NAME}_gen)
+    target_include_directories(${TARGET_NAME} INTERFACE "${EXECTOS_BINARY_DIR}/sdk/includes")
+endfunction()
+
 # This function compiles an assembly bootsector file into a flat binary
 function(compile_bootsector NAME SOURCE BASEADDR ENTRYPOINT)
     set(BINARY_NAME "${NAME}.bin")
     set(OBJECT_NAME "${NAME}.obj")
 
+    get_directory_property(DEFS COMPILE_DEFINITIONS)
+    foreach(def ${DEFS})
+        list(APPEND ASM_DEFS "-D${def}")
+    endforeach()
+
     add_custom_command(
         OUTPUT ${CMAKE_CURRENT_BINARY_DIR}/${BINARY_NAME}
         COMMAND ${CMAKE_ASM_COMPILER}
             /nologo
             --target=i386-none-elf
+            ${ASM_DEFS}
             -I${CMAKE_CURRENT_SOURCE_DIR}
             /Fo${CMAKE_CURRENT_BINARY_DIR}/${OBJECT_NAME}
             -c -- ${SOURCE}

sdk/firmware/README.md

@@ -13,6 +13,10 @@ The ovmf_vars files, store UEFI variables, which are used to store and retrieve
 boot options, device settings, and system preferences. The ovmf_vars file contains the persistent variables specific to
 a virtual machine, allowing it to maintain its configuration across multiple boot sessions.
 
+## BOCHS ROM BIOS
+The rombios.bin file contains the ROM BIOS image for Bochs. This image is distributed under the GNU Lesser General Public
+License (LGPL).
+
 ## Video BIOS (LGPL'd VGABios)
 The vgabios.bin file contains the Video Bios for Bochs and QEMU. This VGA Bios is very specific to the emulated VGA card.
 It is NOT meant to drive a physical vga card. It also implements support for VBE version 2.0.

sdk/xtadk/CMakeLists.txt

@@ -0,0 +1,14 @@
+# XT Assembly Development Kit
+PROJECT(XTADK)
+
+# Specify include directories
+include_directories(
+    ${EXECTOS_SOURCE_DIR}/sdk/xtdk
+    ${XTADK_SOURCE_DIR}/includes)
+
+# Specify list of XTADK source code files
+list(APPEND XTADK_SOURCE
+    ${XTADK_SOURCE_DIR}/${ARCH}/ke.cc)
+
+# Generate assembly header from XTADK sources
+generate_xtadk(xtadk "${XTADK_SOURCE}")

sdk/xtadk/amd64/ke.cc

@@ -0,0 +1,83 @@
+/**
+ * PROJECT:         ExectOS
+ * COPYRIGHT:       See COPYING.md in the top level directory
+ * FILE:            sdk/xtadk/amd64/ke.cc
+ * DESCRIPTION:     ADK generator for AMD64 version of Kernel Library
+ * DEVELOPERS:      Aiken Harris <harraiken91@gmail.com>
+ */
+
+#include <xtkmapi.h>
+#include <adkdefs.h>
+
+
+/**
+ * Generates a definitions file for the Kernel Library used by the XTOS kernel assembly code
+ *
+ * @return This routine does not return any value.
+ *
+ * @since XT 1.0
+ */
+XTCLINK
+XTAPI
+VOID
+GenerateAssemblyDefinitions(VOID)
+{
+    /* Generate KTRAP_FRAME offsets */
+    ADK_OFFSET(KTRAP_FRAME, Xmm0);
+    ADK_OFFSET(KTRAP_FRAME, Xmm1);
+    ADK_OFFSET(KTRAP_FRAME, Xmm2);
+    ADK_OFFSET(KTRAP_FRAME, Xmm3);
+    ADK_OFFSET(KTRAP_FRAME, Xmm4);
+    ADK_OFFSET(KTRAP_FRAME, Xmm5);
+    ADK_OFFSET(KTRAP_FRAME, Xmm6);
+    ADK_OFFSET(KTRAP_FRAME, Xmm7);
+    ADK_OFFSET(KTRAP_FRAME, Xmm8);
+    ADK_OFFSET(KTRAP_FRAME, Xmm9);
+    ADK_OFFSET(KTRAP_FRAME, Xmm10);
+    ADK_OFFSET(KTRAP_FRAME, Xmm11);
+    ADK_OFFSET(KTRAP_FRAME, Xmm12);
+    ADK_OFFSET(KTRAP_FRAME, Xmm13);
+    ADK_OFFSET(KTRAP_FRAME, Xmm14);
+    ADK_OFFSET(KTRAP_FRAME, Xmm15);
+    ADK_OFFSET(KTRAP_FRAME, MxCsr);
+    ADK_OFFSET(KTRAP_FRAME, PreviousMode);
+    ADK_OFFSET(KTRAP_FRAME, Cr2);
+    ADK_OFFSET(KTRAP_FRAME, Cr3);
+    ADK_OFFSET(KTRAP_FRAME, Dr0);
+    ADK_OFFSET(KTRAP_FRAME, Dr1);
+    ADK_OFFSET(KTRAP_FRAME, Dr2);
+    ADK_OFFSET(KTRAP_FRAME, Dr3);
+    ADK_OFFSET(KTRAP_FRAME, Dr6);
+    ADK_OFFSET(KTRAP_FRAME, Dr7);
+    ADK_OFFSET(KTRAP_FRAME, SegDs);
+    ADK_OFFSET(KTRAP_FRAME, SegEs);
+    ADK_OFFSET(KTRAP_FRAME, SegFs);
+    ADK_OFFSET(KTRAP_FRAME, SegGs);
+    ADK_OFFSET(KTRAP_FRAME, Rax);
+    ADK_OFFSET(KTRAP_FRAME, Rbx);
+    ADK_OFFSET(KTRAP_FRAME, Rcx);
+    ADK_OFFSET(KTRAP_FRAME, Rdx);
+    ADK_OFFSET(KTRAP_FRAME, R8);
+    ADK_OFFSET(KTRAP_FRAME, R9);
+    ADK_OFFSET(KTRAP_FRAME, R10);
+    ADK_OFFSET(KTRAP_FRAME, R11);
+    ADK_OFFSET(KTRAP_FRAME, R12);
+    ADK_OFFSET(KTRAP_FRAME, R13);
+    ADK_OFFSET(KTRAP_FRAME, R14);
+    ADK_OFFSET(KTRAP_FRAME, R15);
+    ADK_OFFSET(KTRAP_FRAME, Rsi);
+    ADK_OFFSET(KTRAP_FRAME, Rdi);
+    ADK_OFFSET(KTRAP_FRAME, Rbp);
+    ADK_OFFSET(KTRAP_FRAME, Vector);
+    ADK_OFFSET(KTRAP_FRAME, ErrorCode);
+    ADK_OFFSET(KTRAP_FRAME, ExceptionFrame);
+    ADK_OFFSET(KTRAP_FRAME, Rip);
+    ADK_OFFSET(KTRAP_FRAME, SegCs);
+    ADK_OFFSET(KTRAP_FRAME, Flags);
+    ADK_OFFSET(KTRAP_FRAME, Rsp);
+    ADK_OFFSET(KTRAP_FRAME, SegSs);
+
+    /* Generate KTRAP_FRAME size and REGISTERS_SIZE */
+    ADK_SIZE(KTRAP_FRAME);
+    ADK_SIZE_FROM(REGISTERS_SIZE, KTRAP_FRAME, Rax);
+}

sdk/xtadk/i686/ke.cc

@@ -0,0 +1,57 @@
+/**
+ * PROJECT:         ExectOS
+ * COPYRIGHT:       See COPYING.md in the top level directory
+ * FILE:            sdk/xtadk/i686/ke.cc
+ * DESCRIPTION:     ADK generator for i686 version of Kernel Library
+ * DEVELOPERS:      Aiken Harris <harraiken91@gmail.com>
+ */
+
+#include <xtkmapi.h>
+#include <adkdefs.h>
+
+
+/**
+ * Generates a definitions file for the Kernel Library used by the XTOS kernel assembly code
+ *
+ * @return This routine does not return any value.
+ *
+ * @since XT 1.0
+ */
+XTCLINK
+XTAPI
+VOID
+GenerateAssemblyDefinitions(VOID)
+{
+    /* Generate KTRAP_FRAME offsets */
+    ADK_OFFSET(KTRAP_FRAME, PreviousMode);
+    ADK_OFFSET(KTRAP_FRAME, Cr2);
+    ADK_OFFSET(KTRAP_FRAME, Cr3);
+    ADK_OFFSET(KTRAP_FRAME, Dr0);
+    ADK_OFFSET(KTRAP_FRAME, Dr1);
+    ADK_OFFSET(KTRAP_FRAME, Dr2);
+    ADK_OFFSET(KTRAP_FRAME, Dr3);
+    ADK_OFFSET(KTRAP_FRAME, Dr6);
+    ADK_OFFSET(KTRAP_FRAME, Dr7);
+    ADK_OFFSET(KTRAP_FRAME, SegDs);
+    ADK_OFFSET(KTRAP_FRAME, SegEs);
+    ADK_OFFSET(KTRAP_FRAME, SegFs);
+    ADK_OFFSET(KTRAP_FRAME, SegGs);
+    ADK_OFFSET(KTRAP_FRAME, Eax);
+    ADK_OFFSET(KTRAP_FRAME, Ebx);
+    ADK_OFFSET(KTRAP_FRAME, Ecx);
+    ADK_OFFSET(KTRAP_FRAME, Edx);
+    ADK_OFFSET(KTRAP_FRAME, Esi);
+    ADK_OFFSET(KTRAP_FRAME, Edi);
+    ADK_OFFSET(KTRAP_FRAME, Ebp);
+    ADK_OFFSET(KTRAP_FRAME, Vector);
+    ADK_OFFSET(KTRAP_FRAME, ErrorCode);
+    ADK_OFFSET(KTRAP_FRAME, Eip);
+    ADK_OFFSET(KTRAP_FRAME, SegCs);
+    ADK_OFFSET(KTRAP_FRAME, Flags);
+    ADK_OFFSET(KTRAP_FRAME, Esp);
+    ADK_OFFSET(KTRAP_FRAME, SegSs);
+
+    /* Generate KTRAP_FRAME size and REGISTERS_SIZE */
+    ADK_SIZE(KTRAP_FRAME);
+    ADK_SIZE_FROM(REGISTERS_SIZE, KTRAP_FRAME, Eax);
+}

sdk/xtadk/includes/adkdefs.h

@@ -0,0 +1,19 @@
+/**
+ * PROJECT:         ExectOS
+ * COPYRIGHT:       See COPYING.md in the top level directory
+ * FILE:            sdk/xtadk/adkdefs.h
+ * DESCRIPTION:     Definitions for XTADK
+ * DEVELOPERS:      Aiken Harris <harraiken91@gmail.com>
+ */
+
+#ifndef __XTADK_ADKDEFS_H
+#define __XTADK_ADKDEFS_H
+
+
+/* Macros for calculating structure size and offsets for assembler code */
+#define ADK_DEFINE(Symbol, Value)              __asm__ volatile("\n\t# ==> " #Symbol " %c0" : : "i" ((SIZE_T)(Value)))
+#define ADK_OFFSET(Structure, Member)          ADK_DEFINE(Structure ## _ ## Member, FIELD_OFFSET(Structure, Member))
+#define ADK_SIZE(Structure)                    ADK_DEFINE(Structure ## _SIZE, sizeof(Structure))
+#define ADK_SIZE_FROM(Name, Structure, Member) ADK_DEFINE(Structure ## _ ## Name, sizeof(Structure) - FIELD_OFFSET(Structure, Member))
+
+#endif /* __XTADK_ADKDEFS_H */

sdk/xtdk/amd64/artypes.h

@@ -12,6 +12,7 @@
 #include <xtdefs.h>
 #include <xtstruct.h>
 #include <xttypes.h>
+#include ARCH_HEADER(xtstruct.h)
 
 
 /* Control Register 0 constants */
@@ -127,6 +128,10 @@
 #define X86_EFLAGS_VIP_MASK                             0x00100000 /* Virtual Interrupt Pending */
 #define X86_EFLAGS_ID_MASK                              0x00200000 /* Identification */
 
+
+/* C/C++ specific code */
+#ifndef __XTOS_ASSEMBLER__
+
 /* CPU vendor enumeration list */
 typedef enum _CPU_VENDOR
 {
@@ -135,6 +140,18 @@ typedef enum _CPU_VENDOR
     CPU_VENDOR_UNKNOWN = 0xFFFFFFFF
 } CPU_VENDOR, *PCPU_VENDOR;
 
+/* CPUID advanced power management features (0x80000007) enumeration list */
+typedef enum _CPUID_FEATURES_ADVANCED_POWER_MANAGEMENT
+{
+    CPUID_FEATURES_EDX_TS                     = 1 << 0, /* Temperature Sensor */
+    CPUID_FEATURES_EDX_FIS                    = 1 << 1, /* Frequency ID Selection */
+    CPUID_FEATURES_EDX_VIS                    = 1 << 2, /* Voltage ID Selection */
+    CPUID_FEATURES_EDX_TTS                    = 1 << 3, /* ThermaTrip Support */
+    CPUID_FEATURES_EDX_HTC                    = 1 << 4, /* Hardware Thermal Throttling */
+    CPUID_FEATURES_EDX_STC                    = 1 << 5, /* Software Thermal Throttling */
+    CPUID_FEATURES_EDX_TSCI                   = 1 << 8 /* TSC Invariant */
+} CPUID_FEATURES_ADVANCED_POWER_MANAGEMENT, *PCPUID_FEATURES_ADVANCED_POWER_MANAGEMENT;
+
 /* CPUID extended features (0x80000001) enumeration list */
 typedef enum _CPUID_FEATURES_EXTENDED
 {
@@ -176,6 +193,23 @@ typedef enum _CPUID_FEATURES_EXTENDED
     CPUID_FEATURES_EDX_3DNOW                  = 1 << 31
 } CPUID_FEATURES_EXTENDED, *PCPUID_FEATURES_EXTENDED;
 
+/* CPUID Thermal and Power Management features (0x00000006) enumeration list */
+typedef enum _CPUID_FEATURES_POWER_MANAGEMENT
+{
+    CPUID_FEATURES_EAX_DTHERM                  = 1 << 0,
+    CPUID_FEATURES_EAX_IDA                     = 1 << 1,
+    CPUID_FEATURES_EAX_ARAT                    = 1 << 2,
+    CPUID_FEATURES_EAX_PLN                     = 1 << 4,
+    CPUID_FEATURES_EAX_PTS                     = 1 << 6,
+    CPUID_FEATURES_EAX_HWP                     = 1 << 7,
+    CPUID_FEATURES_EAX_HWP_NOTIFY              = 1 << 8,
+    CPUID_FEATURES_EAX_HWP_ACT_WINDOW          = 1 << 9,
+    CPUID_FEATURES_EAX_HWP_EPP                 = 1 << 10,
+    CPUID_FEATURES_EAX_HWP_PKG_REQ             = 1 << 11,
+    CPUID_FEATURES_EAX_HWP_HIGHEST_PERF_CHANGE = 1 << 15,
+    CPUID_FEATURES_EAX_HFI                     = 1 << 19
+} CPUID_FEATURES_LEAF6, *PCPUID_FEATURES_LEAF6;
+
 /* CPUID STD1 features (0x00000001) enumeration list */
 typedef enum _CPUID_FEATURES_STANDARD1
 {
@@ -202,7 +236,7 @@ typedef enum _CPUID_FEATURES_STANDARD1
     CPUID_FEATURES_ECX_X2APIC                 = 1 << 21,
     CPUID_FEATURES_ECX_MOVBE                  = 1 << 22,
     CPUID_FEATURES_ECX_POPCNT                 = 1 << 23,
-    CPUID_FEATURES_ECX_TSC                    = 1 << 24,
+    CPUID_FEATURES_ECX_TSC_DEADLINE           = 1 << 24,
     CPUID_FEATURES_ECX_AES                    = 1 << 25,
     CPUID_FEATURES_ECX_XSAVE                  = 1 << 26,
     CPUID_FEATURES_ECX_OSXSAVE                = 1 << 27,
@@ -376,16 +410,23 @@ typedef enum _CPUID_FEATURES_STANDARD7_LEAF1
 /* CPUID requests */
 typedef enum _CPUID_REQUESTS
 {
-    CPUID_GET_VENDOR_STRING,
-    CPUID_GET_STANDARD1_FEATURES,
-    CPUID_GET_TLB_CACHE,
-    CPUID_GET_SERIAL,
-    CPUID_GET_CACHE_TOPOLOGY,
-    CPUID_GET_MONITOR_MWAIT,
-    CPUID_GET_POWER_MANAGEMENT,
-    CPUID_GET_STANDARD7_FEATURES
+    CPUID_GET_VENDOR_STRING                   = 0x00000000,
+    CPUID_GET_STANDARD1_FEATURES              = 0x00000001,
+    CPUID_GET_TLB_CACHE                       = 0x00000002,
+    CPUID_GET_SERIAL                          = 0x00000003,
+    CPUID_GET_CACHE_TOPOLOGY                  = 0x00000004,
+    CPUID_GET_MONITOR_MWAIT                   = 0x00000005,
+    CPUID_GET_POWER_MANAGEMENT                = 0x00000006,
+    CPUID_GET_STANDARD7_FEATURES              = 0x00000007,
+    CPUID_GET_TSC_CRYSTAL_CLOCK               = 0x00000015,
+    CPUID_GET_EXTENDED_MAX                    = 0x80000000,
+    CPUID_GET_EXTENDED_FEATURES               = 0x80000001,
+    CPUID_GET_ADVANCED_POWER_MANAGEMENT       = 0x80000007
 } CPUID_REQUESTS, *PCPUID_REQUESTS;
 
+/* Interrupt handler */
+typedef VOID (*PINTERRUPT_HANDLER)(PKTRAP_FRAME TrapFrame);
+
 /* Processor identification information */
 typedef struct _CPU_IDENTIFICATION
 {
@@ -426,4 +467,5 @@ typedef enum _TRAMPOLINE_TYPE
     TrampolineEnableXpa
 } TRAMPOLINE_TYPE, *PTRAMPOLINE_TYPE;
 
+#endif /* __XTOS_ASSEMBLER__ */
 #endif /* __XTDK_AMD64_ARTYPES_H */

sdk/xtdk/amd64/hlfuncs.h

@@ -15,6 +15,9 @@
 #include <amd64/xtstruct.h>
 
 
+/* C/C++ specific code */
+#ifndef __XTOS_ASSEMBLER__
+
 /* Hardware layer routines forward references */
 XTCLINK
 XTCDECL
@@ -49,4 +52,5 @@ VOID
 HlWritePort32(IN USHORT Port,
               IN ULONG Value);
 
+#endif /* __XTOS_ASSEMBLER__ */
 #endif /* __XTDK_AMD64_HLFUNCS_H */

sdk/xtdk/amd64/hltypes.h

@@ -9,6 +9,7 @@
 #ifndef __XTDK_AMD64_HLTYPES_H
 #define __XTDK_AMD64_HLTYPES_H
 
+#include <xtbase.h>
 #include <xtdefs.h>
 #include <xtstruct.h>
 #include <xttypes.h>
@@ -53,6 +54,27 @@
 /* Maximum number of I/O APICs */
 #define APIC_MAX_IOAPICS                                64
 
+/* I/O APIC base address */
+#define IOAPIC_DEFAULT_BASE                             0xFEC00000
+
+/* I/O APIC definitions */
+#define IOAPIC_MAX_CONTROLLERS                          128
+#define IOAPIC_MAX_OVERRIDES                            16
+#define IOAPIC_RTE_MASKED                               0x100FF
+#define IOAPIC_RTE_SIZE                                 2
+#define IOAPIC_VECTOR_FREE                              0xFF
+#define IOAPIC_VECTOR_RESERVED                          0xFE
+
+/* IOAPIC offsets */
+#define IOAPIC_IOREGSEL                                 0x00
+#define IOAPIC_IOWIN                                    0x10
+
+/* IOAPIC registers */
+#define IOAPIC_ID                                       0x00
+#define IOAPIC_VER                                      0x01
+#define IOAPIC_ARB                                      0x02
+#define IOAPIC_REDTBL                                   0x10
+
 /* 8259/ISP PIC ports definitions */
 #define PIC1_CONTROL_PORT                               0x20
 #define PIC1_DATA_PORT                                  0x21
@@ -62,6 +84,10 @@
 /* PIC vector definitions */
 #define PIC1_VECTOR_SPURIOUS                            0x37
 
+/* PIT ports definitions */
+#define PIT_COMMAND_PORT                                0x43
+#define PIT_DATA_PORT0                                  0x40
+
 /* Serial ports information */
 #define COMPORT_ADDRESS                                 {0x3F8, 0x2F8, 0x3E8, 0x2E8, 0x5F8, 0x4F8, 0x5E8, 0x4E8}
 #define COMPORT_COUNT                                   8
@@ -69,6 +95,17 @@
 /* Initial stall factor */
 #define INITIAL_STALL_FACTOR                            100
 
+
+/* C/C++ specific code */
+#ifndef __XTOS_ASSEMBLER__
+
+/* APIC destination mode enumeration list */
+typedef enum _APIC_DEST_MODE
+{
+    APIC_DM_Physical,
+    APIC_DM_Logical
+} APIC_DEST_MODE, *PAPIC_DEST_MODE;
+
 /* APIC delivery mode enumeration list */
 typedef enum _APIC_DM
 {
@@ -126,6 +163,7 @@ typedef enum _APIC_REGISTER
     APIC_TICR     = 0x38, /* Initial Count Register for Timer */
     APIC_TCCR     = 0x39, /* Current Count Register for Timer */
     APIC_TDCR     = 0x3E, /* Timer Divide Configuration Register */
+    APIC_SIPI     = 0x3F, /* Self-IPI Register */
     APIC_EAFR     = 0x40, /* extended APIC Feature register */
     APIC_EACR     = 0x41, /* Extended APIC Control Register */
     APIC_SEOI     = 0x42, /* Specific End Of Interrupt Register */
@@ -135,6 +173,19 @@ typedef enum _APIC_REGISTER
     APIC_EXT3LVTR = 0x53  /* Extended Interrupt 3 Local Vector Table */
 } APIC_REGISTER, *PAPIC_REGISTER;
 
+/* APIC Timer Divide enumeration list */
+typedef enum _APIC_TIMER_DIVISOR
+{
+    TIMER_DivideBy2   = 0,
+    TIMER_DivideBy4   = 1,
+    TIMER_DivideBy8   = 2,
+    TIMER_DivideBy16  = 3,
+    TIMER_DivideBy32  = 8,
+    TIMER_DivideBy64  = 9,
+    TIMER_DivideBy128 = 10,
+    TIMER_DivideBy1   = 11,
+} APIC_TIMER_DIVISOR, *PAPIC_TIMER_DIVISOR;
+
 /* I8259 PIC interrupt mode enumeration list */
 typedef enum _PIC_I8259_ICW1_INTERRUPT_MODE
 {
@@ -252,6 +303,40 @@ typedef union _APIC_SPURIOUS_REGISTER
     };
 } APIC_SPURIOUS_REGISTER, *PAPIC_SPURIOUS_REGISTER;
 
+/* I/O APIC Controller information */
+typedef struct _IOAPIC_DATA
+{
+    ULONG GsiBase;
+    ULONG Identifier;
+    ULONG LineCount;
+    PHYSICAL_ADDRESS PhysicalAddress;
+    ULONG_PTR VirtualAddress;
+} IOAPIC_DATA, *PIOAPIC_DATA;
+
+/* I/O APIC Redirection Register */
+typedef union _IOAPIC_REDIRECTION_REGISTER
+{
+    ULONGLONG LongLong;
+    struct
+    {
+        UINT Base;
+        UINT Extended;
+    };
+    struct
+    {
+        ULONGLONG Vector:8;
+        ULONGLONG DeliveryMode:3;
+        ULONGLONG DestinationMode:1;
+        ULONGLONG DeliveryStatus:1;
+        ULONGLONG PinPolarity:1;
+        ULONGLONG RemoteIRR:1;
+        ULONGLONG TriggerMode:1;
+        ULONGLONG Mask:1;
+        ULONGLONG Reserved:39;
+        ULONGLONG Destination:8;
+    };
+} IOAPIC_REDIRECTION_REGISTER, *PIOAPIC_REDIRECTION_REGISTER;
+
 /* I8259 PIC register structure */
 typedef union _PIC_I8259_ICW1
 {
@@ -317,4 +402,17 @@ typedef union _PIC_I8259_ICW4
     UCHAR Bits;
 } PIC_I8259_ICW4, *PPIC_I8259_ICW4;
 
+typedef struct _TIMER_CAPABILITIES
+{
+    BOOLEAN Arat;
+    BOOLEAN Art;
+    BOOLEAN InvariantTsc;
+    BOOLEAN RDTSCP;
+    ULONG TimerFrequency;
+    BOOLEAN TscDeadline;
+    ULONG TscDenominator;
+    ULONG TscNumerator;
+} TIMER_CAPABILITIES, *PTIMER_CAPABILITIES;
+
+#endif /* __XTOS_ASSEMBLER__ */
 #endif /* __XTDK_AMD64_HLTYPES_H */

sdk/xtdk/amd64/ketypes.h

@@ -23,6 +23,7 @@
 
 /* GDT selector names */
 #define KGDT_NULL                                 0x0000
+#define KGDT_R0_CMCODE                            0x0008
 #define KGDT_R0_CODE                              0x0010
 #define KGDT_R0_DATA                              0x0018
 #define KGDT_R3_CMCODE                            0x0020
@@ -46,7 +47,7 @@
 #define KGDT_DESCRIPTOR_CODE                      0x08
 
 /* GDT descriptor type codes */
-#define KGDT_TYPE_NONE                            0x0
+#define KGDT_TYPE_NONE                            0x00
 #define KGDT_TYPE_CODE                            (0x10 | KGDT_DESCRIPTOR_CODE | KGDT_DESCRIPTOR_EXECUTE_READ)
 #define KGDT_TYPE_DATA                            (0x10 | KGDT_DESCRIPTOR_READ_WRITE)
 
@@ -58,6 +59,7 @@
 #define KIDT_IST_RESERVED                         0
 #define KIDT_IST_PANIC                            1
 #define KIDT_IST_MCA                              2
+#define KIDT_IST_NMI                              3
 
 /* AMD64 Segment Types */
 #define AMD64_TASK_GATE                           0x5
@@ -108,11 +110,9 @@
 /* Static Kernel-Mode address start */
 #define KSEG0_BASE                        0xFFFFF80000000000
 
-/* XTOS Kernel address base */
-#define KSEG0_KERNEL_BASE                 0x0000000800000000
-
 /* XTOS Kernel stack size */
 #define KERNEL_STACK_SIZE                 0x8000
+#define KERNEL_STACKS                     3
 
 /* XTOS Kernel stack guard pages */
 #define KERNEL_STACK_GUARD_PAGES          1
@@ -138,6 +138,10 @@
 #define NPX_STATE_SCRUB                   0x1
 #define NPX_STATE_SWITCH                  0x2
 
+
+/* C/C++ specific code */
+#ifndef __XTOS_ASSEMBLER__
+
 /* Floating point state storing structure */
 typedef struct _FLOATING_SAVE_AREA
 {
@@ -272,11 +276,18 @@ typedef struct _KIDTENTRY
 {
     USHORT OffsetLow;
     USHORT Selector;
-    USHORT IstIndex:3;
-    USHORT Reserved0:5;
-    USHORT Type:5;
-    USHORT Dpl:2;
-    USHORT Present:1;
+    union
+    {
+        struct
+        {
+            USHORT IstIndex:3;
+            USHORT Reserved0:5;
+            USHORT Type:5;
+            USHORT Dpl:2;
+            USHORT Present:1;
+        };
+        USHORT Access;
+    };
     USHORT OffsetMiddle;
     ULONG OffsetHigh;
     ULONG Reserved1;
@@ -512,6 +523,7 @@ typedef struct _KPROCESSOR_BLOCK
     KAFFINITY SetMember;
     ULONG StallScaleFactor;
     UCHAR CpuNumber;
+    PINTERRUPT_HANDLER InterruptDispatchTable[256];
 } KPROCESSOR_BLOCK, *PKPROCESSOR_BLOCK;
 
 /* Thread Environment Block (TEB) structure definition */
@@ -520,4 +532,5 @@ typedef struct _THREAD_ENVIRONMENT_BLOCK
     THREAD_INFORMATION_BLOCK InformationBlock;
 } THREAD_ENVIRONMENT_BLOCK, *PTHREAD_ENVIRONMENT_BLOCK;
 
+#endif /* __XTOS_ASSEMBLER__ */
 #endif /* __XTDK_AMD64_KETYPES_H */

sdk/xtdk/amd64/mmtypes.h

@@ -25,11 +25,11 @@
 #define MM_PXE_BASE                                0xFFFFF6FB7DBED000ULL
 
 /* Page directory and page base addresses for 5-level paging */
-#define MM_PTE_LA57_BASE                           0xFFFF000000000000ULL
-#define MM_PDE_LA57_BASE                           0xFFFF010000000000ULL
-#define MM_PPE_LA57_BASE                           0xFFFF010800000000ULL
-#define MM_PXE_LA57_BASE                           0xFFFF010840000000ULL
-#define MM_P5E_LA57_BASE                           0xFFFF010840200000ULL
+#define MM_PTE_LA57_BASE                           0xFFED000000000000ULL
+#define MM_PDE_LA57_BASE                           0xFFEDF68000000000ULL
+#define MM_PPE_LA57_BASE                           0xFFEDF6FB40000000ULL
+#define MM_PXE_LA57_BASE                           0xFFEDF6FB7DA00000ULL
+#define MM_P5E_LA57_BASE                           0xFFEDF6FB7DBED000ULL
 
 /* PTE shift values */
 #define MM_PTE_SHIFT                               3
@@ -39,15 +39,56 @@
 #define MM_PXI_SHIFT                               39
 #define MM_P5I_SHIFT                               48
 
-/* Number of PTEs per page */
-#define MM_PTE_PER_PAGE                            512
-#define MM_PDE_PER_PAGE                            512
-#define MM_PPE_PER_PAGE                            512
-#define MM_PXE_PER_PAGE                            512
+/* PTE state flags */
+#define MM_PTE_VALID                               0x0000000000000001ULL
+#define MM_PTE_ACCESSED                            0x0000000000000020ULL
+#define MM_PTE_DIRTY                               0x0000000000000040ULL
+
+/* PTE scope flags */
+#define MM_PTE_LARGE_PAGE                          0x0000000000000080ULL
+#define MM_PTE_GLOBAL                              0x0000000000000100ULL
+
+/* PTE access flags */
+#define MM_PTE_NOACCESS                            0x0000000000000000ULL
+#define MM_PTE_READONLY                            0x0000000000000000ULL
+#define MM_PTE_EXECUTE                             0x0000000000000000ULL
+#define MM_PTE_EXECUTE_READ                        0x0000000000000000ULL
+#define MM_PTE_READWRITE                           0x8000000000000002ULL
+#define MM_PTE_WRITECOPY                           0x8000000000000200ULL
+#define MM_PTE_EXECUTE_READWRITE                   0x0000000000000002ULL
+#define MM_PTE_EXECUTE_WRITECOPY                   0x0000000000000200ULL
+
+/* PTE protection flags */
+#define MM_PTE_NOEXECUTE                           0x8000000000000000ULL
+#define MM_PTE_GUARDED                             0x8000000000000018ULL
+#define MM_PTE_PROTECT                             0x8000000000000612ULL
+
+/* PTE cache flags */
+#define MM_PTE_CACHE_ENABLE                        0x0000000000000000ULL
+#define MM_PTE_CACHE_DISABLE                       0x0000000000000010ULL
+#define MM_PTE_CACHE_WRITECOMBINED                 0x0000000000000010ULL
+#define MM_PTE_CACHE_WRITETHROUGH                  0x0000000000000008ULL
+
+/* PTE software flags */
+#define MM_PTE_COPY_ON_WRITE                       0x0000000000000200ULL
+#define MM_PTE_PROTOTYPE                           0x0000000000000400ULL
+#define MM_PTE_TRANSITION                          0x0000000000000800ULL
+
+/* PTE frame bits */
+#define MM_PTE_FRAME_BITS                          57
+
+/* PTE protection bits */
+#define MM_PTE_PROTECTION_BITS                     5
+
+/* Base address of the system page table */
+#define MM_SYSTEM_PTE_BASE                         KSEG0_BASE
 
 /* Minimum number of physical pages needed by the system */
 #define MM_MINIMUM_PHYSICAL_PAGES                  2048
 
+/* Number of system PTEs */
+#define MM_DEFAULT_NUMBER_SYSTEM_PTES              22000
+
 /* Default number of secondary colors */
 #define MM_DEFAULT_SECONDARY_COLORS                64
 
@@ -63,9 +104,25 @@
 /* Maximum physical address used by HAL allocations */
 #define MM_MAXIMUM_PHYSICAL_ADDRESS                0x00000000FFFFFFFFULL
 
+/* Highest system address */
+#define MM_HIGHEST_SYSTEM_ADDRESS                  0xFFFFFFFFFFFFFFFFULL
+
 /* Trampoline code address */
 #define MM_TRAMPOLINE_ADDRESS                      0x80000
 
+/* Pool block size */
+#define MM_POOL_BLOCK_SIZE                         16
+
+/* Number of pool lists per page */
+#define MM_POOL_LISTS_PER_PAGE                     (MM_PAGE_SIZE / MM_POOL_BLOCK_SIZE)
+
+/* Number of pool tracking tables */
+#define MM_POOL_TRACKING_TABLES                    64
+
+
+/* C/C++ specific code */
+#ifndef __XTOS_ASSEMBLER__
+
 /* Page size enumeration list */
 typedef enum _PAGE_SIZE
 {
@@ -252,6 +309,7 @@ typedef struct _MMPFN
             USHORT ReferenceCount;
         } e2;
     } u3;
+    ULONG UsedPageTableEntries;
     union
     {
         MMPTE OriginalPte;
@@ -262,15 +320,33 @@ typedef struct _MMPFN
         ULONG_PTR EntireFrame;
         struct
         {
-            ULONG_PTR PteFrame:58;
+            ULONG_PTR PteFrame:57;
             ULONG_PTR InPageError:1;
             ULONG_PTR VerifierAllocation:1;
             ULONG_PTR AweAllocation:1;
-            ULONG_PTR LockCharged:1;
-            ULONG_PTR KernelStack:1;
+            ULONG_PTR Priority:3;
             ULONG_PTR MustBeCached:1;
         };
     } u4;
 } MMPFN, *PMMPFN;
 
+/* Pool descriptor structure definition */
+typedef struct _POOL_DESCRIPTOR
+{
+    LIST_ENTRY ListHeads[MM_POOL_LISTS_PER_PAGE];
+    PVOID LockAddress;
+    ULONG PoolIndex;
+    LONG PendingFreeDepth;
+    PVOID PendingFrees;
+    MMPOOL_TYPE PoolType;
+    ULONG RunningFrees;
+    ULONG RunningAllocations;
+    ULONG Threshold;
+    ULONG TotalPages;
+    ULONG TotalBigAllocations;
+    SIZE_T TotalBytes;
+    SIZE_T Reserved;
+} POOL_DESCRIPTOR, *PPOOL_DESCRIPTOR;
+
+#endif /* __XTOS_ASSEMBLER__ */
 #endif /* __XTDK_AMD64_MMTYPES_H */

sdk/xtdk/amd64/xtstruct.h

@@ -12,13 +12,20 @@
 #include <xtdefs.h>
 
 
+/* C/C++ specific code */
+#ifndef __XTOS_ASSEMBLER__
+
 /* Architecture-specific enumeration lists forward references */
+typedef enum _APIC_DEST_MODE APIC_DEST_MODE, *PAPIC_DEST_MODE;
 typedef enum _APIC_DM APIC_DM, *PAPIC_DM;
 typedef enum _APIC_DSH APIC_DSH, *PAPIC_DSH;
 typedef enum _APIC_MODE APIC_MODE, *PAPIC_MODE;
 typedef enum _APIC_REGISTER APIC_REGISTER, *PAPIC_REGISTER;
+typedef enum _APIC_TIMER_DIVISOR APIC_TIMER_DIVISOR, *PAPIC_TIMER_DIVISOR;
 typedef enum _CPU_VENDOR CPU_VENDOR, *PCPU_VENDOR;
+typedef enum _CPUID_FEATURES_ADVANCED_POWER_MANAGEMENT CPUID_FEATURES_ADVANCED_POWER_MANAGEMENT, *PCPUID_FEATURES_ADVANCED_POWER_MANAGEMENT;
 typedef enum _CPUID_FEATURES_EXTENDED CPUID_FEATURES_EXTENDED, *PCPUID_FEATURES_EXTENDED;
+typedef enum _CPUID_FEATURES_POWER_MANAGEMENT CPUID_FEATURES_POWER_MANAGEMENT, *PCPUID_FEATURES_POWER_MANAGEMENT;
 typedef enum _CPUID_FEATURES_STANDARD1 CPUID_FEATURES_STANDARD1, *PCPUID_FEATURES_STANDARD1;
 typedef enum _CPUID_FEATURES_STANDARD7_LEAF0 CPUID_FEATURES_STANDARD7_LEAF0, *PCPUID_FEATURES_STANDARD7_LEAF0;
 typedef enum _CPUID_FEATURES_STANDARD7_LEAF1 CPUID_FEATURES_STANDARD7_LEAF1, *PCPUID_FEATURES_STANDARD7_LEAF1;
@@ -39,6 +46,7 @@ typedef struct _CPUID_REGISTERS CPUID_REGISTERS, *PCPUID_REGISTERS;
 typedef struct _CPUID_SIGNATURE CPUID_SIGNATURE, *PCPUID_SIGNATURE;
 typedef struct _FLOATING_SAVE_AREA FLOATING_SAVE_AREA, *PFLOATING_SAVE_AREA;
 typedef struct _HARDWARE_PTE HARDWARE_PTE, *PHARDWARE_PTE;
+typedef struct _IOAPIC_DATA IOAPIC_DATA, *PIOAPIC_DATA;
 typedef struct _KDESCRIPTOR KDESCRIPTOR, *PKDESCRIPTOR;
 typedef struct _KEXCEPTION_FRAME KEXCEPTION_FRAME, *PKEXCEPTION_FRAME;
 typedef struct _KGDTENTRY KGDTENTRY, *PKGDTENTRY;
@@ -61,13 +69,16 @@ typedef struct _MMPTE_PROTOTYPE MMPTE_PROTOTYPE, *PMMPTE_PROTOTYPE;
 typedef struct _MMPTE_SOFTWARE MMPTE_SOFTWARE, *PMMPTE_SOFTWARE;
 typedef struct _MMPTE_SUBSECTION MMPTE_SUBSECTION, *PMMPTE_SUBSECTION;
 typedef struct _MMPTE_TRANSITION MMPTE_TRANSITION, *PMMPTE_TRANSITION;
+typedef struct _POOL_DESCRIPTOR POOL_DESCRIPTOR, *PPOOL_DESCRIPTOR;
 typedef struct _THREAD_ENVIRONMENT_BLOCK THREAD_ENVIRONMENT_BLOCK, *PTHREAD_ENVIRONMENT_BLOCK;
+typedef struct _TIMER_CAPABILITIES TIMER_CAPABILITIES, *PTIMER_CAPABILITIES;
 
 /* Unions forward references */
 typedef union _APIC_BASE_REGISTER APIC_BASE_REGISTER, *PAPIC_BASE_REGISTER;
 typedef union _APIC_COMMAND_REGISTER APIC_COMMAND_REGISTER, *PAPIC_COMMAND_REGISTER;
 typedef union _APIC_LVT_REGISTER APIC_LVT_REGISTER, *PAPIC_LVT_REGISTER;
 typedef union _APIC_SPURIOUS_REGISTER APIC_SPURIOUS_REGISTER, *PAPIC_SPURIOUS_REGISTER;
+typedef union _IOAPIC_REDIRECTION_REGISTER IOAPIC_REDIRECTION_REGISTER, *PIOAPIC_REDIRECTION_REGISTER;
 typedef union _MMPTE MMP5E, *PMMP5E;
 typedef union _MMPTE MMPDE, *PMMPDE;
 typedef union _MMPTE MMPPE, *PMMPPE;
@@ -78,4 +89,5 @@ typedef union _PIC_I8259_ICW2 PIC_I8259_ICW2, *PPIC_I8259_ICW2;
 typedef union _PIC_I8259_ICW3 PIC_I8259_ICW3, *PPIC_I8259_ICW3;
 typedef union _PIC_I8259_ICW4 PIC_I8259_ICW4, *PPIC_I8259_ICW4;
 
+#endif /* __XTOS_ASSEMBLER__ */
 #endif /* __XTDK_AMD64_XTSTRUCT_H */

sdk/xtdk/blfuncs.h

@@ -13,6 +13,9 @@
 #include <xtuefi.h>
 
 
+/* C/C++ specific code */
+#ifndef D__XTOS_ASSEMBLER__
+
 /* XT BootLoader routines forward references */
 XTCLINK
 XTCDECL
@@ -21,4 +24,5 @@ BlGetXtLdrProtocol(IN PEFI_SYSTEM_TABLE SystemTable,
                    IN EFI_HANDLE ImageHandle,
                    OUT PXTBL_LOADER_PROTOCOL *ProtocolHandler);
 
+#endif /* __XTOS_ASSEMBLER__ */
 #endif /* __XTDK_BLFUNCS_H */

sdk/xtdk/bltypes.h

@@ -41,6 +41,10 @@
 /* TUI dialog box maximum width */
 #define XTBL_TUI_MAX_DIALOG_WIDTH                                   100
 
+
+/* C/C++ specific code */
+#ifndef D__XTOS_ASSEMBLER__
+
 /* XTLDR Routine pointers */
 typedef LOADER_MEMORY_TYPE (XTCDECL *PBL_GET_MEMTYPE_ROUTINE)(IN EFI_MEMORY_TYPE EfiMemoryType);
 
@@ -51,6 +55,7 @@ typedef EFI_STATUS (XTCDECL *PBL_BOOTMENU_INITIALIZE_OS_LIST)(IN ULONG MaxNameLe
 typedef BOOLEAN (XTCDECL *PBL_BOOTUTILS_GET_BOOLEAN_PARAMETER)(IN PCWSTR Parameters, IN PCWSTR Needle);
 typedef VOID (XTAPI *PBL_BOOTUTILS_GET_TRAMPOLINE_INFORMATION)(IN TRAMPOLINE_TYPE TrampolineType, OUT PVOID *TrampolineCode, OUT PULONG_PTR TrampolineSize);
 typedef EFI_STATUS (XTCDECL *PBL_BUILD_PAGE_MAP)(IN PXTBL_PAGE_MAPPING PageMap, IN ULONG_PTR SelfMapAddress);
+typedef EFI_STATUS (XTCDECL *PBL_COMMIT_PAGE_MAP)(IN PXTBL_PAGE_MAPPING PageMap);
 typedef EFI_STATUS (XTCDECL *PBL_CLOSE_VOLUME)(IN PEFI_HANDLE VolumeHandle);
 typedef VOID (XTCDECL *PBL_CLEAR_CONSOLE_LINE)(IN ULONGLONG LineNo);
 typedef BOOLEAN (XTCDECL *PBL_CPU_CPUID)(IN OUT PCPUID_REGISTERS Registers);
@@ -100,9 +105,9 @@ typedef VOID (XTCDECL *PBL_LLIST_INITIALIZE_HEAD)(IN PLIST_ENTRY ListHead);
 typedef VOID (XTCDECL *PBL_LLIST_INSERT_HEAD)(IN OUT PLIST_ENTRY ListHead, IN PLIST_ENTRY Entry);
 typedef VOID (XTCDECL *PBL_LLIST_INSERT_TAIL)(IN OUT PLIST_ENTRY ListHead, IN PLIST_ENTRY Entry);
 typedef VOID (XTCDECL *PBL_LLIST_REMOVE_ENTRY)(IN PLIST_ENTRY Entry);
-typedef EFI_STATUS (XTCDECL *PBL_MAP_EFI_MEMORY)(IN OUT PXTBL_PAGE_MAPPING PageMap, IN OUT PVOID *MemoryMapAddress, IN PBL_GET_MEMTYPE_ROUTINE GetMemoryTypeRoutine);
-typedef EFI_STATUS (XTCDECL *PBL_MAP_PAGE)(IN PXTBL_PAGE_MAPPING PageMap, IN ULONG_PTR VirtualAddress, IN ULONG_PTR PhysicalAddress, IN ULONG NumberOfPages);
-typedef EFI_STATUS (XTCDECL *PBL_MAP_VIRTUAL_MEMORY)(IN OUT PXTBL_PAGE_MAPPING PageMap, IN PVOID VirtualAddress, IN PVOID PhysicalAddress, IN ULONGLONG NumberOfPages, IN LOADER_MEMORY_TYPE MemoryType);
+typedef EFI_STATUS (XTCDECL *PBL_MAP_EFI_MEMORY)(IN OUT PXTBL_PAGE_MAPPING PageMap, IN OUT PVOID *BaseAddress, IN BOOLEAN IdentityMapping, IN PBL_GET_MEMTYPE_ROUTINE GetMemoryTypeRoutine);
+typedef EFI_STATUS (XTCDECL *PBL_MAP_PAGE)(IN PXTBL_PAGE_MAPPING PageMap, IN ULONGLONG VirtualAddress, IN ULONGLONG PhysicalAddress, IN ULONGLONG NumberOfPages);
+typedef EFI_STATUS (XTCDECL *PBL_MAP_VIRTUAL_MEMORY)(IN OUT PXTBL_PAGE_MAPPING PageMap, IN ULONGLONG VirtualAddress, IN ULONGLONG PhysicalAddress, IN ULONGLONG NumberOfPages, IN LOADER_MEMORY_TYPE MemoryType);
 typedef VOID (XTAPI *PBL_MOVE_MEMORY)(IN OUT PVOID Destination, IN PCVOID Source, IN SIZE_T Length);
 typedef EFI_STATUS (XTCDECL *PBL_OPEN_VOLUME)(IN PEFI_DEVICE_PATH_PROTOCOL DevicePath, OUT PEFI_HANDLE DiskHandle, OUT PEFI_FILE_HANDLE *FsHandle);
 typedef EFI_STATUS (XTCDECL *PBL_OPEN_PROTOCOL)(OUT PEFI_HANDLE Handle, OUT PVOID *ProtocolHandler, IN PEFI_GUID ProtocolGuid);
@@ -232,8 +237,8 @@ typedef struct _XTBL_KNOWN_BOOT_PROTOCOL
 typedef struct _XTBL_MEMORY_MAPPING
 {
     LIST_ENTRY ListEntry;
-    PVOID VirtualAddress;
-    PVOID PhysicalAddress;
+    ULONGLONG VirtualAddress;
+    ULONGLONG PhysicalAddress;
     ULONGLONG NumberOfPages;
     LOADER_MEMORY_TYPE MemoryType;
 } XTBL_MEMORY_MAPPING, *PXTBL_MEMORY_MAPPING;
@@ -449,6 +454,7 @@ typedef struct _XTBL_LOADER_PROTOCOL
         PBL_ALLOCATE_PAGES AllocatePages;
         PBL_ALLOCATE_POOL AllocatePool;
         PBL_BUILD_PAGE_MAP BuildPageMap;
+        PBL_COMMIT_PAGE_MAP CommitPageMap;
         PBL_COMPARE_MEMORY CompareMemory;
         PBL_COPY_MEMORY CopyMemory;
         PBL_FREE_PAGES FreePages;
@@ -518,4 +524,5 @@ typedef struct _XTBL_LOADER_PROTOCOL
     } WideString;
 } XTBL_LOADER_PROTOCOL, *PXTBL_LOADER_PROTOCOL;
 
+#endif /* __XTOS_ASSEMBLER__ */
 #endif /* __XTDK_BLTYPES_H */

sdk/xtdk/exfuncs.h

@@ -13,6 +13,9 @@
 #include <xttypes.h>
 
 
+/* C/C++ specific code */
+#ifndef __XTOS_ASSEMBLER__
+
 /* Kernel Executive routines forward references */
 XTCLINK
 XTFASTCALL
@@ -44,4 +47,5 @@ XTFASTCALL
 VOID
 ExWaitForRundownProtectionRelease(IN PEX_RUNDOWN_REFERENCE Descriptor);
 
+#endif /* __XTOS_ASSEMBLER__ */
 #endif /* __XTDK_EXFUNCS_H */

sdk/xtdk/extypes.h

@@ -17,6 +17,10 @@
 /* Rundown protection flags */
 #define EX_RUNDOWN_ACTIVE                               0x1
 
+
+/* C/C++ specific code */
+#ifndef __XTOS_ASSEMBLER__
+
 /* Executive rundown protection structure definition */
 typedef struct _EX_RUNDOWN_REFERENCE
 {
@@ -34,4 +38,5 @@ typedef struct _EX_RUNDOWN_WAIT_BLOCK
     KEVENT WakeEvent;
 } EX_RUNDOWN_WAIT_BLOCK, *PEX_RUNDOWN_WAIT_BLOCK;
 
+#endif /* __XTOS_ASSEMBLER__ */
 #endif /* __XTDK_EXTYPES_H */

sdk/xtdk/hlfuncs.h

@@ -14,6 +14,9 @@
 #include <xttypes.h>
 
 
+/* C/C++ specific code */
+#ifndef __XTOS_ASSEMBLER__
+
 /* Hardware layer routines forward references */
 XTCLINK
 XTAPI
@@ -48,4 +51,5 @@ VOID
 HlWriteRegister32(IN PVOID Register,
                   IN ULONG Value);
 
+#endif /* __XTOS_ASSEMBLER__ */
 #endif /* __XTDK_HLFUNCS_H */

sdk/xtdk/hltypes.h

@@ -101,6 +101,12 @@
 #define ACPI_MADT_PLACE_ENABLED                     0 /* Processor Local APIC CPU Enabled */
 #define ACPI_MADT_PLAOC_ENABLED                     1 /* Processor Local APIC Online Capable */
 
+/* ACPI address space definitions */
+#define ACPI_ADDRESS_SPACE_MEMORY                   0x00
+
+/* Maximum number of cached ACPI tables */
+#define ACPI_MAX_CACHED_TABLES                      32
+
 /* Default serial port settings */
 #define COMPORT_CLOCK_RATE                          0x1C200
 #define COMPORT_WAIT_TIMEOUT                        204800
@@ -179,6 +185,14 @@
 #define COMPORT_REG_MSR                             0x06 /* Modem Status Register */
 #define COMPORT_REG_SR                              0x07 /* Scratch Register */
 
+/* Minimum and maximum profile intervals */
+#define MIN_PROFILE_INTERVAL 1000
+#define MAX_PROFILE_INTERVAL 10000000
+
+
+/* C/C++ specific code */
+#ifndef __XTOS_ASSEMBLER__
+
 /* Generic Address structure */
 typedef struct _GENERIC_ADDRESS
 {
@@ -214,7 +228,7 @@ typedef struct _ACPI_SUBTABLE_HEADER
 typedef struct _ACPI_CACHE_LIST
 {
     LIST_ENTRY ListEntry;
-    ACPI_DESCRIPTION_HEADER Header;
+    PACPI_DESCRIPTION_HEADER Table;
 } ACPI_CACHE_LIST, *PACPI_CACHE_LIST;
 
 /* ACPI Root System Description Table Pointer (RSDP) structure */
@@ -305,6 +319,17 @@ typedef struct _ACPI_FADT
     GENERIC_ADDRESS SleepStatusReg;
 } PACKED ACPI_FADT, *PACPI_FADT;
 
+/* ACPI High Precision Event Timer (HPET) table structure */
+typedef struct _ACPI_HPET
+{
+    ACPI_DESCRIPTION_HEADER Header;
+    ULONG EventTimerBlockId;
+    GENERIC_ADDRESS BaseAddress;
+    UCHAR HpetNumber;
+    USHORT MinimumTick;
+    UCHAR PageProtectionAndOem;
+} PACKED ACPI_HPET, *PACPI_HPET;
+
 /* ACPI Multiple APIC Description Table (MADT) structure */
 typedef struct _ACPI_MADT
 {
@@ -314,6 +339,26 @@ typedef struct _ACPI_MADT
     ULONG ApicTables[];
 } PACKED ACPI_MADT, *PACPI_MADT;
 
+/* ACPI Interrupt Override MADT subtable structure */
+typedef struct _ACPI_MADT_INTERRUPT_OVERRIDE
+{
+    ACPI_SUBTABLE_HEADER Header;
+    UCHAR Bus;
+    UCHAR SourceIrq;
+    ULONG GlobalSystemInterrupt;
+    USHORT Flags;
+} PACKED ACPI_MADT_INTERRUPT_OVERRIDE, *PACPI_MADT_INTERRUPT_OVERRIDE;
+
+/* ACPI IO APIC MADT subtable structure */
+typedef struct _ACPI_MADT_IOAPIC
+{
+    ACPI_SUBTABLE_HEADER Header;
+    UCHAR IoApicId;
+    UCHAR Reserved;
+    ULONG IoApicAddress;
+    ULONG GlobalIrqBase;
+} PACKED ACPI_MADT_IOAPIC, *PACPI_MADT_IOAPIC;
+
 /* ACPI Local APIC MADT subtable structure */
 typedef struct _ACPI_MADT_LOCAL_APIC
 {
@@ -450,4 +495,5 @@ typedef struct _SMBIOS3_TABLE_HEADER
     ULONGLONG TableAddress;
 } SMBIOS3_TABLE_HEADER, *PSMBIOS3_TABLE_HEADER;
 
+#endif /* __XTOS_ASSEMBLER__ */
 #endif /* __XTDK_HLTYPES_H */

sdk/xtdk/i686/artypes.h

@@ -12,6 +12,7 @@
 #include <xtdefs.h>
 #include <xtstruct.h>
 #include <xttypes.h>
+#include ARCH_HEADER(xtstruct.h)
 
 
 /* Control Register 0 constants */
@@ -92,6 +93,10 @@
 #define X86_EFLAGS_VIP_MASK                             0x00100000 /* Virtual Interrupt Pending */
 #define X86_EFLAGS_ID_MASK                              0x00200000 /* Identification */
 
+
+/* C/C++ specific code */
+#ifndef __XTOS_ASSEMBLER__
+
 /* CPU vendor enumeration list */
 typedef enum _CPU_VENDOR
 {
@@ -100,6 +105,18 @@ typedef enum _CPU_VENDOR
     CPU_VENDOR_UNKNOWN = 0xFFFFFFFF
 } CPU_VENDOR, *PCPU_VENDOR;
 
+/* CPUID advanced power management features (0x80000007) enumeration list */
+typedef enum _CPUID_FEATURES_ADVANCED_POWER_MANAGEMENT
+{
+    CPUID_FEATURES_EDX_TS                     = 1 << 0, /* Temperature Sensor */
+    CPUID_FEATURES_EDX_FIS                    = 1 << 1, /* Frequency ID Selection */
+    CPUID_FEATURES_EDX_VIS                    = 1 << 2, /* Voltage ID Selection */
+    CPUID_FEATURES_EDX_TTS                    = 1 << 3, /* ThermaTrip Support */
+    CPUID_FEATURES_EDX_HTC                    = 1 << 4, /* Hardware Thermal Throttling */
+    CPUID_FEATURES_EDX_STC                    = 1 << 5, /* Software Thermal Throttling */
+    CPUID_FEATURES_EDX_TSCI                   = 1 << 8 /* TSC Invariant */
+} CPUID_FEATURES_ADVANCED_POWER_MANAGEMENT, *PCPUID_FEATURES_ADVANCED_POWER_MANAGEMENT;
+
 /* CPUID extended features (0x80000001) enumeration list */
 typedef enum _CPUID_FEATURES_EXTENDED
 {
@@ -141,6 +158,23 @@ typedef enum _CPUID_FEATURES_EXTENDED
     CPUID_FEATURES_EDX_3DNOW                  = 1 << 31
 } CPUID_FEATURES_EXTENDED, *PCPUID_FEATURES_EXTENDED;
 
+/* CPUID Thermal and Power Management features (0x00000006) enumeration list */
+typedef enum _CPUID_FEATURES_POWER_MANAGEMENT
+{
+    CPUID_FEATURES_EAX_DTHERM                  = 1 << 0,
+    CPUID_FEATURES_EAX_IDA                     = 1 << 1,
+    CPUID_FEATURES_EAX_ARAT                    = 1 << 2,
+    CPUID_FEATURES_EAX_PLN                     = 1 << 4,
+    CPUID_FEATURES_EAX_PTS                     = 1 << 6,
+    CPUID_FEATURES_EAX_HWP                     = 1 << 7,
+    CPUID_FEATURES_EAX_HWP_NOTIFY              = 1 << 8,
+    CPUID_FEATURES_EAX_HWP_ACT_WINDOW          = 1 << 9,
+    CPUID_FEATURES_EAX_HWP_EPP                 = 1 << 10,
+    CPUID_FEATURES_EAX_HWP_PKG_REQ             = 1 << 11,
+    CPUID_FEATURES_EAX_HWP_HIGHEST_PERF_CHANGE = 1 << 15,
+    CPUID_FEATURES_EAX_HFI                     = 1 << 19
+} CPUID_FEATURES_LEAF6, *PCPUID_FEATURES_LEAF6;
+
 /* CPUID STD1 features (0x00000001) enumeration list */
 typedef enum _CPUID_FEATURES_STANDARD1
 {
@@ -167,7 +201,7 @@ typedef enum _CPUID_FEATURES_STANDARD1
     CPUID_FEATURES_ECX_X2APIC                 = 1 << 21,
     CPUID_FEATURES_ECX_MOVBE                  = 1 << 22,
     CPUID_FEATURES_ECX_POPCNT                 = 1 << 23,
-    CPUID_FEATURES_ECX_TSC                    = 1 << 24,
+    CPUID_FEATURES_ECX_TSC_DEADLINE           = 1 << 24,
     CPUID_FEATURES_ECX_AES                    = 1 << 25,
     CPUID_FEATURES_ECX_XSAVE                  = 1 << 26,
     CPUID_FEATURES_ECX_OSXSAVE                = 1 << 27,
@@ -341,16 +375,23 @@ typedef enum _CPUID_FEATURES_STANDARD7_LEAF1
 /* CPUID requests */
 typedef enum _CPUID_REQUESTS
 {
-    CPUID_GET_VENDOR_STRING,
-    CPUID_GET_STANDARD1_FEATURES,
-    CPUID_GET_TLB_CACHE,
-    CPUID_GET_SERIAL,
-    CPUID_GET_CACHE_TOPOLOGY,
-    CPUID_GET_MONITOR_MWAIT,
-    CPUID_GET_POWER_MANAGEMENT,
-    CPUID_GET_STANDARD7_FEATURES
+    CPUID_GET_VENDOR_STRING                   = 0x00000000,
+    CPUID_GET_STANDARD1_FEATURES              = 0x00000001,
+    CPUID_GET_TLB_CACHE                       = 0x00000002,
+    CPUID_GET_SERIAL                          = 0x00000003,
+    CPUID_GET_CACHE_TOPOLOGY                  = 0x00000004,
+    CPUID_GET_MONITOR_MWAIT                   = 0x00000005,
+    CPUID_GET_POWER_MANAGEMENT                = 0x00000006,
+    CPUID_GET_STANDARD7_FEATURES              = 0x00000007,
+    CPUID_GET_TSC_CRYSTAL_CLOCK               = 0x00000015,
+    CPUID_GET_EXTENDED_MAX                    = 0x80000000,
+    CPUID_GET_EXTENDED_FEATURES               = 0x80000001,
+    CPUID_GET_ADVANCED_POWER_MANAGEMENT       = 0x80000007
 } CPUID_REQUESTS, *PCPUID_REQUESTS;
 
+/* Interrupt handler */
+typedef VOID (*PINTERRUPT_HANDLER)(PKTRAP_FRAME TrapFrame);
+
 /* Processor identification information */
 typedef struct _CPU_IDENTIFICATION
 {
@@ -390,4 +431,5 @@ typedef enum _TRAMPOLINE_TYPE
     TrampolineApStartup
 } TRAMPOLINE_TYPE, *PTRAMPOLINE_TYPE;
 
+#endif /* __XTOS_ASSEMBLER__ */
 #endif /* __XTDK_I686_ARTYPES_H */

sdk/xtdk/i686/hlfuncs.h

@@ -15,6 +15,9 @@
 #include <i686/xtstruct.h>
 
 
+/* C/C++ specific code */
+#ifndef __XTOS_ASSEMBLER__
+
 /* Hardware layer routines forward references */
 XTCLINK
 XTCDECL
@@ -49,4 +52,5 @@ VOID
 HlWritePort32(IN USHORT Port,
               IN ULONG Value);
 
+#endif /* __XTOS_ASSEMBLER__ */
 #endif /* __XTDK_I686_HLFUNCS_H */

sdk/xtdk/i686/hltypes.h

@@ -9,6 +9,7 @@
 #ifndef __XTDK_I686_HLTYPES_H
 #define __XTDK_I686_HLTYPES_H
 
+#include <xtbase.h>
 #include <xtdefs.h>
 #include <xtstruct.h>
 #include <xttypes.h>
@@ -58,6 +59,27 @@
 /* Maximum number of I/O APICs */
 #define APIC_MAX_IOAPICS                                64
 
+/* I/O APIC base address */
+#define IOAPIC_DEFAULT_BASE                             0xFEC00000
+
+/* I/O APIC definitions */
+#define IOAPIC_MAX_CONTROLLERS                          64
+#define IOAPIC_MAX_OVERRIDES                            16
+#define IOAPIC_RTE_MASKED                               0x100FF
+#define IOAPIC_RTE_SIZE                                 2
+#define IOAPIC_VECTOR_FREE                              0xFF
+#define IOAPIC_VECTOR_RESERVED                          0xFE
+
+/* IOAPIC offsets */
+#define IOAPIC_IOREGSEL                                 0x00
+#define IOAPIC_IOWIN                                    0x10
+
+/* IOAPIC registers */
+#define IOAPIC_ID                                       0x00
+#define IOAPIC_VER                                      0x01
+#define IOAPIC_ARB                                      0x02
+#define IOAPIC_REDTBL                                   0x10
+
 /* 8259/ISP PIC ports definitions */
 #define PIC1_CONTROL_PORT                               0x20
 #define PIC1_DATA_PORT                                  0x21
@@ -69,6 +91,10 @@
 /* PIC vector definitions */
 #define PIC1_VECTOR_SPURIOUS                            0x37
 
+/* PIT ports definitions */
+#define PIT_COMMAND_PORT                                0x43
+#define PIT_DATA_PORT0                                  0x40
+
 /* Serial ports information */
 #define COMPORT_ADDRESS                                 {0x3F8, 0x2F8, 0x3E8, 0x2E8, 0x5F8, 0x4F8, 0x5E8, 0x4E8}
 #define COMPORT_COUNT                                   8
@@ -76,6 +102,17 @@
 /* Initial stall factor */
 #define INITIAL_STALL_FACTOR                            100
 
+
+/* C/C++ specific code */
+#ifndef __XTOS_ASSEMBLER__
+
+/* APIC destination mode enumeration list */
+typedef enum _APIC_DEST_MODE
+{
+    APIC_DM_Physical,
+    APIC_DM_Logical
+} APIC_DEST_MODE, *PAPIC_DEST_MODE;
+
 /* APIC delivery mode enumeration list */
 typedef enum _APIC_DM
 {
@@ -133,6 +170,7 @@ typedef enum _APIC_REGISTER
     APIC_TICR     = 0x38, /* Initial Count Register for Timer */
     APIC_TCCR     = 0x39, /* Current Count Register for Timer */
     APIC_TDCR     = 0x3E, /* Timer Divide Configuration Register */
+    APIC_SIPI     = 0x3F, /* Self-IPI Register */
     APIC_EAFR     = 0x40, /* extended APIC Feature register */
     APIC_EACR     = 0x41, /* Extended APIC Control Register */
     APIC_SEOI     = 0x42, /* Specific End Of Interrupt Register */
@@ -142,6 +180,19 @@ typedef enum _APIC_REGISTER
     APIC_EXT3LVTR = 0x53  /* Extended Interrupt 3 Local Vector Table */
 } APIC_REGISTER, *PAPIC_REGISTER;
 
+/* APIC Timer Divide enumeration list */
+typedef enum _APIC_TIMER_DIVISOR
+{
+    TIMER_DivideBy2   = 0,
+    TIMER_DivideBy4   = 1,
+    TIMER_DivideBy8   = 2,
+    TIMER_DivideBy16  = 3,
+    TIMER_DivideBy32  = 8,
+    TIMER_DivideBy64  = 9,
+    TIMER_DivideBy128 = 10,
+    TIMER_DivideBy1   = 11,
+} APIC_TIMER_DIVISOR, *PAPIC_TIMER_DIVISOR;
+
 /* I8259 PIC interrupt mode enumeration list */
 typedef enum _PIC_I8259_ICW1_INTERRUPT_MODE
 {
@@ -259,6 +310,40 @@ typedef union _APIC_SPURIOUS_REGISTER
     };
 } APIC_SPURIOUS_REGISTER, *PAPIC_SPURIOUS_REGISTER;
 
+/* I/O APIC Controller information */
+typedef struct _IOAPIC_DATA
+{
+    ULONG GsiBase;
+    ULONG Identifier;
+    ULONG LineCount;
+    PHYSICAL_ADDRESS PhysicalAddress;
+    ULONG_PTR VirtualAddress;
+} IOAPIC_DATA, *PIOAPIC_DATA;
+
+/* I/O APIC Redirection Register */
+typedef union _IOAPIC_REDIRECTION_REGISTER
+{
+    ULONGLONG LongLong;
+    struct
+    {
+        UINT Base;
+        UINT Extended;
+    };
+    struct
+    {
+        ULONGLONG Vector:8;
+        ULONGLONG DeliveryMode:3;
+        ULONGLONG DestinationMode:1;
+        ULONGLONG DeliveryStatus:1;
+        ULONGLONG PinPolarity:1;
+        ULONGLONG RemoteIRR:1;
+        ULONGLONG TriggerMode:1;
+        ULONGLONG Mask:1;
+        ULONGLONG Reserved:39;
+        ULONGLONG Destination:8;
+    };
+} IOAPIC_REDIRECTION_REGISTER, *PIOAPIC_REDIRECTION_REGISTER;
+
 /* I8259 PIC register structure */
 typedef union _PIC_I8259_ICW1
 {
@@ -324,4 +409,18 @@ typedef union _PIC_I8259_ICW4
     UCHAR Bits;
 } PIC_I8259_ICW4, *PPIC_I8259_ICW4;
 
+/* Timer Capabilities */
+typedef struct _TIMER_CAPABILITIES
+{
+    BOOLEAN Arat;
+    BOOLEAN Art;
+    BOOLEAN InvariantTsc;
+    BOOLEAN RDTSCP;
+    ULONG TimerFrequency;
+    BOOLEAN TscDeadline;
+    ULONG TscDenominator;
+    ULONG TscNumerator;
+} TIMER_CAPABILITIES, *PTIMER_CAPABILITIES;
+
+#endif /* __XTOS_ASSEMBLER__ */
 #endif /* __XTDK_I686_HLTYPES_H */

sdk/xtdk/i686/ketypes.h

@@ -50,7 +50,7 @@
 #define KGDT_DESCRIPTOR_CODE              0x08
 
 /* GDT descriptor type codes */
-#define KGDT_TYPE_NONE                    0x0
+#define KGDT_TYPE_NONE                    0x00
 #define KGDT_TYPE_CODE                    (0x10 | KGDT_DESCRIPTOR_CODE | KGDT_DESCRIPTOR_EXECUTE_READ)
 #define KGDT_TYPE_DATA                    (0x10 | KGDT_DESCRIPTOR_READ_WRITE)
 
@@ -58,12 +58,6 @@
 #define KIDT_ACCESS_RING0                 0x00
 #define KIDT_ACCESS_RING3                 0x60
 
-/* IDT gate types */
-#define KIDT_TASK                         0x05
-#define KIDT_CALL                         0x0C
-#define KIDT_INTERRUPT                    0x0E
-#define KIDT_TRAP                         0x0F
-
 /* TSS Offsets */
 #define KTSS_ESP0                         0x04
 #define KTSS_CR3                          0x1C
@@ -88,6 +82,7 @@
 #define KTSS_IO_MAPS                      0x68
 
 /* I686 Segment Types */
+#define I686_LDT                          0x2
 #define I686_TASK_GATE                    0x5
 #define I686_TSS                          0x9
 #define I686_ACTIVE_TSS                   0xB
@@ -134,11 +129,9 @@
 /* Static Kernel-Mode address start */
 #define KSEG0_BASE                        0x80000000
 
-/* XTOS Kernel address base */
-#define KSEG0_KERNEL_BASE                 0x01800000
-
 /* XTOS Kernel stack size */
 #define KERNEL_STACK_SIZE                 0x4000
+#define KERNEL_STACKS                     3
 
 /* XTOS Kernel stack guard pages */
 #define KERNEL_STACK_GUARD_PAGES          1
@@ -166,6 +159,10 @@
 #define NPX_STATE_LOADED                  0x0
 #define NPX_STATE_UNLOADED                0xA
 
+
+/* C/C++ specific code */
+#ifndef __XTOS_ASSEMBLER__
+
 /* Floating point state storing structure */
 typedef struct _FN_SAVE_FORMAT
 {
@@ -284,7 +281,18 @@ typedef struct _KIDTENTRY
 {
     USHORT Offset;
     USHORT Selector;
-    USHORT Access;
+    union
+    {
+        struct
+        {
+            UCHAR Reserved;
+            UCHAR Type:4;
+            UCHAR Flag:1;
+            UCHAR Dpl:2;
+            UCHAR Present:1;
+        };
+        USHORT Access;
+    };
     USHORT ExtendedOffset;
 } KIDTENTRY, *PKIDTENTRY;
 
@@ -470,6 +478,7 @@ typedef struct _KPROCESSOR_BLOCK
     KAFFINITY SetMember;
     ULONG StallScaleFactor;
     UCHAR CpuNumber;
+    PINTERRUPT_HANDLER InterruptDispatchTable[256];
 } KPROCESSOR_BLOCK, *PKPROCESSOR_BLOCK;
 
 /* Thread Environment Block (TEB) structure definition */
@@ -478,4 +487,5 @@ typedef struct _THREAD_ENVIRONMENT_BLOCK
     THREAD_INFORMATION_BLOCK InformationBlock;
 } THREAD_ENVIRONMENT_BLOCK, *PTHREAD_ENVIRONMENT_BLOCK;
 
+#endif /* __XTOS_ASSEMBLER__ */
 #endif /* __XTDK_I686_KETYPES_H */

sdk/xtdk/i686/mmtypes.h

@@ -35,9 +35,58 @@
 #define MM_PTE_LEGACY_SHIFT                        2
 #define MM_PDI_LEGACY_SHIFT                        22
 
+/* PTE state flags */
+#define MM_PTE_VALID                               0x00000001
+#define MM_PTE_ACCESSED                            0x00000020
+#define MM_PTE_DIRTY                               0x00000040
+
+/* PTE scope flags */
+#define MM_PTE_LARGE_PAGE                          0x00000080
+#define MM_PTE_GLOBAL                              0x00000100
+
+/* PTE access flags */
+#define MM_PTE_NOACCESS                            0x00000000
+#define MM_PTE_READONLY                            0x00000000
+#define MM_PTE_EXECUTE                             0x00000000
+#define MM_PTE_EXECUTE_READ                        0x00000000
+#define MM_PTE_READWRITE                           0x00000002
+#define MM_PTE_WRITECOPY                           0x00000200
+#define MM_PTE_EXECUTE_READWRITE                   0x00000002
+#define MM_PTE_EXECUTE_WRITECOPY                   0x00000200
+
+/* PTE protection flags */
+#define MM_PTE_NOEXECUTE                           0x00000000
+#define MM_PTE_GUARDED                             0x00000018
+#define MM_PTE_PROTECT                             0x00000612
+
+/* PTE cache flags */
+#define MM_PTE_CACHE_ENABLE                        0x00000000
+#define MM_PTE_CACHE_DISABLE                       0x00000010
+#define MM_PTE_CACHE_WRITECOMBINED                 0x00000010
+#define MM_PTE_CACHE_WRITETHROUGH                  0x00000008
+
+/* PTE software flags */
+#define MM_PTE_COPY_ON_WRITE                       0x00000200
+#define MM_PTE_PROTOTYPE                           0x00000400
+#define MM_PTE_TRANSITION                          0x00000800
+
+/* PTE frame bits */
+#define MM_PTE_FRAME_BITS                          25
+
+/* PTE protection bits */
+#define MM_PTE_PROTECTION_BITS                     5
+
+/* Base address of the system page table */
+#define MM_SYSTEM_PTE_BASE                         NULLPTR
+
 /* Minimum number of physical pages needed by the system */
 #define MM_MINIMUM_PHYSICAL_PAGES                  1100
 
+/* Number of system PTEs */
+#define MM_MINIMUM_NUMBER_SYSTEM_PTES              7000
+#define MM_DEFAULT_NUMBER_SYSTEM_PTES              11000
+#define MM_MAXIMUM_NUMBER_SYSTEM_PTES              22000
+
 /* Default number of secondary colors */
 #define MM_DEFAULT_SECONDARY_COLORS                64
 
@@ -53,9 +102,25 @@
 /* Maximum physical address used by HAL allocations */
 #define MM_MAXIMUM_PHYSICAL_ADDRESS                0xFFFFFFFF
 
+/* Highest system address */
+#define MM_HIGHEST_SYSTEM_ADDRESS                  0xFFFFFFFF
+
 /* Trampoline code address */
 #define MM_TRAMPOLINE_ADDRESS                      0x80000
 
+/* Pool block size */
+#define MM_POOL_BLOCK_SIZE                         8
+
+/* Number of pool lists per page */
+#define MM_POOL_LISTS_PER_PAGE                     (MM_PAGE_SIZE / MM_POOL_BLOCK_SIZE)
+
+/* Number of pool tracking tables */
+#define MM_POOL_TRACKING_TABLES                    32
+
+
+/* C/C++ specific code */
+#ifndef __XTOS_ASSEMBLER__
+
 /* Page size enumeration list */
 typedef enum _PAGE_SIZE
 {
@@ -106,7 +171,6 @@ typedef struct _HARDWARE_MODERN_PTE
 /* Generic Page Table entry union to abstract PML2 and PML3 formats */
 typedef union _HARDWARE_PTE
 {
-    ULONGLONG Long;
     HARDWARE_LEGACY_PTE Pml2;
     HARDWARE_MODERN_PTE Pml3;
 } HARDWARE_PTE, *PHARDWARE_PTE;
@@ -201,12 +265,12 @@ typedef struct _MMPML2_PTE_TRANSITION
 typedef union _MMPML2_PTE
 {
     ULONG Long;
-    HARDWARE_PTE Flush;
-    MMPML2_PTE_HARDWARE Hard;
-    MMPML2_PTE_PROTOTYPE Proto;
-    MMPML2_PTE_SOFTWARE Soft;
-    MMPML2_PTE_TRANSITION Trans;
-    MMPML2_PTE_SUBSECTION Subsect;
+    HARDWARE_LEGACY_PTE Flush;
+    MMPML2_PTE_HARDWARE Hardware;
+    MMPML2_PTE_PROTOTYPE Prototype;
+    MMPML2_PTE_SOFTWARE Software;
+    MMPML2_PTE_TRANSITION Transition;
+    MMPML2_PTE_SUBSECTION Subsection;
     MMPML2_PTE_LIST List;
 } MMPML2_PTE, *PMMPML2_PTE;
 
@@ -296,7 +360,7 @@ typedef struct _MMPML3_PTE_TRANSITION
 typedef union _MMPML3_PTE
 {
     ULONGLONG Long;
-    HARDWARE_PTE Flush;
+    HARDWARE_MODERN_PTE Flush;
     MMPML3_PTE_HARDWARE Hardware;
     MMPML3_PTE_PROTOTYPE Prototype;
     MMPML3_PTE_SOFTWARE Software;
@@ -308,7 +372,6 @@ typedef union _MMPML3_PTE
 /* Generic Page Table Entry union to abstract PML2 and PML3 formats */
 typedef union _MMPTE
 {
-    ULONGLONG Long;
     MMPML2_PTE Pml2;
     MMPML3_PTE Pml3;
 } MMPTE, *PMMPTE;
@@ -339,6 +402,7 @@ typedef struct _MMPFN
             USHORT ReferenceCount;
         } e2;
     } u3;
+    ULONG UsedPageTableEntries;
     union
     {
         MMPTE OriginalPte;
@@ -349,15 +413,33 @@ typedef struct _MMPFN
         ULONG_PTR EntireFrame;
         struct
         {
-            ULONG_PTR PteFrame:26;
+            ULONG_PTR PteFrame:25;
             ULONG_PTR InPageError:1;
             ULONG_PTR VerifierAllocation:1;
             ULONG_PTR AweAllocation:1;
-            ULONG_PTR LockCharged:1;
-            ULONG_PTR KernelStack:1;
+            ULONG_PTR Priority:3;
             ULONG_PTR MustBeCached:1;
         };
     } u4;
 } MMPFN, *PMMPFN;
 
+/* Pool descriptor structure definition */
+typedef struct _POOL_DESCRIPTOR
+{
+    LIST_ENTRY ListHeads[MM_POOL_LISTS_PER_PAGE];
+    PVOID LockAddress;
+    ULONG PoolIndex;
+    LONG PendingFreeDepth;
+    PVOID PendingFrees;
+    MMPOOL_TYPE PoolType;
+    ULONG RunningFrees;
+    ULONG RunningAllocations;
+    ULONG Threshold;
+    ULONG TotalPages;
+    ULONG TotalBigAllocations;
+    SIZE_T TotalBytes;
+    SIZE_T Reserved;
+} POOL_DESCRIPTOR, *PPOOL_DESCRIPTOR;
+
+#endif /* __XTOS_ASSEMBLER__ */
 #endif /* __XTDK_I686_MMTYPES_H */

sdk/xtdk/i686/xtstruct.h

@@ -12,13 +12,20 @@
 #include <xtdefs.h>
 
 
+/* C/C++ specific code */
+#ifndef __XTOS_ASSEMBLER__
+
 /* Architecture-specific enumeration lists forward references */
+typedef enum _APIC_DEST_MODE APIC_DEST_MODE, *PAPIC_DEST_MODE;
 typedef enum _APIC_DM APIC_DM, *PAPIC_DM;
 typedef enum _APIC_DSH APIC_DSH, *PAPIC_DSH;
 typedef enum _APIC_MODE APIC_MODE, *PAPIC_MODE;
 typedef enum _APIC_REGISTER APIC_REGISTER, *PAPIC_REGISTER;
+typedef enum _APIC_TIMER_DIVISOR APIC_TIMER_DIVISOR, *PAPIC_TIMER_DIVISOR;
 typedef enum _CPU_VENDOR CPU_VENDOR, *PCPU_VENDOR;
+typedef enum _CPUID_FEATURES_ADVANCED_POWER_MANAGEMENT CPUID_FEATURES_ADVANCED_POWER_MANAGEMENT, *PCPUID_FEATURES_ADVANCED_POWER_MANAGEMENT;
 typedef enum _CPUID_FEATURES_EXTENDED CPUID_FEATURES_EXTENDED, *PCPUID_FEATURES_EXTENDED;
+typedef enum _CPUID_FEATURES_POWER_MANAGEMENT CPUID_FEATURES_POWER_MANAGEMENT, *PCPUID_FEATURES_POWER_MANAGEMENT;
 typedef enum _CPUID_FEATURES_STANDARD1 CPUID_FEATURES_STANDARD1, *PCPUID_FEATURES_STANDARD1;
 typedef enum _CPUID_FEATURES_STANDARD7_LEAF0 CPUID_FEATURES_STANDARD7_LEAF0, *PCPUID_FEATURES_STANDARD7_LEAF0;
 typedef enum _CPUID_FEATURES_STANDARD7_LEAF1 CPUID_FEATURES_STANDARD7_LEAF1, *PCPUID_FEATURES_STANDARD7_LEAF1;
@@ -42,6 +49,7 @@ typedef struct _FX_SAVE_AREA FX_SAVE_AREA, *PFX_SAVE_AREA;
 typedef struct _FX_SAVE_FORMAT FX_SAVE_FORMAT, *PFX_SAVE_FORMAT;
 typedef struct _HARDWARE_LEGACY_PTE HARDWARE_LEGACY_PTE, *PHARDWARE_LEGACY_PTE;
 typedef struct _HARDWARE_MODERN_PTE HARDWARE_MODERN_PTE, *PHARDWARE_MODERN_PTE;
+typedef struct _IOAPIC_DATA IOAPIC_DATA, *PIOAPIC_DATA;
 typedef struct _KDESCRIPTOR KDESCRIPTOR, *PKDESCRIPTOR;
 typedef struct _KEXCEPTION_FRAME KEXCEPTION_FRAME, *PKEXCEPTION_FRAME;
 typedef struct _KGDTENTRY KGDTENTRY, *PKGDTENTRY;
@@ -70,7 +78,9 @@ typedef struct _MMPML3_PTE_PROTOTYPE MMPML3_PTE_PROTOTYPE, *PMMPML3_PTE_PROTOTYP
 typedef struct _MMPML3_PTE_SOFTWARE MMPML3_PTE_SOFTWARE, *PMMPML3_PTE_SOFTWARE;
 typedef struct _MMPML3_PTE_SUBSECTION MMPML3_PTE_SUBSECTION, *PMMPML3_PTE_SUBSECTION;
 typedef struct _MMPML3_PTE_TRANSITION MMPML3_PTE_TRANSITION, *PMMPML3_PTE_TRANSITION;
+typedef struct _POOL_DESCRIPTOR POOL_DESCRIPTOR, *PPOOL_DESCRIPTOR;
 typedef struct _THREAD_ENVIRONMENT_BLOCK THREAD_ENVIRONMENT_BLOCK, *PTHREAD_ENVIRONMENT_BLOCK;
+typedef struct _TIMER_CAPABILITIES TIMER_CAPABILITIES, *PTIMER_CAPABILITIES;
 
 /* Unions forward references */
 typedef union _APIC_BASE_REGISTER APIC_BASE_REGISTER, *PAPIC_BASE_REGISTER;
@@ -78,6 +88,7 @@ typedef union _APIC_COMMAND_REGISTER APIC_COMMAND_REGISTER, *PAPIC_COMMAND_REGIS
 typedef union _APIC_LVT_REGISTER APIC_LVT_REGISTER, *PAPIC_LVT_REGISTER;
 typedef union _APIC_SPURIOUS_REGISTER APIC_SPURIOUS_REGISTER, *PAPIC_SPURIOUS_REGISTER;
 typedef union _HARDWARE_PTE HARDWARE_PTE, *PHARDWARE_PTE;
+typedef union _IOAPIC_REDIRECTION_REGISTER IOAPIC_REDIRECTION_REGISTER, *PIOAPIC_REDIRECTION_REGISTER;
 typedef union _MMPML2_PTE MMPML2_PTE, *PMMPML2_PTE;
 typedef union _MMPML3_PTE MMPML3_PTE, *PMMPML3_PTE;
 typedef union _MMPTE MMPDE, *PMMPDE;
@@ -88,4 +99,5 @@ typedef union _PIC_I8259_ICW2 PIC_I8259_ICW2, *PPIC_I8259_ICW2;
 typedef union _PIC_I8259_ICW3 PIC_I8259_ICW3, *PPIC_I8259_ICW3;
 typedef union _PIC_I8259_ICW4 PIC_I8259_ICW4, *PPIC_I8259_ICW4;
 
+#endif /* __XTOS_ASSEMBLER__ */
 #endif /* __XTDK_I686_XTSTRUCT_H */

sdk/xtdk/iotypes.h

@@ -58,6 +58,10 @@
 #define PCI_STATUS_SIGNALED_SYSTEM_ERROR        0x4000
 #define PCI_STATUS_DETECTED_PARITY_ERROR        0x8000
 
+
+/* C/C++ specific code */
+#ifndef __XTOS_ASSEMBLER__
+
 /* PCI bridge control registers */
 typedef struct _PCI_BRIDGE_CONTROL_REGISTER
 {
@@ -214,4 +218,5 @@ typedef struct _PCI_TYPE1_DEVICE
     PCI_BRIDGE_CONTROL_REGISTER Bridge;
 } PCI_TYPE1_DEVICE, *PPCI_TYPE1_DEVICE;
 
+#endif /* __XTOS_ASSEMBLER__ */
 #endif /* __XTDK_IOTYPES_H */

sdk/xtdk/kdfuncs.h

@@ -13,6 +13,9 @@
 #include <xttypes.h>
 
 
+/* C/C++ specific code */
+#ifndef __XTOS_ASSEMBLER__
+
 /* Kernel debugger routines forward references */
 XTCLINK
 XTCDECL
@@ -20,4 +23,5 @@ VOID
 DbgPrint(PCWSTR Format,
          ...);
 
+#endif /* __XTOS_ASSEMBLER__ */
 #endif /* __XTDK_KDFUNCS_H */

sdk/xtdk/kdtypes.h

@@ -21,6 +21,10 @@
 #define DEBUG_PROVIDER_COMPORT                              0x00000001
 #define DEBUG_PROVIDER_FRAMEBUFFER                          0x00000002
 
+
+/* C/C++ specific code */
+#ifndef __XTOS_ASSEMBLER__
+
 /* Kernel routine callbacks */
 typedef XTSTATUS (XTAPI *PKD_INIT_ROUTINE)();
 typedef VOID (*PKD_PRINT_ROUTINE)(IN PCWSTR Format, IN ...);
@@ -42,4 +46,5 @@ typedef struct _KD_DISPATCH_TABLE
     RTL_PRINT_CONTEXT PrintContext;
 } KD_DISPATCH_TABLE, *PKD_DISPATCH_TABLE;
 
+#endif /* __XTOS_ASSEMBLER__ */
 #endif /* __XTDK_KDTYPES_H */

sdk/xtdk/kefuncs.h

@@ -15,6 +15,9 @@
 #include <ketypes.h>
 
 
+/* C/C++ specific code */
+#ifndef __XTOS_ASSEMBLER__
+
 /* Kernel services routines forward references */
 XTCLINK
 XTFASTCALL
@@ -159,4 +162,5 @@ XTAPI
 BOOLEAN
 KeSignalCallDpcSynchronize(IN PVOID SystemArgument);
 
+#endif /* __XTOS_ASSEMBLER__ */
 #endif /* __XTDK_KEFUNCS_H */

sdk/xtdk/ketypes.h

@@ -49,6 +49,10 @@
 #define THREAD_HIGH_PRIORITY                        31
 #define THREAD_MAXIMUM_PRIORITY                     32
 
+
+/* C/C++ specific code */
+#ifndef __XTOS_ASSEMBLER__
+
 /* Adjust reason */
 typedef enum _ADJUST_REASON
 {
@@ -133,6 +137,37 @@ typedef enum _KPROCESS_STATE
     ProcessOutSwap
 } KPROCESS_STATE, *PKPROCESS_STATE;
 
+/* Kernel profiling sources */
+typedef enum _KPROFILE_SOURCE
+{
+    ProfileTime,
+    ProfileAlignmentFixup,
+    ProfileTotalIssues,
+    ProfilePipelineDry,
+    ProfileLoadInstructions,
+    ProfilePipelineFrozen,
+    ProfileBranchInstructions,
+    ProfileTotalNonissues,
+    ProfileDcacheMisses,
+    ProfileIcacheMisses,
+    ProfileCacheMisses,
+    ProfileBranchMispredictions,
+    ProfileStoreInstructions,
+    ProfileFpInstructions,
+    ProfileIntegerInstructions,
+    Profile2Issue,
+    Profile3Issue,
+    Profile4Issue,
+    ProfileSpecialInstructions,
+    ProfileTotalCycles,
+    ProfileIcacheIssues,
+    ProfileDcacheAccesses,
+    ProfileMemoryBarrierCycles,
+    ProfileLoadLinkedIssues,
+    ProfileXtKernel,
+    ProfileMaximum
+} KPROFILE_SOURCE, *PKPROFILE_SOURCE;
+
 /* Thread state */
 typedef enum _KTHREAD_STATE
 {
@@ -150,21 +185,23 @@ typedef enum _KTHREAD_STATE
 typedef enum _KSPIN_LOCK_QUEUE_LEVEL
 {
     DispatcherLock,
-    UnusedSpareLock,
+    ExpansionLock,
     PfnLock,
     SystemSpaceLock,
     VacbLock,
     MasterLock,
-    NonPagedPoolLock,
+    NonPagedAllocPoolLock,
     IoCancelLock,
     WorkQueueLock,
     IoVpbLock,
     IoDatabaseLock,
     IoCompletionLock,
-    FsStructLock,
+    FileSystemLock,
     AfdWorkQueueLock,
     BcbLock,
-    MmNonPagedPoolLock,
+    NonPagedPoolLock,
+    ReservedSystemLock,
+    TimerTableLock,
     MaximumLock
 } KSPIN_LOCK_QUEUE_LEVEL, *PKSPIN_LOCK_QUEUE_LEVEL;
 
@@ -645,4 +682,5 @@ typedef struct _KUBSAN_TYPE_MISMATCH_DATA_V1
     UCHAR TypeCheckKind;
 } KUBSAN_TYPE_MISMATCH_DATA_V1, *PKUBSAN_TYPE_MISMATCH_DATA_V1;
 
+#endif /* __XTOS_ASSEMBLER__ */
 #endif /* __XTDK_KEFUNCS_H */

sdk/xtdk/ldrtypes.h

@@ -38,6 +38,10 @@
 #define LDR_DTE_MM_LOADED                          0x40000000
 #define LDR_DTE_COMPAT_DATABASE_PROCESSED          0x80000000
 
+
+/* C/C++ specific code */
+#ifndef __XTOS_ASSEMBLER__
+
 /* Loader data table entry */
 typedef struct _LDR_DATA_TABLE_ENTRY
 {
@@ -70,4 +74,5 @@ typedef struct _LDR_DATA_TABLE_ENTRY
     PVOID PatchInformation;
 } LDR_DATA_TABLE_ENTRY, *PLDR_DATA_TABLE_ENTRY;
 
+#endif /* __XTOS_ASSEMBLER__ */
 #endif /* __XTDK_LDRTYPES_H */

sdk/xtdk/mmfuncs.h

@@ -0,0 +1,44 @@
+/**
+ * PROJECT:         ExectOS
+ * COPYRIGHT:       See COPYING.md in the top level directory
+ * FILE:            sdk/xtdk/mmfuncs.h
+ * DESCRIPTION:     XTOS memory manager routine definitions
+ * DEVELOPERS:      Aiken Harris <harraiken91@gmail.com>
+ */
+
+#ifndef __XTDK_MMFUNCS_H
+#define __XTDK_MMFUNCS_H
+
+#include <xtdefs.h>
+#include <xtstruct.h>
+#include <xttypes.h>
+
+
+/* C/C++ specific code */
+#ifndef __XTOS_ASSEMBLER__
+
+/* Memory manager routines forward references */
+XTAPI
+XTSTATUS
+MmAllocatePool(IN MMPOOL_TYPE PoolType,
+               IN SIZE_T Bytes,
+               OUT PVOID *Memory);
+
+XTAPI
+XTSTATUS
+MmAllocatePoolWithTag(IN MMPOOL_TYPE PoolType,
+                      IN SIZE_T Bytes,
+                      OUT PVOID *Memory,
+                      IN ULONG Tag);
+
+XTAPI
+XTSTATUS
+MmFreePool(IN PVOID VirtualAddress);
+
+XTAPI
+XTSTATUS
+MmFreePoolWithTag(IN PVOID VirtualAddress,
+                  IN ULONG Tag);
+
+#endif /* __XTOS_ASSEMBLER__ */
+#endif /* __XTDK_MMFUNCS_H */

sdk/xtdk/mmtypes.h

@@ -4,6 +4,7 @@
  * FILE:            sdk/xtdk/mmtypes.h
  * DESCRIPTION:     Memory management data structures
  * DEVELOPERS:      Rafal Kupiec <belliash@codingworkshop.eu.org>
+ *                  Aiken Harris <harraiken91@gmail.com>
  */
 
 #ifndef __XTDK_MMTYPES_H
@@ -13,6 +14,99 @@
 #include ARCH_HEADER(xtstruct.h)
 
 
+/* Number of hyper space pages */
+#define MM_HYPERSPACE_PAGE_COUNT                   255
+
+/* Number of free page list heads */
+#define MM_MAX_FREE_PAGE_LIST_HEADS                4
+
+/* Number of paging colors */
+#define MM_PAGING_COLORS                           64
+
+/* PTE frame mask definition */
+#define MM_PFN_PTE_FRAME                           (((ULONG_PTR)1 << MM_PTE_FRAME_BITS) - 1)
+
+/* Memory manager pool type mask definition */
+#define MM_POOL_TYPE_MASK                          1
+
+/* Bad pool caller reasons */
+#define MM_POOL_INVALID_ALLOC_RUNLEVEL             8
+#define MM_POOL_INVALID_FREE_RUNLEVEL              9
+
+/* Pool flags */
+#define MM_POOL_BIG_ALLOCATIONS_ENTRY_FREE         0x1
+#define MM_POOL_PROTECTED                          0x80000000
+#define MM_POOL_RAISE_EXCEPTION                    0x10
+
+/* Number of reserved zeroed PTEs */
+#define MM_RESERVED_ZERO_PTES                      32
+
+/* Memory Manager Protection Bits */
+#define MM_ZERO_ACCESS                             0
+#define MM_READONLY                                1
+#define MM_EXECUTE                                 2
+#define MM_EXECUTE_READ                            3
+#define MM_READWRITE                               4
+#define MM_WRITECOPY                               5
+#define MM_EXECUTE_READWRITE                       6
+#define MM_EXECUTE_WRITECOPY                       7
+#define MM_PROTECT_ACCESS                          7
+
+/* Protection field shift */
+#define MM_PROTECT_FIELD_SHIFT                     5
+
+
+/* C/C++ specific code */
+#ifndef __XTOS_ASSEMBLER__
+
+/* Memory manager page lists */
+typedef enum _MMPAGELISTS
+{
+   ZeroedPageList = 0,
+   FreePageList = 1,
+   StandbyPageList = 2,
+   ModifiedPageList = 3,
+   ModifiedReadOnlyPageList = 4,
+   BadPageList = 5,
+   ActiveAndValid = 6,
+   TransitionPage = 7
+} MMPAGELISTS, *PMMPAGELISTS;
+
+/* Page cache attributes */
+typedef enum _MMPFN_CACHE_ATTRIBUTE
+{
+    PfnNonCached,
+    PfnCached,
+    PfnWriteCombined,
+    PfnNotMapped
+} MMPFN_CACHE_ATTRIBUTE, *PMMPFN_CACHE_ATTRIBUTE;
+
+/* Memory Manager pool types */
+typedef enum _MMPOOL_TYPE
+{
+    NonPagedPool = 0,
+    PagedPool = 1,
+    NonPagedPoolMustSucceed = 2,
+    NonPagedPoolCacheAligned = 4,
+    PagedPoolCacheAligned = 5,
+    NonPagedPoolCacheAlignedMustSucceed = 6,
+    MaxPoolType = 7,
+    NonPagedPoolSession = 32,
+    PagedPoolSession = 33,
+    NonPagedPoolMustSucceedSession = 34,
+    NonPagedPoolCacheAlignedSession = 36,
+    PagedPoolCacheAlignedSession = 37,
+    NonPagedPoolCacheAlignedMustSucceedSession = 38
+} MMPOOL_TYPE, *PMMPOOL_TYPE;
+
+/* Page table pool types */
+typedef enum _MMSYSTEM_PTE_POOL_TYPE
+{
+    SystemPteSpace,
+    NonPagedPoolExpansion,
+    MaximumPtePoolTypes
+} MMSYSTEM_PTE_POOL_TYPE, *PMMSYSTEM_PTE_POOL_TYPE;
+
 /* Page map routines structure definition */
 typedef CONST STRUCT _CMMPAGEMAP_ROUTINES
 {
@@ -30,6 +124,58 @@ typedef struct _MMCOLOR_TABLES
     ULONG_PTR Count;
 } MMCOLOR_TABLES, *PMMCOLOR_TABLES;
 
+/* Free pool entry structure definition */
+typedef struct _MMFREE_POOL_ENTRY
+{
+    LIST_ENTRY List;
+    PFN_COUNT Size;
+    PMMFREE_POOL_ENTRY Owner;
+} MMFREE_POOL_ENTRY, *PMMFREE_POOL_ENTRY;
+
+/* Memory layout structure definition */
+typedef struct _MMMEMORY_LAYOUT
+{
+    PMMPFN PfnDatabase;
+    PFN_NUMBER PfnDatabaseSize;
+    PVOID SelfMapAddress;
+    PVOID HardwarePoolStart;
+    PVOID HardwarePoolEnd;
+    PVOID HyperSpaceStart;
+    PVOID HyperSpaceEnd;
+    PVOID LoaderMappingsStart;
+    PVOID LoaderMappingsEnd;
+    PFN_NUMBER LoaderMappingsSize;
+    PVOID NonCanonicalStart;
+    PVOID NonCanonicalEnd;
+    PVOID NonPagedPoolStart;
+    PVOID NonPagedPoolEnd;
+    PFN_NUMBER NonPagedPoolSize;
+    PVOID NonPagedExpansionPoolStart;
+    PVOID NonPagedExpansionPoolEnd;
+    PFN_NUMBER NonPagedExpansionPoolSize;
+    PVOID NonPagedSystemPoolStart;
+    PVOID NonPagedSystemPoolEnd;
+    PFN_NUMBER NonPagedSystemPoolSize;
+    PVOID PagedPoolStart;
+    PVOID PagedPoolEnd;
+    PFN_NUMBER PagedPoolSize;
+    PVOID ReservedSystemPoolStart;
+    PVOID ReservedSystemPoolEnd;
+    PVOID SessionSpaceStart;
+    PVOID SessionSpaceEnd;
+    PFN_NUMBER SessionSpaceSize;
+    PVOID SharedSystemPageStart;
+    PVOID SharedSystemPageEnd;
+    PVOID SystemCacheStart;
+    PVOID SystemCacheEnd;
+    PVOID SystemWorkingSetStart;
+    PVOID SystemWorkingSetEnd;
+    PVOID UserSpaceStart;
+    PVOID UserSpaceEnd;
+    PVOID PteSpaceStart;
+    PVOID PteSpaceEnd;
+} MMMEMORY_LAYOUT, *PMMMEMORY_LAYOUT;
+
 /* Page Frame Entry structure definition */
 typedef struct _MMPFNENTRY
 {
@@ -45,4 +191,76 @@ typedef struct _MMPFNENTRY
     USHORT ParityError:1;
 } MMPFNENTRY, *PMMPFNENTRY;
 
+/* Page Frame List structure definition */
+typedef struct _MMPFNLIST
+{
+    PFN_NUMBER Total;
+    MMPAGELISTS ListName;
+    PFN_NUMBER Flink;
+    PFN_NUMBER Blink;
+} MMPFNLIST, *PMMPFNLIST;
+
+/* Physical memory run structure definition */
+typedef struct _PHYSICAL_MEMORY_RUN
+{
+    PFN_NUMBER BasePage;
+    PFN_NUMBER PageCount;
+} PHYSICAL_MEMORY_RUN, *PPHYSICAL_MEMORY_RUN;
+
+/* Physical memory descriptor structure definition */
+typedef struct _PHYSICAL_MEMORY_DESCRIPTOR
+{
+    ULONG NumberOfRuns;
+    PFN_NUMBER NumberOfPages;
+    PHYSICAL_MEMORY_RUN Run[1];
+} PHYSICAL_MEMORY_DESCRIPTOR, *PPHYSICAL_MEMORY_DESCRIPTOR;
+
+/* Pool header structure definition */
+typedef struct _POOL_HEADER
+{
+    union
+    {
+        struct
+        {
+            USHORT PreviousSize:9;
+            USHORT PoolIndex:7;
+            USHORT BlockSize:9;
+            USHORT PoolType:7;
+        };
+        ULONG Long;
+    };
+    union
+    {
+        ULONG PoolTag;
+        PEPROCESS ProcessBilled;
+        struct
+        {
+            USHORT AllocatorBackTraceIndex;
+            USHORT PoolTagHash;
+        };
+    };
+} POOL_HEADER, *PPOOL_HEADER;
+
+/* Pool descriptor structure definition */
+typedef struct _POOL_TRACKING_BIG_ALLOCATIONS
+{
+    ULONG NumberOfPages;
+    PVOID QuotaObject;
+    ULONG Tag;
+    PVOID VirtualAddress;
+} POOL_TRACKING_BIG_ALLOCATIONS, *PPOOL_TRACKING_BIG_ALLOCATIONS;
+
+/* Pool tracking table structure definition */
+typedef struct _POOL_TRACKING_TABLE
+{
+    LONG NonPagedAllocations;
+    SIZE_T NonPagedBytes;
+    LONG NonPagedFrees;
+    LONG PagedAllocations;
+    SIZE_T PagedBytes;
+    LONG PagedFrees;
+    ULONG Tag;
+} POOL_TRACKING_TABLE, *PPOOL_TRACKING_TABLE;
+
+#endif /* __XTOS_ASSEMBLER__ */
 #endif /* __XTDK_MMTYPES_H */

sdk/xtdk/potypes.h

@@ -14,6 +14,9 @@
 #include <ketypes.h>
 
 
+/* C/C++ specific code */
+#ifndef __XTOS_ASSEMBLER__
+
 /* Power Manager routine callbacks */
 typedef VOID (XTFASTCALL *PPROCESSOR_IDLE_FUNCTION)(IN PPROCESSOR_POWER_STATE PowerState);
 typedef XTSTATUS (XTFASTCALL *PSET_PROCESSOR_THROTTLE)(IN UCHAR Throttle);
@@ -88,4 +91,5 @@ typedef struct _PROCESSOR_POWER_STATE
     ULONG LastC3UserTime;
 } PROCESSOR_POWER_STATE, *PPROCESSOR_POWER_STATE;
 
+#endif /* __XTOS_ASSEMBLER__ */
 #endif /* __XTDK_POTYPES_H */

sdk/xtdk/pstypes.h

@@ -13,6 +13,9 @@
 #include <ketypes.h>
 
 
+/* C/C++ specific code */
+#ifndef __XTOS_ASSEMBLER__
+
 /* Kernel's representation of a process object */
 typedef struct _EPROCESS
 {
@@ -27,4 +30,5 @@ typedef struct _ETHREAD
     UINT Reserved0;
 } ETHREAD, *PETHREAD;
 
+#endif /* __XTOS_ASSEMBLER__ */
 #endif /* __XTDK_PSTYPES_H */

sdk/xtdk/rtlfuncs.h

@@ -15,6 +15,9 @@
 #include <rtltypes.h>
 
 
+/* C/C++ specific code */
+#ifndef __XTOS_ASSEMBLER__
+
 /* Runtime Library routines forward references */
 XTCLINK
 XTAPI
@@ -370,4 +373,5 @@ VOID
 RtlZeroMemory(OUT PVOID Destination,
               IN SIZE_T Length);
 
+#endif /* __XTOS_ASSEMBLER__ */
 #endif /* __XTDK_RTLFUNCS_H */

sdk/xtdk/rtltypes.h

@@ -49,6 +49,14 @@
 #define PFL_DIGIT_PRECISION             0x00002000
 #define PFL_THOUSANDS_GROUPING          0x00004000
 
+/* Cryptographic related definitions */
+#define SHA1_BLOCK_SIZE                 64
+#define SHA1_DIGEST_SIZE                20
+
+
+/* C/C++ specific code */
+#ifndef __XTOS_ASSEMBLER__
+
 /* Runtime Library routine callbacks */
 typedef XTSTATUS (*PWRITE_CHARACTER)(IN CHAR Character);
 typedef XTSTATUS (*PWRITE_WIDE_CHARACTER)(IN WCHAR Character);
@@ -95,4 +103,13 @@ typedef struct _RTL_PRINT_FORMAT_PROPERTIES
     LONG Flags;
 } RTL_PRINT_FORMAT_PROPERTIES, *PRTL_PRINT_FORMAT_PROPERTIES;
 
+/* Runtime Library SHA-1 context structure definition */
+typedef struct _RTL_SHA1_CONTEXT
+{
+    ULONG   State[5];
+    ULONG   Count[2];
+    UCHAR   Buffer[SHA1_BLOCK_SIZE];
+} RTL_SHA1_CONTEXT, *PRTL_SHA1_CONTEXT;
+
+#endif /* __XTOS_ASSEMBLER__ */
 #endif /* __XTDK_RTLTYPES_H */

sdk/xtdk/xtbase.h

@@ -14,6 +14,9 @@
 #include <xttypes.h>
 
 
+/* C/C++ specific code */
+#ifndef __XTOS_ASSEMBLER__
+
 /* Kernel affinity */
 typedef ULONG_PTR KAFFINITY, *PKAFFINITY;
 
@@ -29,6 +32,9 @@ typedef UCHAR KRUNLEVEL, *PKRUNLEVEL;
 /* Spin locks synchronization mechanism */
 typedef ULONG_PTR KSPIN_LOCK, *PKSPIN_LOCK;
 
+/* Page Frame Number count */
+typedef ULONG PFN_COUNT;
+
 /* Page Frame Number */
 typedef ULONG_PTR PFN_NUMBER, *PPFN_NUMBER;
 
@@ -105,4 +111,5 @@ typedef struct _DISPATCHER_HEADER
     LIST_ENTRY WaitListHead;
 } DISPATCHER_HEADER, *PDISPATCHER_HEADER;
 
+#endif /* __XTOS_ASSEMBLER_ */
 #endif /* __XTDK_XTBASE_H */

sdk/xtdk/xtcompat.h

@@ -10,10 +10,15 @@
 #define __XTDK_XTCOMPAT_H
 
 
+/* C/C++ specific code */
+#ifndef __XTOS_ASSEMBLER__
+
 #ifdef __cplusplus
     /* C++ definitions */
-    #define XTCLINK         extern "C"
     #define NULLPTR         nullptr
+    #define VIRTUAL         virtual
+    #define XTCLINK         extern "C"
+    #define XTSYMBOL(Name)  __asm__(Name)
 
     /* C++ boolean type */
     typedef bool BOOLEAN, *PBOOLEAN;
@@ -24,8 +29,10 @@
     typedef wchar_t wchar;
 #else
     /* C definitions */
-    #define XTCLINK
     #define NULLPTR         ((void *)0)
+    #define VIRTUAL
+    #define XTCLINK
+    #define XTSYMBOL(Name)
 
     /* C boolean type */
     typedef enum _BOOLEAN
@@ -38,4 +45,5 @@
     typedef unsigned short wchar;
 #endif
 
+#endif /* __XTOS_ASSEMBLER__ */
 #endif /* __XTDK_XTCOMPAT_H */

sdk/xtdk/xtdebug.h

@@ -23,7 +23,7 @@
     #define DebugPrint(Format, ...)     DbgPrint(Format, __VA_ARGS__);
 #else
     #define DEBUG                       0
-    #define DebugPrint(Format, ...)     ((VOID)NULL)
+    #define DebugPrint(Format, ...)     ((VOID)NULLPTR)
 #endif
 
 #endif /* __XTDK_XTDEBUG_H */

sdk/xtdk/xtdefs.h

@@ -74,12 +74,20 @@
 /* Macro for calculating size of a field in the structure */
 #define FIELD_SIZE(Structure, Field)           (sizeof(((Structure *)0)->Field))
 
+/* Macros for calculating minimum and maximum of two values */
+#define MIN(A, B)                              (((A) < (B)) ? (A) : (B))
+#define MAX(A, B)                              (((A) > (B)) ? (A) : (B))
+
 /* Macro that page-aligns a virtual address */
 #define PAGE_ALIGN(VirtualAddress)             ((PVOID)((ULONG_PTR)VirtualAddress & ~MM_PAGE_MASK))
 
 /* Macro that returns offset of the virtual address */
 #define PAGE_OFFSET(VirtualAddress)            ((ULONG)((ULONG_PTR)VirtualAddress & MM_PAGE_MASK))
 
+/* Macros for bitwise rotating */
+#define ROTATE_LEFT(Value, Count)              ((Value << Count) | (Value >> (32 - Count)))
+#define ROTATE_RIGHT(Value, Count)             ((Value >> Count) | (Value << (32 - Count)))
+
 /* Macro for rounding down */
 #define ROUND_DOWN(Value, Alignment)           ((Value) & ~((Alignment) - 1))
 
@@ -103,8 +111,7 @@
 #define UNIQUE(Prefix)                         CONCATENATE(CONCATENATE(__UNIQUE_ID_, Prefix), __COUNTER__)
 
 /* Variadic ABI functions */
-typedef __builtin_va_list VA_LIST, *PVA_LIST;
-#define VA_ARG(Marker, Type)                   ((sizeof (Type) < sizeof(UINT_PTR)) ? \
+#define VA_ARG(Marker, Type)                   ((sizeof(Type) < sizeof(UINT_PTR)) ? \
                                                (Type)(__builtin_va_arg(Marker, UINT_PTR)) : \
                                                (Type)(__builtin_va_arg(Marker, Type)))
 #define VA_COPY(Dest, Start)                   __builtin_va_copy(Dest, Start)

sdk/xtdk/xtfont.h

@@ -13,6 +13,9 @@
 #include <xtdefs.h>
 
 
+/* C/C++ specific code */
+#ifndef D__XTOS_ASSEMBLER__
+
 /* SSF2 font header */
 typedef struct _SSFN_FONT_HEADER
 {
@@ -3980,4 +3983,5 @@ UCHAR XtFbDefaultFont[] = {0x78, 0x74, 0x66, 0x6E, 0x3B, 0xE7, 0x00, 0x00, 0x03,
                            0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
                            0x82, 0x32, 0x4E, 0x46, 0x53};
 
+#endif /* __XTOS_ASSEMBLER__ */
 #endif /* __XTDK_XTFONT_H */

sdk/xtdk/xtfw.h

@@ -19,6 +19,10 @@
 /* Version number of the current XTOS loader protocol */
 #define BOOT_PROTOCOL_VERSION                                   1
 
+
+/* C/C++ specific code */
+#ifndef __XTOS_ASSEMBLER__
+
 /* Memory allocation structures */
 typedef enum _LOADER_MEMORY_TYPE
 {
@@ -107,6 +111,7 @@ typedef struct _KERNEL_INITIALIZATION_BLOCK
     ULONG BlockVersion;
     ULONG ProtocolVersion;
     PWCHAR KernelParameters;
+    PFN_NUMBER BootImageSize;
     LIST_ENTRY LoadOrderListHead;
     LIST_ENTRY MemoryDescriptorListHead;
     LIST_ENTRY BootDriverListHead;
@@ -115,4 +120,5 @@ typedef struct _KERNEL_INITIALIZATION_BLOCK
     FIRMWARE_INFORMATION_BLOCK FirmwareInformation;
 } KERNEL_INITIALIZATION_BLOCK, *PKERNEL_INITIALIZATION_BLOCK;
 
+#endif /* __XTOS_ASSEMBLER_ */
 #endif /* __XTDK_XTFW_H */

sdk/xtdk/xtglyph.h

@@ -12,6 +12,9 @@
 #include <xttypes.h>
 
 
+/* C/C++ specific code */
+#ifndef D__XTOS_ASSEMBLER__
+
 CHAR XTGLYPH_EXECTOS_LOGO[] =
 {
   0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x25, 0x23,
@@ -61,4 +64,5 @@ CHAR XTGLYPH_EXECTOS_LOGO[] =
   0x28, 0x0d, 0x0a
 };
 
+#endif /* __XTOS_ASSEMBLER__ */
 #endif /* __XTDK_XTGLYPH_H */

sdk/xtdk/xtimage.h

@@ -202,6 +202,10 @@
 #define PECOFF_IMAGE_SCN_MEM_READ                          0x40000000
 #define PECOFF_IMAGE_SCN_MEM_WRITE                         0x80000000
 
+
+/* C/C++ specific code */
+#ifndef __XTOS_ASSEMBLER__
+
 /* PE/COFF image representation structure */
 typedef struct _PECOFF_IMAGE_CONTEXT
 {
@@ -638,4 +642,5 @@ typedef struct _PECOFF_IMAGE_RESOURCE_DATA_ENTRY
     ULONG Reserved;
 } PECOFF_IMAGE_RESOURCE_DATA_ENTRY, *PPECOFF_IMAGE_RESOURCE_DATA_ENTRY;
 
+#endif /* __XTOS_ASSEMBLER__ */
 #endif /* __XTDK_XTIMAGE_H */

sdk/xtdk/xtkmapi.h

@@ -50,6 +50,7 @@
 #include <hlfuncs.h>
 #include <kdfuncs.h>
 #include <kefuncs.h>
+#include <mmfuncs.h>
 #include <rtlfuncs.h>
 
 /* Architecture specific XT routines */

sdk/xtdk/xtstruct.h

@@ -12,6 +12,9 @@
 #include <xtdefs.h>
 
 
+/* C/C++ specific code */
+#ifndef __XTOS_ASSEMBLER__
+
 /* Enumeration lists forward references */
 typedef enum _ADJUST_REASON ADJUST_REASON, *PADJUST_REASON;
 typedef enum _EXCEPTION_DISPOSITION EXCEPTION_DISPOSITION, *PEXCEPTION_DISPOSITION;
@@ -44,10 +47,15 @@ typedef enum _KDPC_IMPORTANCE KDPC_IMPORTANCE, *PKDPC_IMPORTANCE;
 typedef enum _KEVENT_TYPE KEVENT_TYPE, *PKEVENT_TYPE;
 typedef enum _KOBJECTS KOBJECTS, *PKOBJECTS;
 typedef enum _KPROCESS_STATE KPROCESS_STATE, *PKPROCESS_STATE;
+typedef enum _KPROFILE_SOURCE KPROFILE_SOURCE, *PKPROFILE_SOURCE;
 typedef enum _KTHREAD_STATE KTHREAD_STATE, *PKTHREAD_STATE;
 typedef enum _KTIMER_TYPE KTIMER_TYPE, *PKTIMER_TYPE;
 typedef enum _KUBSAN_DATA_TYPE KUBSAN_DATA_TYPE, *PKUBSAN_DATA_TYPE;
 typedef enum _LOADER_MEMORY_TYPE LOADER_MEMORY_TYPE, *PLOADER_MEMORY_TYPE;
+typedef enum _MMPAGELISTS MMPAGELISTS, *PMMPAGELISTS;
+typedef enum _MMPFN_CACHE_ATTRIBUTE MMPFN_CACHE_ATTRIBUTE, *PMMPFN_CACHE_ATTRIBUTE;
+typedef enum _MMPOOL_TYPE MMPOOL_TYPE, *PMMPOOL_TYPE;
+typedef enum _MMSYSTEM_PTE_POOL_TYPE MMSYSTEM_PTE_POOL_TYPE, *PMMSYSTEM_PTE_POOL_TYPE;
 typedef enum _MODE MODE, *PMODE;
 typedef enum _RTL_VARIABLE_TYPE RTL_VARIABLE_TYPE, *PRTL_VARIABLE_TYPE;
 typedef enum _SYSTEM_FIRMWARE_TYPE SYSTEM_FIRMWARE_TYPE, *PSYSTEM_FIRMWARE_TYPE;
@@ -58,8 +66,12 @@ typedef enum _WAIT_TYPE WAIT_TYPE, *PWAIT_TYPE;
 typedef struct _ACPI_CACHE_LIST ACPI_CACHE_LIST, *PACPI_CACHE_LIST;
 typedef struct _ACPI_DESCRIPTION_HEADER ACPI_DESCRIPTION_HEADER, *PACPI_DESCRIPTION_HEADER;
 typedef struct _ACPI_FADT ACPI_FADT, *PACPI_FADT;
+typedef struct _ACPI_HPET ACPI_HPET, *PACPI_HPET;
 typedef struct _ACPI_MADT ACPI_MADT, *PACPI_MADT;
-typedef struct _ACPI_MADT_TABLE_LOCAL_APIC ACPI_MADT_TABLE_LOCAL_APIC, *PACPI_MADT_TABLE_LOCAL_APIC;
+typedef struct _ACPI_MADT_INTERRUPT_OVERRIDE ACPI_MADT_INTERRUPT_OVERRIDE, *PACPI_MADT_INTERRUPT_OVERRIDE;
+typedef struct _ACPI_MADT_IOAPIC ACPI_MADT_IOAPIC, *PACPI_MADT_IOAPIC;
+typedef struct _ACPI_MADT_LOCAL_APIC ACPI_MADT_LOCAL_APIC, *PACPI_MADT_LOCAL_APIC;
+typedef struct _ACPI_MADT_LOCAL_X2APIC ACPI_MADT_LOCAL_X2APIC, *PACPI_MADT_LOCAL_X2APIC;
 typedef struct _ACPI_RSDP ACPI_RSDP, *PACPI_RSDP;
 typedef struct _ACPI_RSDT ACPI_RSDT, *PACPI_RSDT;
 typedef struct _ACPI_SUBTABLE_HEADER ACPI_SUBTABLE_HEADER, *PACPI_SUBTABLE_HEADER;
@@ -274,7 +286,10 @@ typedef struct _LOADER_INFORMATION_BLOCK LOADER_INFORMATION_BLOCK, *PLOADER_INFO
 typedef struct _LOADER_MEMORY_DESCRIPTOR LOADER_MEMORY_DESCRIPTOR, *PLOADER_MEMORY_DESCRIPTOR;
 typedef struct _M128 M128, *PM128;
 typedef struct _MMCOLOR_TABLES MMCOLOR_TABLES, *PMMCOLOR_TABLES;
+typedef struct _MMFREE_POOL_ENTRY MMFREE_POOL_ENTRY, *PMMFREE_POOL_ENTRY;
+typedef struct _MMMEMORY_LAYOUT MMMEMORY_LAYOUT, *PMMMEMORY_LAYOUT;
 typedef struct _MMPFNENTRY MMPFNENTRY, *PMMPFNENTRY;
+typedef struct _MMPFNLIST MMPFNLIST, *PMMPFNLIST;
 typedef struct _PCAT_FIRMWARE_INFORMATION PCAT_FIRMWARE_INFORMATION, *PPCAT_FIRMWARE_INFORMATION;
 typedef struct _PCI_BRIDGE_CONTROL_REGISTER PCI_BRIDGE_CONTROL_REGISTER, *PPCI_BRIDGE_CONTROL_REGISTER;
 typedef struct _PCI_COMMON_CONFIG PCI_COMMON_CONFIG, *PPCI_COMMON_CONFIG;
@@ -303,6 +318,11 @@ typedef struct _PECOFF_IMAGE_ROM_HEADER PECOFF_IMAGE_ROM_HEADER, *PPECOFF_IMAGE_
 typedef struct _PECOFF_IMAGE_ROM_OPTIONAL_HEADER PECOFF_IMAGE_ROM_OPTIONAL_HEADER, *PPECOFF_IMAGE_ROM_OPTIONAL_HEADER;
 typedef struct _PECOFF_IMAGE_SECTION_HEADER PECOFF_IMAGE_SECTION_HEADER, *PPECOFF_IMAGE_SECTION_HEADER;
 typedef struct _PECOFF_IMAGE_VXD_HEADER PECOFF_IMAGE_VXD_HEADER, *PPECOFF_IMAGE_VXD_HEADER;
+typedef struct _PHYSICAL_MEMORY_DESCRIPTOR PHYSICAL_MEMORY_DESCRIPTOR, *PPHYSICAL_MEMORY_DESCRIPTOR;
+typedef struct _PHYSICAL_MEMORY_RUN PHYSICAL_MEMORY_RUN, *PPHYSICAL_MEMORY_RUN;
+typedef struct _POOL_HEADER POOL_HEADER, *PPOOL_HEADER;
+typedef struct _POOL_TRACKING_BIG_ALLOCATIONS POOL_TRACKING_BIG_ALLOCATIONS, *PPOOL_TRACKING_BIG_ALLOCATIONS;
+typedef struct _POOL_TRACKING_TABLE POOL_TRACKING_TABLE, *PPOOL_TRACKING_TABLE;
 typedef struct _PROCESSOR_IDENTITY PROCESSOR_IDENTITY, *PPROCESSOR_IDENTITY;
 typedef struct _PROCESSOR_POWER_STATE PROCESSOR_POWER_STATE, *PPROCESSOR_POWER_STATE;
 typedef struct _RTL_BITMAP RTL_BITMAP, *PRTL_BITMAP;
@@ -351,4 +371,5 @@ typedef union _LARGE_INTEGER LARGE_INTEGER, *PLARGE_INTEGER;
 typedef union _SINGLE_LIST_HEADER SINGLE_LIST_HEADER, *PSINGLE_LIST_HEADER;
 typedef union _ULARGE_INTEGER ULARGE_INTEGER, *PULARGE_INTEGER;
 
+#endif /* __XTOS_ASSEMBLER__ */
 #endif /* __XTDK_XTSTRUCT_H */

sdk/xtdk/xttypes.h

@@ -13,6 +13,9 @@
 #include <xtcompat.h>
 
 
+/* C/C++ specific code */
+#ifndef __XTOS_ASSEMBLER__
+
 /* Standard C types */
 typedef unsigned char BYTE, *PBYTE, *LPBYTE;
 typedef char CHAR, *PCHAR, *LPCHAR;
@@ -150,6 +153,9 @@ typedef LPCWSTR PCTSTR, LPCTSTR;
 typedef LPUWSTR PUTSTR, LPUTSTR;
 typedef LPCUWSTR PCUTSTR, LPCUTSTR;
 
+/* Variadic ABI types */
+typedef __builtin_va_list VA_LIST, *PVA_LIST;
+
 /* 128-bit floats structure */
 typedef struct _FLOAT128
 {
@@ -287,4 +293,5 @@ typedef struct _UNICODE_STRING64
 } UNICODE_STRING64, *PUNICODE_STRING64;
 typedef const UNICODE_STRING64 *PCUNICODE_STRING64;
 
+#endif /* __XTOS_ASSEMBLER__ */
 #endif /* __XTDK_XTTYPES_H */

sdk/xtdk/xtuefi.h

@@ -373,6 +373,10 @@
 #define EFI_CONFIG_TABLE_SMBIOS_TABLE_GUID                 {0xEB9D2D31, 0x2D88, 0x11D3, {0x9A, 0x16, 0x00, 0x90, 0x27, 0x3F, 0xC1, 0x4D}}
 #define EFI_CONFIG_TABLE_SMBIOS3_TABLE_GUID                {0xF2FD1544, 0x9794, 0x4A2C, {0x99, 0x2E, 0xE5, 0xBB, 0xCf, 0x20, 0xE3, 0x94}}
 
+
+/* C/C++ specific code */
+#ifndef __XTOS_ASSEMBLER__
+
 /* Basic UEFI types */
 typedef PVOID EFI_EVENT, *PEFI_EVENT;
 typedef PVOID EFI_HANDLE, *PEFI_HANDLE;
@@ -2723,4 +2727,5 @@ typedef struct _EFI_PROCESSOR_INFORMATION
     EFI_PROCESSOR_PHYSICAL_LOCATION Location;
 } EFI_PROCESSOR_INFORMATION, *PEFI_PROCESSOR_INFORMATION;
 
+#endif /* __XTOS_ASSEMBLER__ */
 #endif /* __XTDK_XTUEFI_H */

xtoskrnl/CMakeLists.txt

@@ -10,7 +10,6 @@ include_directories(
 # Specify list of kernel source code files
 list(APPEND XTOSKRNL_SOURCE
     ${XTOSKRNL_SOURCE_DIR}/ar/${ARCH}/archsup.S
-    ${XTOSKRNL_SOURCE_DIR}/ar/${ARCH}/boot.S
     ${XTOSKRNL_SOURCE_DIR}/ar/${ARCH}/cpufunc.cc
     ${XTOSKRNL_SOURCE_DIR}/ar/${ARCH}/data.cc
     ${XTOSKRNL_SOURCE_DIR}/ar/${ARCH}/procsup.cc
@@ -20,7 +19,9 @@ list(APPEND XTOSKRNL_SOURCE
     ${XTOSKRNL_SOURCE_DIR}/hl/${ARCH}/cpu.cc
     ${XTOSKRNL_SOURCE_DIR}/hl/${ARCH}/pic.cc
     ${XTOSKRNL_SOURCE_DIR}/hl/${ARCH}/ioport.cc
+    ${XTOSKRNL_SOURCE_DIR}/hl/${ARCH}/irq.cc
     ${XTOSKRNL_SOURCE_DIR}/hl/${ARCH}/runlevel.cc
+    ${XTOSKRNL_SOURCE_DIR}/hl/${ARCH}/timer.cc
     ${XTOSKRNL_SOURCE_DIR}/hl/acpi.cc
     ${XTOSKRNL_SOURCE_DIR}/hl/cport.cc
     ${XTOSKRNL_SOURCE_DIR}/hl/data.cc
@@ -31,7 +32,6 @@ list(APPEND XTOSKRNL_SOURCE
     ${XTOSKRNL_SOURCE_DIR}/kd/data.cc
     ${XTOSKRNL_SOURCE_DIR}/kd/dbgio.cc
     ${XTOSKRNL_SOURCE_DIR}/kd/exports.cc
-    ${XTOSKRNL_SOURCE_DIR}/ke/${ARCH}/irq.cc
     ${XTOSKRNL_SOURCE_DIR}/ke/${ARCH}/krnlinit.cc
     ${XTOSKRNL_SOURCE_DIR}/ke/${ARCH}/kthread.cc
     ${XTOSKRNL_SOURCE_DIR}/ke/${ARCH}/proc.cc
@@ -51,14 +51,24 @@ list(APPEND XTOSKRNL_SOURCE
     ${XTOSKRNL_SOURCE_DIR}/ke/spinlock.cc
     ${XTOSKRNL_SOURCE_DIR}/ke/sysres.cc
     ${XTOSKRNL_SOURCE_DIR}/ke/timer.cc
-    ${XTOSKRNL_SOURCE_DIR}/mm/${ARCH}/init.cc
+    ${XTOSKRNL_SOURCE_DIR}/mm/${ARCH}/mmgr.cc
     ${XTOSKRNL_SOURCE_DIR}/mm/${ARCH}/pagemap.cc
     ${XTOSKRNL_SOURCE_DIR}/mm/${ARCH}/paging.cc
+    ${XTOSKRNL_SOURCE_DIR}/mm/${ARCH}/pfault.cc
+    ${XTOSKRNL_SOURCE_DIR}/mm/${ARCH}/pfn.cc
+    ${XTOSKRNL_SOURCE_DIR}/mm/${ARCH}/pool.cc
+    ${XTOSKRNL_SOURCE_DIR}/mm/${ARCH}/pte.cc
+    ${XTOSKRNL_SOURCE_DIR}/mm/alloc.cc
+    ${XTOSKRNL_SOURCE_DIR}/mm/colors.cc
     ${XTOSKRNL_SOURCE_DIR}/mm/data.cc
+    ${XTOSKRNL_SOURCE_DIR}/mm/exports.cc
     ${XTOSKRNL_SOURCE_DIR}/mm/hlpool.cc
-    ${XTOSKRNL_SOURCE_DIR}/mm/init.cc
     ${XTOSKRNL_SOURCE_DIR}/mm/kpool.cc
+    ${XTOSKRNL_SOURCE_DIR}/mm/mmgr.cc
     ${XTOSKRNL_SOURCE_DIR}/mm/paging.cc
+    ${XTOSKRNL_SOURCE_DIR}/mm/pfn.cc
+    ${XTOSKRNL_SOURCE_DIR}/mm/pool.cc
+    ${XTOSKRNL_SOURCE_DIR}/mm/pte.cc
     ${XTOSKRNL_SOURCE_DIR}/po/idle.cc
     ${XTOSKRNL_SOURCE_DIR}/rtl/${ARCH}/dispatch.cc
     ${XTOSKRNL_SOURCE_DIR}/rtl/${ARCH}/exsup.cc
@@ -71,6 +81,8 @@ list(APPEND XTOSKRNL_SOURCE
     ${XTOSKRNL_SOURCE_DIR}/rtl/llist.cc
     ${XTOSKRNL_SOURCE_DIR}/rtl/math.cc
     ${XTOSKRNL_SOURCE_DIR}/rtl/memory.cc
+    ${XTOSKRNL_SOURCE_DIR}/rtl/sha1.cc
+    ${XTOSKRNL_SOURCE_DIR}/rtl/slist.cc
     ${XTOSKRNL_SOURCE_DIR}/rtl/string.cc
     ${XTOSKRNL_SOURCE_DIR}/rtl/widestr.cc)
 
@@ -79,14 +91,13 @@ set_specfile(xtoskrnl.spec xtoskrnl.exe)
 
 # Link static XTOS library
 add_library(libxtos ${XTOSKRNL_SOURCE})
+target_link_libraries(libxtos PRIVATE xtadk)
 
 # Link kernel executable
-add_executable(xtoskrnl
-               ${XTOSKRNL_SOURCE}
-               ${CMAKE_CURRENT_BINARY_DIR}/xtoskrnl.def)
+add_executable(xtoskrnl ${CMAKE_CURRENT_BINARY_DIR}/xtoskrnl.def)
 
 # Add linker libraries
-target_link_libraries(xtoskrnl)
+target_link_libraries(xtoskrnl PRIVATE libxtos)
 
 # Set proper binary name and install target
 set_target_properties(xtoskrnl PROPERTIES SUFFIX .exe)

xtoskrnl/README.md

@@ -4,6 +4,18 @@ within the XTOS kernel space. It is responsible for various core services, such
 management, and process scheduling. The kernel contains the scheduler (sometimes referred to as the Dispatcher), the
 cache, object, and memory managers, the security manager, and other executive components described below.
 
+
+## Kernel Parameters
+Kernel parameters are XTOS boot-time options used to ensure proper initialization and handling of hardware peripherals.
+These parameters can be configured either temporarily by editing the boot entry in the bootloader’s selection menu, or
+permanently by modifying the XTLDR configuration file.
+
+The following is a consolidated list of available kernel parameters:
+ * **NOXPA**: Disables PAE or LA57 support, depending on the CPU architecture. This parameter is handled by the
+   bootloader, which configures paging and selects the appropriate Page Map Level (PML) before transferring control to
+   the kernel.
+
+## Source Code
 The source code of the kernel is organized into subsystem-specific directories. Each directory name also defines the
 corresponding C++ namespace in which the subsystem's classes and routines reside. These subsystems include:
 
@@ -68,8 +80,8 @@ routine:
 For all C++ code inside the kernel the naming model has evolved. Consider the **KE::KThread::InitializeThread()**
 routine:
  * **KE** - The namespace replaces the prefix and indicates the subsystem. Namespaces are written in uppercase and no
-            longer use the trailing p for private routines, because classes use C++ visibility to control access.
+   longer use the trailing p for private routines, because classes use C++ visibility to control access.
  * **KThread** - Within each namespace, related functionality is grouped into classes, which encapsulate variables and
-                 methods.
+   methods.
  * **InitializeThread** - Method names follow the `<Operation><Object>` pattern.
  

xtoskrnl/ar/amd64/archsup.S

@@ -4,29 +4,40 @@
  * FILE:            xtoskrnl/ar/amd64/archsup.S
  * DESCRIPTION:     Provides AMD64 architecture features not implementable in C
  * DEVELOPERS:      Rafal Kupiec <belliash@codingworkshop.eu.org>
+ *                  Aiken Harris <harraiken91@gmail.com>
  */
 
-#include <ar/amd64/asmsup.h>
+#include <xtkmapi.h>
+#include <xtadk.h>
 
 .altmacro
 .text
 
 
 /**
- * Creates a trap handler for the specified vector.
+ * Creates a trap or interrupt handler for the specified vector.
  *
  * @param Vector
- *        Supplies a trap vector number.
+ *        Supplies a trap/interrupt vector number.
+ *
+ * @param Type
+ *        Specifies whether the handler is designed to handle an interrupt or a trap.
  *
  * @return This macro does not return any value.
  *
  * @since XT 1.0
  */
-.macro ArCreateTrapHandler Vector
-.global ArTrap\Vector
-ArTrap\Vector:
-    /* Push fake error code for non-error vectors */
-    .if \Vector != 8 && \Vector != 10 && \Vector != 11 && \Vector != 12 && \Vector != 13 && \Vector != 14 && \Vector != 17 && \Vector != 30
+.macro ArCreateHandler Vector Type
+.global Ar\Type\Vector
+Ar\Type\Vector:
+    /* Check handler type */
+    .ifc \Type,Trap
+        /* Push fake error code for non-error vector traps */
+        .if \Vector != 8 && \Vector != 10 && \Vector != 11 && \Vector != 12 && \Vector != 13 && \Vector != 14 && \Vector != 17 && \Vector != 30
+            push $0
+        .endif
+    .else
+        /* Push fake error code for interrupts */
         push $0
     .endif
 
@@ -51,105 +62,122 @@ ArTrap\Vector:
     push %rax
 
     /* Reserve space for other registers and point RBP to the trap frame */
-    sub $(TRAP_FRAME_SIZE - TRAP_REGISTERS_SIZE), %rsp
+    sub $(KTRAP_FRAME_SIZE - KTRAP_FRAME_REGISTERS_SIZE), %rsp
     lea (%rsp), %rbp
 
     /* Store segment selectors */
-    mov %gs, TrapSegGs(%rbp)
-    mov %fs, TrapSegFs(%rbp)
-    mov %es, TrapSegEs(%rbp)
-    mov %ds, TrapSegDs(%rbp)
+    mov %gs, KTRAP_FRAME_SegGs(%rbp)
+    mov %fs, KTRAP_FRAME_SegFs(%rbp)
+    mov %es, KTRAP_FRAME_SegEs(%rbp)
+    mov %ds, KTRAP_FRAME_SegDs(%rbp)
 
     /* Store debug registers */
     mov %dr7, %rax
-    mov %rax, TrapDr7(%rbp)
+    mov %rax, KTRAP_FRAME_Dr7(%rbp)
     mov %dr6, %rax
-    mov %rax, TrapDr6(%rbp)
+    mov %rax, KTRAP_FRAME_Dr6(%rbp)
     mov %dr3, %rax
-    mov %rax, TrapDr3(%rbp)
+    mov %rax, KTRAP_FRAME_Dr3(%rbp)
     mov %dr2, %rax
-    mov %rax, TrapDr2(%rbp)
+    mov %rax, KTRAP_FRAME_Dr2(%rbp)
     mov %dr1, %rax
-    mov %rax, TrapDr1(%rbp)
+    mov %rax, KTRAP_FRAME_Dr1(%rbp)
     mov %dr0, %rax
-    mov %rax, TrapDr0(%rbp)
+    mov %rax, KTRAP_FRAME_Dr0(%rbp)
 
     /* Store CR2 and CR3 */
     mov %cr3, %rax
-    mov %rax, TrapCr3(%rbp)
+    mov %rax, KTRAP_FRAME_Cr3(%rbp)
     mov %cr2, %rax
-    mov %rax, TrapCr2(%rbp)
+    mov %rax, KTRAP_FRAME_Cr2(%rbp)
 
     /* Store MxCsr register */
-    stmxcsr TrapMxCsr(%rbp)
+    stmxcsr KTRAP_FRAME_MxCsr(%rbp)
 
     /* Store XMM registers */
-    movdqa %xmm15, TrapXmm15(%rbp)
-    movdqa %xmm14, TrapXmm14(%rbp)
-    movdqa %xmm13, TrapXmm13(%rbp)
-    movdqa %xmm12, TrapXmm12(%rbp)
-    movdqa %xmm11, TrapXmm11(%rbp)
-    movdqa %xmm10, TrapXmm10(%rbp)
-    movdqa %xmm9, TrapXmm9(%rbp)
-    movdqa %xmm8, TrapXmm8(%rbp)
-    movdqa %xmm7, TrapXmm7(%rbp)
-    movdqa %xmm6, TrapXmm6(%rbp)
-    movdqa %xmm5, TrapXmm5(%rbp)
-    movdqa %xmm4, TrapXmm4(%rbp)
-    movdqa %xmm3, TrapXmm3(%rbp)
-    movdqa %xmm2, TrapXmm2(%rbp)
-    movdqa %xmm1, TrapXmm1(%rbp)
-    movdqa %xmm0, TrapXmm0(%rbp)
+    movdqa %xmm15, KTRAP_FRAME_Xmm15(%rbp)
+    movdqa %xmm14, KTRAP_FRAME_Xmm14(%rbp)
+    movdqa %xmm13, KTRAP_FRAME_Xmm13(%rbp)
+    movdqa %xmm12, KTRAP_FRAME_Xmm12(%rbp)
+    movdqa %xmm11, KTRAP_FRAME_Xmm11(%rbp)
+    movdqa %xmm10, KTRAP_FRAME_Xmm10(%rbp)
+    movdqa %xmm9, KTRAP_FRAME_Xmm9(%rbp)
+    movdqa %xmm8, KTRAP_FRAME_Xmm8(%rbp)
+    movdqa %xmm7, KTRAP_FRAME_Xmm7(%rbp)
+    movdqa %xmm6, KTRAP_FRAME_Xmm6(%rbp)
+    movdqa %xmm5, KTRAP_FRAME_Xmm5(%rbp)
+    movdqa %xmm4, KTRAP_FRAME_Xmm4(%rbp)
+    movdqa %xmm3, KTRAP_FRAME_Xmm3(%rbp)
+    movdqa %xmm2, KTRAP_FRAME_Xmm2(%rbp)
+    movdqa %xmm1, KTRAP_FRAME_Xmm1(%rbp)
+    movdqa %xmm0, KTRAP_FRAME_Xmm0(%rbp)
 
     /* Test previous mode and swap GS if needed */
-    movl $0, TrapPreviousMode(%rbp)
-    mov %cs, %ax
-    and $1, %al
-    mov %al, TrapPreviousMode(%rbp)
-    jz KernelMode$\Vector
+    movl $0, KTRAP_FRAME_PreviousMode(%rbp)
+    mov KTRAP_FRAME_SegCs(%rbp), %ax
+    and $3, %al
+    mov %al, KTRAP_FRAME_PreviousMode(%rbp)
+
+    /* Skip swapgs as the interrupt originated from kernel mode */
+    jz Dispatch\Type\Vector
+
     swapgs
 
-KernelMode$\Vector:
-    /* Push Frame Pointer, clear direction flag and pass to trap dispatcher */
+Dispatch\Type\Vector:
+    /* Set up trap frame pointer for the dispatcher and clear the direction flag */
     mov %rsp, %rcx
     cld
-    call ArDispatchTrap
+
+    /* Preserve the original stack pointer */
+    mov %rsp, %rbx
+
+    /* Force stack alignment */
+    and $-16, %rsp
+
+    /* Allocate 32 bytes of shadow space */
+    sub $32, %rsp
+
+    .ifc \Type,Trap
+        /* Pass to the trap dispatcher */
+        call ArDispatchTrap
+    .else
+        /* Pass to the interrupt dispatcher */
+        call ArDispatchInterrupt
+    .endif
+
+    /* Restore the original trap frame stack pointer */
+    mov %rbx, %rsp
 
     /* Test previous mode and swapgs if needed */
-    testb $1, TrapPreviousMode(%rbp)
-    jz KernelModeReturn$\Vector
+    testb $1, KTRAP_FRAME_PreviousMode(%rbp)
+    jz RestoreState\Type\Vector
     cli
     swapgs
 
-KernelModeReturn$\Vector:
+RestoreState\Type\Vector:
     /* Restore XMM registers */
-    movdqa TrapXmm0(%rbp), %xmm0
-    movdqa TrapXmm1(%rbp), %xmm1
-    movdqa TrapXmm2(%rbp), %xmm2
-    movdqa TrapXmm3(%rbp), %xmm3
-    movdqa TrapXmm4(%rbp), %xmm4
-    movdqa TrapXmm5(%rbp), %xmm5
-    movdqa TrapXmm6(%rbp), %xmm6
-    movdqa TrapXmm7(%rbp), %xmm7
-    movdqa TrapXmm8(%rbp), %xmm8
-    movdqa TrapXmm9(%rbp), %xmm9
-    movdqa TrapXmm10(%rbp), %xmm10
-    movdqa TrapXmm11(%rbp), %xmm11
-    movdqa TrapXmm12(%rbp), %xmm12
-    movdqa TrapXmm13(%rbp), %xmm13
-    movdqa TrapXmm14(%rbp), %xmm14
-    movdqa TrapXmm15(%rbp), %xmm15
+    movdqa KTRAP_FRAME_Xmm0(%rbp), %xmm0
+    movdqa KTRAP_FRAME_Xmm1(%rbp), %xmm1
+    movdqa KTRAP_FRAME_Xmm2(%rbp), %xmm2
+    movdqa KTRAP_FRAME_Xmm3(%rbp), %xmm3
+    movdqa KTRAP_FRAME_Xmm4(%rbp), %xmm4
+    movdqa KTRAP_FRAME_Xmm5(%rbp), %xmm5
+    movdqa KTRAP_FRAME_Xmm6(%rbp), %xmm6
+    movdqa KTRAP_FRAME_Xmm7(%rbp), %xmm7
+    movdqa KTRAP_FRAME_Xmm8(%rbp), %xmm8
+    movdqa KTRAP_FRAME_Xmm9(%rbp), %xmm9
+    movdqa KTRAP_FRAME_Xmm10(%rbp), %xmm10
+    movdqa KTRAP_FRAME_Xmm11(%rbp), %xmm11
+    movdqa KTRAP_FRAME_Xmm12(%rbp), %xmm12
+    movdqa KTRAP_FRAME_Xmm13(%rbp), %xmm13
+    movdqa KTRAP_FRAME_Xmm14(%rbp), %xmm14
+    movdqa KTRAP_FRAME_Xmm15(%rbp), %xmm15
 
     /* Load MxCsr register */
-    ldmxcsr TrapMxCsr(%rbp)
-
-    /* Restore segment selectors */
-    mov TrapSegDs(%rbp), %ds
-    mov TrapSegEs(%rbp), %es
-    mov TrapSegFs(%rbp), %fs
+    ldmxcsr KTRAP_FRAME_MxCsr(%rbp)
 
     /* Free stack space */
-    add $(TRAP_FRAME_SIZE - TRAP_REGISTERS_SIZE), %rsp
+    add $(KTRAP_FRAME_SIZE - KTRAP_FRAME_REGISTERS_SIZE), %rsp
 
     /* Pop General Purpose Registers */
     pop %rax
@@ -173,9 +201,172 @@ KernelModeReturn$\Vector:
     iretq
 .endm
 
-/* Populate common trap handlers */
+/* Populate common interrupt and trap handlers */
 .irp i,0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F
     .irp j,0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F
-        ArCreateTrapHandler 0x\i\j
+        ArCreateHandler 0x\i\j Interrupt
+        ArCreateHandler 0x\i\j Trap
     .endr
 .endr
+
+/* Define array of pointers to the interrupt handlers */
+.global ArInterruptEntry
+ArInterruptEntry:
+.irp i,0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F
+    .irp j,0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F
+        .quad ArInterrupt0x\i\j
+    .endr
+.endr
+
+/* Define array of pointers to the trap handlers */
+.global ArTrapEntry
+ArTrapEntry:
+.irp i,0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F
+    .irp j,0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F
+        .quad ArTrap0x\i\j
+    .endr
+.endr
+
+/**
+ * Enables eXtended Physical Addressing (XPA).
+ *
+ * @param PageMap
+ *        Supplies a pointer to the page map to be used.
+ *
+ * @return This routine does not return any value.
+ *
+ * @since XT 1.0
+ */
+.global ArEnableExtendedPhysicalAddressing
+ArEnableExtendedPhysicalAddressing:
+    /* Save the original CR4 register */
+    movq %cr4, %rax
+
+    /* Save the state of stack pointer and non-volatile registers */
+    movq %rsp, XpaRegisterSaveArea(%rip)
+    movq %rbp, XpaRegisterSaveArea+0x08(%rip)
+    movq %rax, XpaRegisterSaveArea+0x10(%rip)
+    movq %rbx, XpaRegisterSaveArea+0x18(%rip)
+
+    /* Save the original CR0 register */
+    movq %cr0, %rbp
+
+    /* Load temporary GDT required for mode transitions */
+    leaq XpaTemporaryGdtDesc(%rip), %rax
+    movq %rax, XpaTemporaryGdtBase(%rip)
+    lgdtq XpaTemporaryGdtSize(%rip)
+
+    /* Load addresses for entering compatibility mode and re-entering long mode */
+    leaq XpaEnterCompatMode(%rip), %rax
+    leaq XpaEnterLongMode(%rip), %rbx
+
+    /* Push the 32-bit code segment selector and the target address for a far jump */
+    pushq $KGDT_R0_CMCODE
+    pushq %rax
+
+    /* Perform a far return to switch to 32-bit compatibility mode */
+    lretq
+
+XpaEnterCompatMode:
+    /* Enter 32-bit compatibility mode */
+    .code32
+
+    /* Store the PageMap pointer on the stack for future use */
+    pushl %ecx
+
+    /* Set the stack segment to the 32-bit data segment selector */
+    movl $KGDT_R0_DATA, %eax
+    movl %eax, %ss
+
+    /* Disable PGE and PCIDE to ensure all TLB entries will be flushed */
+    movl %cr4, %eax
+    andl $~(CR4_PGE | CR4_PCIDE), %eax
+    movl %eax, %cr4
+
+    /* Temporarily disable paging */
+    movl %ebp, %eax
+    andl $~CR0_PG, %eax
+    movl %eax, %cr0
+
+    /* Disable Long Mode as prerequisite for enabling 5-level paging */
+    movl $X86_MSR_EFER, %ecx
+    rdmsr
+    andl $~X86_MSR_EFER_LME, %eax
+    wrmsr
+
+    /* Transition to 5-level paging (PML5/LA57) */
+    movl %cr4, %eax
+    orl $CR4_LA57, %eax
+    movl %eax, %cr4
+
+    /* Restore the PageMap pointer from the stack and load it into CR3 */
+    popl %ecx
+    movl %ecx, %cr3
+
+    /* Re-enable Long Mode */
+    movl $X86_MSR_EFER, %ecx
+    rdmsr
+    orl $X86_MSR_EFER_LME, %eax
+    wrmsr
+
+    /* Restore CR0 with paging enabled and flush the instruction pipeline */
+    movl %ebp, %cr0
+    call XpaFlushInstructions
+
+XpaFlushInstructions:
+    /* Push the 64-bit code segment selector and the target address for a far jump */
+    pushl $KGDT_R0_CODE
+    pushl %ebx
+
+    /* Perform a far return to switch to 64-bit long mode */
+    lretl
+
+XpaEnterLongMode:
+    /* Enter 64-bit long mode */
+    .code64
+
+    /* Restore the stack pointer and non-volatile registers */
+    movq XpaRegisterSaveArea(%rip), %rsp
+    movq XpaRegisterSaveArea+8(%rip), %rbp
+    movq XpaRegisterSaveArea+0x10(%rip), %rax
+    movq XpaRegisterSaveArea+0x18(%rip), %rbx
+
+    /* Restore the original CR4 register with LA57 bit set */
+    orq $CR4_LA57, %rax
+    movq %rax, %cr4
+
+    /* Return to the caller */
+    retq
+
+/* Data section for saving registers and temporary GDT */
+XpaRegisterSaveArea: .quad 0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000
+XpaTemporaryGdtSize: .short ArEnableExtendedPhysicalAddressingEnd - XpaTemporaryGdtDesc - 1
+XpaTemporaryGdtBase: .quad 0x0000000000000000
+XpaTemporaryGdtDesc: .quad 0x0000000000000000, 0x00CF9A000000FFFF, 0x00AF9A000000FFFF, 0x00CF92000000FFFF
+
+.global ArEnableExtendedPhysicalAddressingEnd
+ArEnableExtendedPhysicalAddressingEnd:
+
+/**
+ * Handles a spurious interrupt allowing it to end up.
+ *
+ * @return This routine does not return any value.
+ *
+ * @since XT 1.0
+ */
+.global ArHandleSpuriousInterrupt
+ArHandleSpuriousInterrupt:
+    iretq
+
+/**
+ * Starts an application processor (AP). This is just a stub.
+ *
+ * @return This routine does not return any value.
+ *
+ * @since XT 1.0
+ */
+.global ArStartApplicationProcessor
+ArStartApplicationProcessor:
+
+.global ArStartApplicationProcessorEnd
+ArStartApplicationProcessorEnd:

xtoskrnl/ar/amd64/boot.S

@@ -1,147 +0,0 @@
-/**
- * PROJECT:         ExectOS
- * COPYRIGHT:       See COPYING.md in the top level directory
- * FILE:            xtoskrnl/ar/amd64/boot.S
- * DESCRIPTION:     AMD64-specific boot code for setting up the low-level CPU environment
- * DEVELOPERS:      Aiken Harris <harraiken91@gmail.com>
- */
-
-#include <ar/amd64/asmsup.h>
-
-.altmacro
-.text
-
-
-/**
- * Enables eXtended Physical Addressing (XPA).
- *
- * @param PageMap
- *        Supplies a pointer to the page map to be used.
- *
- * @return This routine does not return any value.
- *
- * @since XT 1.0
- */
-.global ArEnableExtendedPhysicalAddressing
-ArEnableExtendedPhysicalAddressing:
-    /* Save the original CR4 register */
-    movq %cr4, %rax
-
-    /* Save the state of stack pointer and non-volatile registers */
-    movq %rsp, XpaRegisterSaveArea(%rip)
-    movq %rbp, XpaRegisterSaveArea+0x08(%rip)
-    movq %rax, XpaRegisterSaveArea+0x10(%rip)
-    movq %rbx, XpaRegisterSaveArea+0x18(%rip)
-
-    /* Save the original CR0 register */
-    movq %cr0, %rbp
-
-    /* Load temporary GDT required for mode transitions */
-    leaq XpaTemporaryGdtDesc(%rip), %rax
-    movq %rax, XpaTemporaryGdtBase(%rip)
-    lgdtq XpaTemporaryGdtSize(%rip)
-
-    /* Load addresses for entering compatibility mode and re-entering long mode */
-    leaq XpaEnterCompatMode(%rip), %rax
-    leaq XpaEnterLongMode(%rip), %rbx
-
-    /* Push the 32-bit code segment selector and the target address for a far jump */
-    pushq $GDT_R0_CMCODE
-    pushq %rax
-
-    /* Perform a far return to switch to 32-bit compatibility mode */
-    lretq
-
-XpaEnterCompatMode:
-    /* Enter 32-bit compatibility mode */
-    .code32
-
-    /* Store the PageMap pointer on the stack for future use */
-    pushl %ecx
-
-    /* Set the stack segment to the 32-bit data segment selector */
-    movl $GDT_R0_DATA, %eax
-    movl %eax, %ss
-
-    /* Disable PGE and PCIDE to ensure all TLB entries will be flushed */
-    movl %cr4, %eax
-    andl $~(CR4_PGE | CR4_PCIDE), %eax
-    movl %eax, %cr4
-
-    /* Temporarily disable paging */
-    movl %ebp, %eax
-    andl $~CR0_PG, %eax
-    movl %eax, %cr0
-
-    /* Disable Long Mode as prerequisite for enabling 5-level paging */
-    movl $X86_MSR_EFER, %ecx
-    rdmsr
-    andl $~X86_MSR_EFER_LME, %eax
-    wrmsr
-
-    /* Transition to 5-level paging (PML5/LA57) */
-    movl %cr4, %eax
-    orl $CR4_LA57, %eax
-    movl %eax, %cr4
-
-    /* Restore the PageMap pointer from the stack and load it into CR3 */
-    popl %ecx
-    movl %ecx, %cr3
-
-    /* Re-enable Long Mode */
-    movl $X86_MSR_EFER, %ecx
-    rdmsr
-    orl $X86_MSR_EFER_LME, %eax
-    wrmsr
-
-    /* Restore CR0 with paging enabled and flush the instruction pipeline */
-    movl %ebp, %cr0
-    call XpaFlushInstructions
-
-XpaFlushInstructions:
-    /* Push the 64-bit code segment selector and the target address for a far jump */
-    pushl $GDT_R0_CODE
-    pushl %ebx
-
-    /* Perform a far return to switch to 64-bit long mode */
-    lretl
-
-XpaEnterLongMode:
-    /* Enter 64-bit long mode */
-    .code64
-
-    /* Restore the stack pointer and non-volatile registers */
-    movq XpaRegisterSaveArea(%rip), %rsp
-    movq XpaRegisterSaveArea+8(%rip), %rbp
-    movq XpaRegisterSaveArea+0x10(%rip), %rax
-    movq XpaRegisterSaveArea+0x18(%rip), %rbx
-
-    /* Restore the original CR4 register with LA57 bit set */
-    orq $CR4_LA57, %rax
-    movq %rax, %cr4
-
-    /* Return to the caller */
-    retq
-
-/* Data section for saving registers and temporary GDT */
-XpaRegisterSaveArea: .quad 0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000
-XpaTemporaryGdtSize: .short ArEnableExtendedPhysicalAddressingEnd - XpaTemporaryGdtDesc - 1
-XpaTemporaryGdtBase: .quad 0x0000000000000000
-XpaTemporaryGdtDesc: .quad 0x0000000000000000, 0x00CF9A000000FFFF, 0x00AF9A000000FFFF, 0x00CF92000000FFFF
-
-.global ArEnableExtendedPhysicalAddressingEnd
-ArEnableExtendedPhysicalAddressingEnd:
-
-
-/**
- * Starts an application processor (AP). This is just a stub.
- *
- * @return This routine does not return any value.
- *
- * @since XT 1.0
- */
-.global ArStartApplicationProcessor
-ArStartApplicationProcessor:
-
-.global ArStartApplicationProcessorEnd
-ArStartApplicationProcessorEnd:

xtoskrnl/ar/amd64/data.cc

@@ -26,3 +26,9 @@ KPROCESSOR_BLOCK AR::ProcSup::InitialProcessorBlock;
 
 /* Initial TSS */
 KTSS AR::ProcSup::InitialTss;
+
+/* Initial kernel NMI stack */
+UCHAR AR::ProcSup::NmiStack[KERNEL_STACK_SIZE] = {};
+
+/* Unhandled interrupt routine */
+PINTERRUPT_HANDLER AR::Traps::UnhandledInterruptRoutine = NULLPTR;

xtoskrnl/ar/amd64/procsup.cc

@@ -73,7 +73,7 @@ AR::ProcSup::IdentifyProcessor(VOID)
     /* Get CPU vendor by issueing CPUID instruction */
     RtlZeroMemory(&CpuRegisters, sizeof(CPUID_REGISTERS));
     CpuRegisters.Leaf = CPUID_GET_VENDOR_STRING;
-    CpuFunc::CpuId(&CpuRegisters);
+    AR::CpuFunc::CpuId(&CpuRegisters);
 
     /* Store CPU vendor in processor control block */
     Prcb->CpuId.Vendor = (CPU_VENDOR)CpuRegisters.Ebx;
@@ -85,7 +85,7 @@ AR::ProcSup::IdentifyProcessor(VOID)
     /* Get CPU standard features */
     RtlZeroMemory(&CpuRegisters, sizeof(CPUID_REGISTERS));
     CpuRegisters.Leaf = CPUID_GET_STANDARD1_FEATURES;
-    CpuFunc::CpuId(&CpuRegisters);
+    AR::CpuFunc::CpuId(&CpuRegisters);
 
     /* Store CPU signature in processor control block */
     CpuSignature = *(PCPUID_SIGNATURE)&CpuRegisters.Eax;
@@ -97,23 +97,23 @@ AR::ProcSup::IdentifyProcessor(VOID)
     if(Prcb->CpuId.Vendor == CPU_VENDOR_AMD)
     {
         /* AMD CPU */
-        if(Prcb->CpuId.Family >= 0xF)
+        if(CpuSignature.Family == 0xF)
         {
-            Prcb->CpuId.Family = Prcb->CpuId.Family + CpuSignature.ExtendedFamily;
-            Prcb->CpuId.Model = Prcb->CpuId.Model + (CpuSignature.ExtendedModel << 4);
+            Prcb->CpuId.Family += CpuSignature.ExtendedFamily;
+            Prcb->CpuId.Model += (CpuSignature.ExtendedModel << 4);
         }
     }
     else if(Prcb->CpuId.Vendor == CPU_VENDOR_INTEL)
     {
         /* Intel CPU */
-        if(Prcb->CpuId.Family == 0xF)
+        if(CpuSignature.Family == 0xF)
         {
-            Prcb->CpuId.Family = Prcb->CpuId.Family + CpuSignature.ExtendedFamily;
+            Prcb->CpuId.Family += CpuSignature.ExtendedFamily;
         }
 
-        if((Prcb->CpuId.Family == 0x6) || (Prcb->CpuId.Family == 0xF))
+        if((CpuSignature.Family == 0x6) || (CpuSignature.Family == 0xF))
         {
-            Prcb->CpuId.Model = Prcb->CpuId.Model + (CpuSignature.ExtendedModel << 4);
+            Prcb->CpuId.Model += (CpuSignature.ExtendedModel << 4);
         }
     }
     else
@@ -136,8 +136,8 @@ XTAPI
 VOID
 AR::ProcSup::InitializeProcessor(IN PVOID ProcessorStructures)
 {
+    PVOID KernelBootStack, KernelFaultStack, KernelNmiStack;
     KDESCRIPTOR GdtDescriptor, IdtDescriptor;
-    PVOID KernelBootStack, KernelFaultStack;
     PKPROCESSOR_BLOCK ProcessorBlock;
     PKGDTENTRY Gdt;
     PKIDTENTRY Idt;
@@ -148,7 +148,7 @@ AR::ProcSup::InitializeProcessor(IN PVOID ProcessorStructures)
     {
         /* Assign CPU structures from provided buffer */
         InitializeProcessorStructures(ProcessorStructures, &Gdt, &Tss, &ProcessorBlock,
-                                      &KernelBootStack, &KernelFaultStack);
+                                      &KernelBootStack, &KernelFaultStack, &KernelNmiStack);
 
         /* Use global IDT */
         Idt = InitialIdt;
@@ -159,8 +159,9 @@ AR::ProcSup::InitializeProcessor(IN PVOID ProcessorStructures)
         Gdt = InitialGdt;
         Idt = InitialIdt;
         Tss = &InitialTss;
-        KernelBootStack = &BootStack;
-        KernelFaultStack = &FaultStack;
+        KernelBootStack = (PVOID)((ULONG_PTR)&BootStack + KERNEL_STACK_SIZE);
+        KernelFaultStack = (PVOID)((ULONG_PTR)&FaultStack + KERNEL_STACK_SIZE);
+        KernelNmiStack = (PVOID)((ULONG_PTR)&NmiStack + KERNEL_STACK_SIZE);
         ProcessorBlock = &InitialProcessorBlock;
     }
 
@@ -170,7 +171,7 @@ AR::ProcSup::InitializeProcessor(IN PVOID ProcessorStructures)
     /* Initialize GDT, IDT and TSS */
     InitializeGdt(ProcessorBlock);
     InitializeIdt(ProcessorBlock);
-    InitializeTss(ProcessorBlock, KernelBootStack, KernelFaultStack);
+    InitializeTss(ProcessorBlock, KernelBootStack, KernelFaultStack, KernelNmiStack);
 
     /* Set GDT and IDT descriptors */
     GdtDescriptor.Base = Gdt;
@@ -179,9 +180,9 @@ AR::ProcSup::InitializeProcessor(IN PVOID ProcessorStructures)
     IdtDescriptor.Limit = (IDT_ENTRIES * sizeof(KIDTENTRY)) - 1;
 
     /* Load GDT, IDT and TSS */
-    CpuFunc::LoadGlobalDescriptorTable(&GdtDescriptor.Limit);
-    CpuFunc::LoadInterruptDescriptorTable(&IdtDescriptor.Limit);
-    CpuFunc::LoadTaskRegister((UINT)KGDT_SYS_TSS);
+    AR::CpuFunc::LoadGlobalDescriptorTable(&GdtDescriptor.Limit);
+    AR::CpuFunc::LoadInterruptDescriptorTable(&IdtDescriptor.Limit);
+    AR::CpuFunc::LoadTaskRegister((UINT)KGDT_SYS_TSS);
 
     /* Enter passive IRQ level */
     HL::RunLevel::SetRunLevel(PASSIVE_LEVEL);
@@ -190,8 +191,8 @@ AR::ProcSup::InitializeProcessor(IN PVOID ProcessorStructures)
     InitializeSegments();
 
     /* Set GS base */
-    CpuFunc::WriteModelSpecificRegister(X86_MSR_GSBASE, (ULONGLONG)ProcessorBlock);
-    CpuFunc::WriteModelSpecificRegister(X86_MSR_KERNEL_GSBASE, (ULONGLONG)ProcessorBlock);
+    AR::CpuFunc::WriteModelSpecificRegister(X86_MSR_GSBASE, (ULONGLONG)ProcessorBlock);
+    AR::CpuFunc::WriteModelSpecificRegister(X86_MSR_KERNEL_GSBASE, (ULONGLONG)ProcessorBlock);
 
     /* Initialize processor registers */
     InitializeProcessorRegisters();
@@ -249,34 +250,35 @@ AR::ProcSup::InitializeIdt(IN PKPROCESSOR_BLOCK ProcessorBlock)
     for(Vector = 0; Vector < IDT_ENTRIES; Vector++)
     {
         /* Set the IDT to handle unexpected interrupts */
-        SetIdtGate(ProcessorBlock->IdtBase, Vector, (PVOID)ArTrap0xFF, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0);
+        SetIdtGate(ProcessorBlock->IdtBase, Vector, (PVOID)ArInterruptEntry[Vector], KGDT_R0_CODE,
+                   KIDT_IST_RESERVED, KIDT_ACCESS_RING0, AMD64_INTERRUPT_GATE);
     }
 
     /* Setup IDT handlers for known interrupts and traps */
-    SetIdtGate(ProcessorBlock->IdtBase, 0x00, (PVOID)ArTrap0x00, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0);
-    SetIdtGate(ProcessorBlock->IdtBase, 0x01, (PVOID)ArTrap0x01, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0);
-    SetIdtGate(ProcessorBlock->IdtBase, 0x02, (PVOID)ArTrap0x02, KGDT_R0_CODE, KIDT_IST_PANIC, KIDT_ACCESS_RING0);
-    SetIdtGate(ProcessorBlock->IdtBase, 0x03, (PVOID)ArTrap0x03, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING3);
-    SetIdtGate(ProcessorBlock->IdtBase, 0x04, (PVOID)ArTrap0x04, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING3);
-    SetIdtGate(ProcessorBlock->IdtBase, 0x05, (PVOID)ArTrap0x05, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0);
-    SetIdtGate(ProcessorBlock->IdtBase, 0x06, (PVOID)ArTrap0x06, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0);
-    SetIdtGate(ProcessorBlock->IdtBase, 0x07, (PVOID)ArTrap0x07, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0);
-    SetIdtGate(ProcessorBlock->IdtBase, 0x08, (PVOID)ArTrap0x08, KGDT_R0_CODE, KIDT_IST_PANIC, KIDT_ACCESS_RING0);
-    SetIdtGate(ProcessorBlock->IdtBase, 0x09, (PVOID)ArTrap0x09, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0);
-    SetIdtGate(ProcessorBlock->IdtBase, 0x0A, (PVOID)ArTrap0x0A, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0);
-    SetIdtGate(ProcessorBlock->IdtBase, 0x0B, (PVOID)ArTrap0x0B, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0);
-    SetIdtGate(ProcessorBlock->IdtBase, 0x0C, (PVOID)ArTrap0x0C, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0);
-    SetIdtGate(ProcessorBlock->IdtBase, 0x0D, (PVOID)ArTrap0x0D, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0);
-    SetIdtGate(ProcessorBlock->IdtBase, 0x0E, (PVOID)ArTrap0x0E, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0);
-    SetIdtGate(ProcessorBlock->IdtBase, 0x10, (PVOID)ArTrap0x10, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0);
-    SetIdtGate(ProcessorBlock->IdtBase, 0x11, (PVOID)ArTrap0x11, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0);
-    SetIdtGate(ProcessorBlock->IdtBase, 0x12, (PVOID)ArTrap0x12, KGDT_R0_CODE, KIDT_IST_MCA, KIDT_ACCESS_RING0);
-    SetIdtGate(ProcessorBlock->IdtBase, 0x13, (PVOID)ArTrap0x13, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0);
-    SetIdtGate(ProcessorBlock->IdtBase, 0x1F, (PVOID)ArTrap0x1F, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0);
-    SetIdtGate(ProcessorBlock->IdtBase, 0x2C, (PVOID)ArTrap0x2C, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING3);
-    SetIdtGate(ProcessorBlock->IdtBase, 0x2D, (PVOID)ArTrap0x2D, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING3);
-    SetIdtGate(ProcessorBlock->IdtBase, 0x2F, (PVOID)ArTrap0x2F, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0);
-    SetIdtGate(ProcessorBlock->IdtBase, 0xE1, (PVOID)ArTrap0xE1, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0);
+    SetIdtGate(ProcessorBlock->IdtBase, 0x00, (PVOID)ArTrapEntry[0x00], KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0, AMD64_TRAP_GATE);
+    SetIdtGate(ProcessorBlock->IdtBase, 0x01, (PVOID)ArTrapEntry[0x01], KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0, AMD64_TRAP_GATE);
+    SetIdtGate(ProcessorBlock->IdtBase, 0x02, (PVOID)ArTrapEntry[0x02], KGDT_R0_CODE, KIDT_IST_NMI, KIDT_ACCESS_RING0, AMD64_INTERRUPT_GATE);
+    SetIdtGate(ProcessorBlock->IdtBase, 0x03, (PVOID)ArTrapEntry[0x03], KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING3, AMD64_TRAP_GATE);
+    SetIdtGate(ProcessorBlock->IdtBase, 0x04, (PVOID)ArTrapEntry[0x04], KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING3, AMD64_TRAP_GATE);
+    SetIdtGate(ProcessorBlock->IdtBase, 0x05, (PVOID)ArTrapEntry[0x05], KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0, AMD64_TRAP_GATE);
+    SetIdtGate(ProcessorBlock->IdtBase, 0x06, (PVOID)ArTrapEntry[0x06], KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0, AMD64_TRAP_GATE);
+    SetIdtGate(ProcessorBlock->IdtBase, 0x07, (PVOID)ArTrapEntry[0x07], KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0, AMD64_TRAP_GATE);
+    SetIdtGate(ProcessorBlock->IdtBase, 0x08, (PVOID)ArTrapEntry[0x08], KGDT_R0_CODE, KIDT_IST_PANIC, KIDT_ACCESS_RING0, AMD64_TRAP_GATE);
+    SetIdtGate(ProcessorBlock->IdtBase, 0x09, (PVOID)ArTrapEntry[0x09], KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0, AMD64_TRAP_GATE);
+    SetIdtGate(ProcessorBlock->IdtBase, 0x0A, (PVOID)ArTrapEntry[0x0A], KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0, AMD64_TRAP_GATE);
+    SetIdtGate(ProcessorBlock->IdtBase, 0x0B, (PVOID)ArTrapEntry[0x0B], KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0, AMD64_TRAP_GATE);
+    SetIdtGate(ProcessorBlock->IdtBase, 0x0C, (PVOID)ArTrapEntry[0x0C], KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0, AMD64_TRAP_GATE);
+    SetIdtGate(ProcessorBlock->IdtBase, 0x0D, (PVOID)ArTrapEntry[0x0D], KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0, AMD64_TRAP_GATE);
+    SetIdtGate(ProcessorBlock->IdtBase, 0x0E, (PVOID)ArTrapEntry[0x0E], KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0, AMD64_TRAP_GATE);
+    SetIdtGate(ProcessorBlock->IdtBase, 0x10, (PVOID)ArTrapEntry[0x10], KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0, AMD64_TRAP_GATE);
+    SetIdtGate(ProcessorBlock->IdtBase, 0x11, (PVOID)ArTrapEntry[0x11], KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0, AMD64_TRAP_GATE);
+    SetIdtGate(ProcessorBlock->IdtBase, 0x12, (PVOID)ArTrapEntry[0x12], KGDT_R0_CODE, KIDT_IST_MCA, KIDT_ACCESS_RING0, AMD64_TRAP_GATE);
+    SetIdtGate(ProcessorBlock->IdtBase, 0x13, (PVOID)ArTrapEntry[0x13], KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0, AMD64_TRAP_GATE);
+    SetIdtGate(ProcessorBlock->IdtBase, 0x1F, (PVOID)ArTrapEntry[0x1F], KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0, AMD64_INTERRUPT_GATE);
+    SetIdtGate(ProcessorBlock->IdtBase, 0x2C, (PVOID)ArTrapEntry[0x2C], KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING3, AMD64_TRAP_GATE);
+    SetIdtGate(ProcessorBlock->IdtBase, 0x2D, (PVOID)ArTrapEntry[0x2D], KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING3, AMD64_TRAP_GATE);
+    SetIdtGate(ProcessorBlock->IdtBase, 0x2F, (PVOID)ArTrapEntry[0x2F], KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0, AMD64_INTERRUPT_GATE);
+    SetIdtGate(ProcessorBlock->IdtBase, 0xE1, (PVOID)ArInterruptEntry[0xE1], KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0, AMD64_INTERRUPT_GATE);
 }
 
 /**
@@ -355,45 +357,45 @@ AR::ProcSup::InitializeProcessorRegisters(VOID)
     ULONGLONG PatAttributes;
 
     /* Enable FXSAVE restore */
-    CpuFunc::WriteControlRegister(4, CpuFunc::ReadControlRegister(4) | CR4_FXSR);
+    AR::CpuFunc::WriteControlRegister(4, AR::CpuFunc::ReadControlRegister(4) | CR4_FXSR);
 
     /* Enable XMMI exceptions */
-    CpuFunc::WriteControlRegister(4, CpuFunc::ReadControlRegister(4) | CR4_XMMEXCPT);
+    AR::CpuFunc::WriteControlRegister(4, AR::CpuFunc::ReadControlRegister(4) | CR4_XMMEXCPT);
 
     /* Set debugger extension */
-    CpuFunc::WriteControlRegister(4, CpuFunc::ReadControlRegister(4) | CR4_DE);
+    AR::CpuFunc::WriteControlRegister(4, AR::CpuFunc::ReadControlRegister(4) | CR4_DE);
 
     /* Enable large pages */
-    CpuFunc::WriteControlRegister(4, CpuFunc::ReadControlRegister(4) | CR4_PSE);
+    AR::CpuFunc::WriteControlRegister(4, AR::CpuFunc::ReadControlRegister(4) | CR4_PSE);
 
     /* Enable write-protection */
-    CpuFunc::WriteControlRegister(0, CpuFunc::ReadControlRegister(0) | CR0_WP);
+    AR::CpuFunc::WriteControlRegister(0, AR::CpuFunc::ReadControlRegister(0) | CR0_WP);
 
     /* Set alignment mask */
-    CpuFunc::WriteControlRegister(0, CpuFunc::ReadControlRegister(0) | CR0_AM);
+    AR::CpuFunc::WriteControlRegister(0, AR::CpuFunc::ReadControlRegister(0) | CR0_AM);
 
     /* Disable FPU monitoring */
-    CpuFunc::WriteControlRegister(0, CpuFunc::ReadControlRegister(0) & ~CR0_MP);
+    AR::CpuFunc::WriteControlRegister(0, AR::CpuFunc::ReadControlRegister(0) & ~CR0_MP);
 
     /* Disable x87 FPU exceptions */
-    CpuFunc::WriteControlRegister(0, CpuFunc::ReadControlRegister(0) & ~CR0_NE);
+    AR::CpuFunc::WriteControlRegister(0, AR::CpuFunc::ReadControlRegister(0) & ~CR0_NE);
 
     /* Flush the TLB */
-    CpuFunc::FlushTlb();
+    AR::CpuFunc::FlushTlb();
 
     /* Initialize system call MSRs */
-    Traps::InitializeSystemCallMsrs();
+    AR::Traps::InitializeSystemCallMsrs();
     
     /* Enable No-Execute (NXE) in EFER MSR */
-    CpuFunc::WriteModelSpecificRegister(X86_MSR_EFER, CpuFunc::ReadModelSpecificRegister(X86_MSR_EFER) | X86_MSR_EFER_NXE);
+    AR::CpuFunc::WriteModelSpecificRegister(X86_MSR_EFER, CpuFunc::ReadModelSpecificRegister(X86_MSR_EFER) | X86_MSR_EFER_NXE);
 
     /* Initialize Page Attribute Table */
     PatAttributes = (PAT_TYPE_WB << 0) | (PAT_TYPE_USWC << 8) | (PAT_TYPE_WEAK_UC << 16) | (PAT_TYPE_STRONG_UC << 24) |
                     (PAT_TYPE_WB << 32) | (PAT_TYPE_USWC << 40) | (PAT_TYPE_WEAK_UC << 48) | (PAT_TYPE_STRONG_UC << 56);
-    CpuFunc::WriteModelSpecificRegister(X86_MSR_PAT, PatAttributes);
+    AR::CpuFunc::WriteModelSpecificRegister(X86_MSR_PAT, PatAttributes);
 
     /* Initialize MXCSR register */
-    CpuFunc::LoadMxcsrRegister(INITIAL_MXCSR);
+    AR::CpuFunc::LoadMxcsrRegister(INITIAL_MXCSR);
 }
 
 /**
@@ -428,7 +430,8 @@ AR::ProcSup::InitializeProcessorStructures(IN PVOID ProcessorStructures,
                                            OUT PKTSS *Tss,
                                            OUT PKPROCESSOR_BLOCK *ProcessorBlock,
                                            OUT PVOID *KernelBootStack,
-                                           OUT PVOID *KernelFaultStack)
+                                           OUT PVOID *KernelFaultStack,
+                                           OUT PVOID *KernelNmiStack)
 {
     UINT_PTR Address;
 
@@ -439,8 +442,12 @@ AR::ProcSup::InitializeProcessorStructures(IN PVOID ProcessorStructures,
     *KernelBootStack = (PVOID)Address;
     Address += KERNEL_STACK_SIZE;
 
-    /* Assign a space for kernel fault stack, no advance needed as stack grows down */
+    /* Assign a space for kernel fault stack and advance */
     *KernelFaultStack = (PVOID)Address;
+    Address += KERNEL_STACK_SIZE;
+
+    /* Assign a space for kernel NMI stack, no advance needed as stack grows down */
+    *KernelNmiStack = (PVOID)Address;
 
     /* Assign a space for GDT and advance */
     *Gdt = (PKGDTENTRY)(PVOID)Address;
@@ -466,12 +473,12 @@ VOID
 AR::ProcSup::InitializeSegments(VOID)
 {
     /* Initialize segments */
-    CpuFunc::LoadSegment(SEGMENT_CS, KGDT_R0_CODE);
-    CpuFunc::LoadSegment(SEGMENT_DS, KGDT_R3_DATA | RPL_MASK);
-    CpuFunc::LoadSegment(SEGMENT_ES, KGDT_R3_DATA | RPL_MASK);
-    CpuFunc::LoadSegment(SEGMENT_FS, KGDT_R3_CMTEB | RPL_MASK);
-    CpuFunc::LoadSegment(SEGMENT_GS, KGDT_R3_DATA | RPL_MASK);
-    CpuFunc::LoadSegment(SEGMENT_SS, KGDT_R0_DATA);
+    AR::CpuFunc::LoadSegment(SEGMENT_CS, KGDT_R0_CODE);
+    AR::CpuFunc::LoadSegment(SEGMENT_DS, KGDT_R3_DATA | RPL_MASK);
+    AR::CpuFunc::LoadSegment(SEGMENT_ES, KGDT_R3_DATA | RPL_MASK);
+    AR::CpuFunc::LoadSegment(SEGMENT_FS, KGDT_R3_CMTEB | RPL_MASK);
+    AR::CpuFunc::LoadSegment(SEGMENT_GS, KGDT_R3_DATA | RPL_MASK);
+    AR::CpuFunc::LoadSegment(SEGMENT_SS, KGDT_R0_DATA);
 }
 
 /**
@@ -491,7 +498,8 @@ XTAPI
 VOID
 AR::ProcSup::InitializeTss(IN PKPROCESSOR_BLOCK ProcessorBlock,
                            IN PVOID KernelBootStack,
-                           IN PVOID KernelFaultStack)
+                           IN PVOID KernelFaultStack,
+                           IN PVOID KernelNmiStack)
 {
     /* Fill TSS with zeroes */
     RtlZeroMemory(ProcessorBlock->TssBase, sizeof(KTSS));
@@ -501,6 +509,7 @@ AR::ProcSup::InitializeTss(IN PKPROCESSOR_BLOCK ProcessorBlock,
     ProcessorBlock->TssBase->Rsp0 = (ULONG_PTR)KernelBootStack;
     ProcessorBlock->TssBase->Ist[KIDT_IST_PANIC] = (ULONG_PTR)KernelFaultStack;
     ProcessorBlock->TssBase->Ist[KIDT_IST_MCA] = (ULONG_PTR)KernelFaultStack;
+    ProcessorBlock->TssBase->Ist[KIDT_IST_NMI] = (ULONG_PTR)KernelNmiStack;
 }
 
 /**
@@ -636,6 +645,9 @@ AR::ProcSup::SetGdtEntryBase(IN PKGDTENTRY Gdt,
  * @param Access
  *        Supplies the gate access rights.
  *
+ * @param Type
+ *        Supplies the gate type.
+ *
  * @return This routine does not return any value.
  *
  * @since XT 1.0
@@ -647,15 +659,22 @@ AR::ProcSup::SetIdtGate(IN PKIDTENTRY Idt,
                         IN PVOID Handler,
                         IN USHORT Selector,
                         IN USHORT Ist,
-                        IN USHORT Access)
+                        IN USHORT Dpl,
+                        IN USHORT Type)
 {
-    /* Setup the gate */
+    /* Set the handler's address */
     Idt[Vector].OffsetLow = ((ULONG_PTR)Handler & 0xFFFF);
     Idt[Vector].OffsetMiddle = (((ULONG_PTR)Handler >> 16) & 0xFFFF);
     Idt[Vector].OffsetHigh = (ULONG_PTR)Handler >> 32;
-    Idt[Vector].Dpl = Access;
+
+    /* Set the code segment selector */
+    Idt[Vector].Selector = Selector;
+
+    /* Initialize the gate's attributes and flags */
+    Idt[Vector].Access = 0;
+    Idt[Vector].Dpl = Dpl;
     Idt[Vector].IstIndex = Ist;
     Idt[Vector].Present = 1;
-    Idt[Vector].Selector = Selector;
-    Idt[Vector].Type = 0xE;
+    Idt[Vector].Reserved1 = 0;
+    Idt[Vector].Type = Type;
 }

xtoskrnl/ar/amd64/traps.cc

@@ -9,6 +9,44 @@
 #include <xtos.hh>
 
 
+/**
+ * Dispatches the interrupt provided by common interrupt handler.
+ *
+ * @param TrapFrame
+ *        Supplies a kernel trap frame pushed by common interrupt handler on the stack.
+ *
+ * @return This routine does not return any value.
+ *
+ * @since XT 1.0
+ */
+XTCDECL
+VOID
+AR::Traps::DispatchInterrupt(IN PKTRAP_FRAME TrapFrame)
+{
+    PINTERRUPT_HANDLER Handler;
+
+    /* Read the handler pointer from the CPU's interrupt dispatch table */
+    Handler = (PINTERRUPT_HANDLER)AR::CpuFunc::ReadGSQuadWord(FIELD_OFFSET(KPROCESSOR_BLOCK, InterruptDispatchTable) +
+                                                              (TrapFrame->Vector * sizeof(PINTERRUPT_HANDLER)));
+
+    /* Check if the interrupt has a handler registered */
+    if(Handler != NULLPTR)
+    {
+        /* Call the handler */
+        Handler(TrapFrame);
+    }
+    else if(UnhandledInterruptRoutine != NULLPTR)
+    {
+        /* Call the unhandled interrupt routine */
+        UnhandledInterruptRoutine(TrapFrame);
+    }
+    else
+    {
+        /* Dispatcher not initialized, print a debug message */
+        DebugPrint(L"ERROR: Caught unhandled interrupt: 0x%.2llX\n", TrapFrame->Vector);
+    }
+}
+
 /**
  * Dispatches the trap provided by common trap handler.
  *
@@ -227,7 +265,6 @@ VOID
 AR::Traps::HandleTrap02(IN PKTRAP_FRAME TrapFrame)
 {
     DebugPrint(L"Handled Non-Maskable-Interrupt (0x02)!\n");
-    KE::Crash::Panic(0x02);
 }
 
 /**
@@ -645,19 +682,19 @@ AR::Traps::InitializeSystemCallMsrs(VOID)
 }
 
 /**
- * C-linkage wrapper for dispatching the trap provided by common trap handler.
+ * Sets the unhandled interrupt routine used for vectors that have no handler registered.
  *
- * @param TrapFrame
- *        Supplies a kernel trap frame pushed by common trap handler on the stack.
+ * @param Handler
+ *        Supplies the pointer to the interrupt handler routine.
  *
  * @return This routine does not return any value.
  *
  * @since XT 1.0
  */
-XTCLINK
-XTCDECL
+XTAPI
 VOID
-ArDispatchTrap(IN PKTRAP_FRAME TrapFrame)
+AR::Traps::SetUnhandledInterruptRoutine(PINTERRUPT_HANDLER Handler)
 {
-    AR::Traps::DispatchTrap(TrapFrame);
+    /* Set the unhandled interrupt routine */
+    UnhandledInterruptRoutine = Handler;
 }

xtoskrnl/ar/i686/archsup.S

@@ -4,123 +4,244 @@
  * FILE:            xtoskrnl/ar/i686/archsup.S
  * DESCRIPTION:     Provides i686 architecture features not implementable in C.
  * DEVELOPERS:      Rafal Kupiec <belliash@codingworkshop.eu.org>
+ *                  Aiken Harris <harraiken91@gmail.com>
  */
 
-#include <ar/i686/asmsup.h>
+#include <xtkmapi.h>
+#include <xtadk.h>
 
 .altmacro
 .text
 
 
 /**
- * This macro creates a trap handler for the specified vector.
+ * Creates a task, trap or interrupt handler for the specified vector.
  *
  * @param Vector
- *        Supplies a trap vector number.
+ *        Supplies a vector number.
+ *
+ * @param Type
+ *        Specifies whether the handler is designed to handle an interrupt, a task or a trap.
  *
  * @return This macro does not return any value.
  *
  * @since XT 1.0
  */
-.macro ArCreateTrapHandler Vector
-.global _ArTrap\Vector
-_ArTrap\Vector:
-    /* Push fake error code for non-error vectors */
-    .if \Vector != 8 && \Vector != 10 && \Vector != 11 && \Vector != 12 && \Vector != 13 && \Vector != 14 && \Vector != 17 && \Vector != 30
-        push $0
+.macro ArCreateHandler Vector Type
+.global _Ar\Type\Vector
+_Ar\Type\Vector:
+     /* Check handler type */
+    .ifc \Type,Task
+_Ar\Type\Vector\()Start:
+        /* Clear the Task Switch flag */
+        clts
+
+        /* Allocate the trap frame and inject the hardware vector for the dispatcher */
+        sub $KTRAP_FRAME_SIZE, %esp
+        movl $\Vector, KTRAP_FRAME_Vector(%esp)
+
+        /* Pass the trap frame pointer as an argument and clear the direction flag */
+        push %esp
+        cld
+
+        /* Pass control to the trap dispatcher */
+        call _ArDispatchTrap
+
+        /* Discard the argument and deallocate the trap frame */
+        add $4, %esp
+        add $KTRAP_FRAME_SIZE, %esp
+
+        /* Hardware task return */
+        iretl
+
+        /* Spin back to the entry point to rearm the task gate */
+        jmp _Ar\Type\Vector\()Start
+    .else
+        /* Check handler type */
+        .ifc \Type,Trap
+            /* Push fake error code for non-error vector traps */
+            .if \Vector != 8 && \Vector != 10 && \Vector != 11 && \Vector != 12 && \Vector != 13 && \Vector != 14 && \Vector != 17 && \Vector != 30
+                push $0
+            .endif
+        .else
+            /* Push fake error code for interrupts */
+            push $0
+        .endif
+
+        /* Push vector number */
+        push $\Vector
+
+        /* Push General Purpose Registers */
+        push %ebp
+        push %edi
+        push %esi
+        push %edx
+        push %ecx
+        push %ebx
+        push %eax
+
+        /* Reserve space for other registers and point RBP to the trap frame */
+        sub $(KTRAP_FRAME_SIZE - KTRAP_FRAME_REGISTERS_SIZE), %esp
+        lea (%esp), %ebp
+
+        /* Store segment selectors */
+        mov %gs, KTRAP_FRAME_SegGs(%ebp)
+        mov %fs, KTRAP_FRAME_SegFs(%ebp)
+        mov %es, KTRAP_FRAME_SegEs(%ebp)
+        mov %ds, KTRAP_FRAME_SegDs(%ebp)
+
+        /* Store debug registers */
+        mov %dr7, %eax
+        mov %eax, KTRAP_FRAME_Dr7(%ebp)
+        mov %dr6, %eax
+        mov %eax, KTRAP_FRAME_Dr6(%ebp)
+        mov %dr3, %eax
+        mov %eax, KTRAP_FRAME_Dr3(%ebp)
+        mov %dr2, %eax
+        mov %eax, KTRAP_FRAME_Dr2(%ebp)
+        mov %dr1, %eax
+        mov %eax, KTRAP_FRAME_Dr1(%ebp)
+        mov %dr0, %eax
+        mov %eax, KTRAP_FRAME_Dr0(%ebp)
+
+        /* Store CR2 and CR3 */
+        mov %cr3, %eax
+        mov %eax, KTRAP_FRAME_Cr3(%ebp)
+        mov %cr2, %eax
+        mov %eax, KTRAP_FRAME_Cr2(%ebp)
+
+        /* Test previous mode */
+        movl $0, KTRAP_FRAME_PreviousMode(%ebp)
+        mov KTRAP_FRAME_SegCs(%ebp), %ax
+        and $3, %al
+        mov %al, KTRAP_FRAME_PreviousMode(%ebp)
+        jz Dispatch\Type\Vector
+
+        /* Load Kernel PB selector into FS */
+        mov $KGDT_R0_PB, %ax
+        mov %ax, %fs
+
+        /* Set sane data segment selectors */
+        mov $(KGDT_R3_DATA | RPL_MASK), %ax
+        mov %ax, %ds
+        mov %ax, %es
+
+Dispatch\Type\Vector:
+        /* Push Frame Pointer and clear direction flag */
+        push %esp
+        cld
+
+        .ifc \Type,Trap
+            /* Pass to the trap dispatcher */
+            call _ArDispatchTrap
+        .else
+            /* Pass to the interrupt dispatcher */
+            call _ArDispatchInterrupt
+        .endif
+
+        /* Clean up the stack */
+        add $4, %esp
+
+        /* Test previous mode and disable interrupts before user mode return */
+        testb $1, KTRAP_FRAME_PreviousMode(%ebp)
+        jz RestoreState\Type\Vector
+        cli
+
+RestoreState\Type\Vector:
+        /* Restore segment selectors */
+        mov KTRAP_FRAME_SegDs(%ebp), %ds
+        mov KTRAP_FRAME_SegEs(%ebp), %es
+        mov KTRAP_FRAME_SegFs(%ebp), %fs
+        mov KTRAP_FRAME_SegGs(%ebp), %gs
+
+        /* Free stack space */
+        add $(KTRAP_FRAME_SIZE - KTRAP_FRAME_REGISTERS_SIZE), %esp
+
+        /* Pop General Purpose Registers */
+        pop %eax
+        pop %ebx
+        pop %ecx
+        pop %edx
+        pop %esi
+        pop %edi
+        pop %ebp
+
+        /* Skip error code and vector number, then return */
+        add $(2 * 4), %esp
+        iretl
     .endif
-
-    /* Push vector number */
-    push $\Vector
-
-    /* Push General Purpose Registers */
-    push %ebp
-    push %edi
-    push %esi
-    push %edx
-    push %ecx
-    push %ebx
-    push %eax
-
-    /* Reserve space for other registers and point RBP to the trap frame */
-    sub $(TRAP_FRAME_SIZE - TRAP_REGISTERS_SIZE), %esp
-    lea (%esp), %ebp
-
-    /* Store segment selectors */
-    mov %gs, TrapSegGs(%ebp)
-    mov %fs, TrapSegFs(%ebp)
-    mov %es, TrapSegEs(%ebp)
-    mov %ds, TrapSegDs(%ebp)
-
-    /* Store debug registers */
-    mov %dr7, %eax
-    mov %eax, TrapDr7(%ebp)
-    mov %dr6, %eax
-    mov %eax, TrapDr6(%ebp)
-    mov %dr3, %eax
-    mov %eax, TrapDr3(%ebp)
-    mov %dr2, %eax
-    mov %eax, TrapDr2(%ebp)
-    mov %dr1, %eax
-    mov %eax, TrapDr1(%ebp)
-    mov %dr0, %eax
-    mov %eax, TrapDr0(%ebp)
-
-    /* Store CR2 and CR3 */
-    mov %cr3, %eax
-    mov %eax, TrapCr3(%ebp)
-    mov %cr2, %eax
-    mov %eax, TrapCr2(%ebp)
-
-    /* Test previous mode and swap GS if needed */
-    movl $0, TrapPreviousMode(%ebp)
-    mov %cs, %ax
-    and $1, %al
-    mov %al, TrapPreviousMode(%ebp)
-    jz KernelMode$\Vector
-    swapgs
-
-KernelMode$\Vector:
-    /* Push Frame Pointer, clear direction flag and pass to trap dispatcher */
-    push %esp
-    cld
-    call _ArDispatchTrap
-
-    /* Clean up the stack */
-    add $4, %esp
-
-    /* Test previous mode and swapgs if needed */
-    testb $1, TrapPreviousMode(%ebp)
-    jz KernelModeReturn$\Vector
-    cli
-    swapgs
-
-KernelModeReturn$\Vector:
-    /* Restore segment selectors */
-    mov TrapSegDs(%ebp), %ds
-    mov TrapSegEs(%ebp), %es
-    mov TrapSegFs(%ebp), %fs
-
-    /* Free stack space */
-    add $(TRAP_FRAME_SIZE - TRAP_REGISTERS_SIZE), %esp
-
-    /* Pop General Purpose Registers */
-    pop %eax
-    pop %ebx
-    pop %ecx
-    pop %edx
-    pop %esi
-    pop %edi
-    pop %ebp
-
-    /* Skip error code and vector number, then return */
-    add $(2 * 4), %esp
-    iretl
 .endm
 
-/* Populate common trap handlers */
+/* Populate common interrupt, task and trap handlers */
 .irp i,0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F
     .irp j,0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F
-        ArCreateTrapHandler 0x\i\j
+        ArCreateHandler 0x\i\j Interrupt
+        .if 0x\i\j == 0x02 || 0x\i\j == 0x08
+            ArCreateHandler 0x\i\j Task
+        .else
+            ArCreateHandler 0x\i\j Trap
+        .endif
     .endr
 .endr
+
+/* Define array of pointers to the interrupt handlers */
+.global _ArInterruptEntry
+_ArInterruptEntry:
+.irp i,0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F
+    .irp j,0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F
+        .long _ArInterrupt0x\i\j
+    .endr
+.endr
+
+/* Define array of pointers to the trap handlers */
+.global _ArTrapEntry
+_ArTrapEntry:
+.irp i,0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F
+    .irp j,0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F
+        .if 0x\i\j == 0x02 || 0x\i\j == 0x08
+            .long _ArTask0x\i\j
+        .else
+            .long _ArTrap0x\i\j
+        .endif
+    .endr
+.endr
+
+/**
+ * Enables eXtended Physical Addressing (XPA). On i386, this is just a stub.
+ *
+ * @param PageMap
+ *        Supplies a pointer to the page map to be used.
+ *
+ * @return This routine does not return any value.
+ *
+ * @since XT 1.0
+ */
+.global ArEnableExtendedPhysicalAddressing
+ArEnableExtendedPhysicalAddressing:
+
+.global ArEnableExtendedPhysicalAddressingEnd
+ArEnableExtendedPhysicalAddressingEnd:
+
+/**
+ * Handles a spurious interrupt allowing it to end up.
+ *
+ * @return This routine does not return any value.
+ *
+ * @since XT 1.0
+ */
+.global _ArHandleSpuriousInterrupt
+_ArHandleSpuriousInterrupt:
+    iret
+
+/**
+ * Starts an application processor (AP). This is just a stub.
+ *
+ * @return This routine does not return any value.
+ *
+ * @since XT 1.0
+ */
+.global _ArStartApplicationProcessor
+_ArStartApplicationProcessor:
+
+.global _ArStartApplicationProcessorEnd
+_ArStartApplicationProcessorEnd:

xtoskrnl/ar/i686/boot.S

@@ -1,26 +0,0 @@
-/**
- * PROJECT:         ExectOS
- * COPYRIGHT:       See COPYING.md in the top level directory
- * FILE:            xtoskrnl/ar/i686/boot.S
- * DESCRIPTION:     i686-specific boot code for setting up the low-level CPU environment
- * DEVELOPERS:      Aiken Harris <harraiken91@gmail.com>
- */
-
-#include <ar/amd64/asmsup.h>
-
-.altmacro
-.text
-
-
-/**
- * Starts an application processor (AP). This is just a stub.
- *
- * @return This routine does not return any value.
- *
- * @since XT 1.0
- */
-.global _ArStartApplicationProcessor
-_ArStartApplicationProcessor:
-
-.global _ArStartApplicationProcessorEnd
-_ArStartApplicationProcessorEnd:

xtoskrnl/ar/i686/data.cc

@@ -30,5 +30,11 @@ KPROCESSOR_BLOCK AR::ProcSup::InitialProcessorBlock;
 /* Initial TSS */
 KTSS AR::ProcSup::InitialTss;
 
+/* Initial kernel NMI stack */
+UCHAR AR::ProcSup::NmiStack[KERNEL_STACK_SIZE] = {};
+
 /* NMI task gate */
 UCHAR AR::ProcSup::NonMaskableInterruptTss[KTSS_IO_MAPS];
+
+/* Unhandled interrupt routine */
+PINTERRUPT_HANDLER AR::Traps::UnhandledInterruptRoutine = NULLPTR;

xtoskrnl/ar/i686/procsup.cc

@@ -68,7 +68,7 @@ AR::ProcSup::IdentifyProcessor(VOID)
     /* Get CPU vendor by issueing CPUID instruction */
     RtlZeroMemory(&CpuRegisters, sizeof(CPUID_REGISTERS));
     CpuRegisters.Leaf = CPUID_GET_VENDOR_STRING;
-    CpuFunc::CpuId(&CpuRegisters);
+    AR::CpuFunc::CpuId(&CpuRegisters);
 
     /* Store CPU vendor in processor control block */
     Prcb->CpuId.Vendor = (CPU_VENDOR)CpuRegisters.Ebx;
@@ -80,7 +80,7 @@ AR::ProcSup::IdentifyProcessor(VOID)
     /* Get CPU standard features */
     RtlZeroMemory(&CpuRegisters, sizeof(CPUID_REGISTERS));
     CpuRegisters.Leaf = CPUID_GET_STANDARD1_FEATURES;
-    CpuFunc::CpuId(&CpuRegisters);
+    AR::CpuFunc::CpuId(&CpuRegisters);
 
     /* Store CPU signature in processor control block */
     CpuSignature = *(PCPUID_SIGNATURE)&CpuRegisters.Eax;
@@ -92,23 +92,23 @@ AR::ProcSup::IdentifyProcessor(VOID)
     if(Prcb->CpuId.Vendor == CPU_VENDOR_AMD)
     {
         /* AMD CPU */
-        if(Prcb->CpuId.Family >= 0xF)
+        if(CpuSignature.Family == 0xF)
         {
-            Prcb->CpuId.Family = Prcb->CpuId.Family + CpuSignature.ExtendedFamily;
-            Prcb->CpuId.Model = Prcb->CpuId.Model + (CpuSignature.ExtendedModel << 4);
+            Prcb->CpuId.Family += CpuSignature.ExtendedFamily;
+            Prcb->CpuId.Model += (CpuSignature.ExtendedModel << 4);
         }
     }
     else if(Prcb->CpuId.Vendor == CPU_VENDOR_INTEL)
     {
         /* Intel CPU */
-        if(Prcb->CpuId.Family == 0xF)
+        if(CpuSignature.Family == 0xF)
         {
-            Prcb->CpuId.Family = Prcb->CpuId.Family + CpuSignature.ExtendedFamily;
+            Prcb->CpuId.Family += CpuSignature.ExtendedFamily;
         }
 
-        if((Prcb->CpuId.Family == 0x6) || (Prcb->CpuId.Family == 0xF))
+        if((CpuSignature.Family == 0x6) || (CpuSignature.Family == 0xF))
         {
-            Prcb->CpuId.Model = Prcb->CpuId.Model + (CpuSignature.ExtendedModel << 4);
+            Prcb->CpuId.Model += (CpuSignature.ExtendedModel << 4);
         }
     }
     else
@@ -132,7 +132,7 @@ VOID
 AR::ProcSup::InitializeProcessor(IN PVOID ProcessorStructures)
 {
     KDESCRIPTOR GdtDescriptor, IdtDescriptor;
-    PVOID KernelBootStack, KernelFaultStack;
+    PVOID KernelBootStack, KernelFaultStack, KernelNmiStack;
     PKPROCESSOR_BLOCK ProcessorBlock;
     PKGDTENTRY Gdt;
     PKIDTENTRY Idt;
@@ -143,7 +143,7 @@ AR::ProcSup::InitializeProcessor(IN PVOID ProcessorStructures)
     {
         /* Assign CPU structures from provided buffer */
         InitializeProcessorStructures(ProcessorStructures, &Gdt, &Tss, &ProcessorBlock,
-                                      &KernelBootStack, &KernelFaultStack);
+                                      &KernelBootStack, &KernelFaultStack, &KernelNmiStack);
 
         /* Use global IDT */
         Idt = InitialIdt;
@@ -154,8 +154,9 @@ AR::ProcSup::InitializeProcessor(IN PVOID ProcessorStructures)
         Gdt = InitialGdt;
         Idt = InitialIdt;
         Tss = &InitialTss;
-        KernelBootStack = &BootStack;
-        KernelFaultStack = &FaultStack;
+        KernelBootStack = (PVOID)((ULONG_PTR)&BootStack + KERNEL_STACK_SIZE);
+        KernelFaultStack = (PVOID)((ULONG_PTR)&FaultStack + KERNEL_STACK_SIZE);
+        KernelNmiStack = (PVOID)((ULONG_PTR)&NmiStack + KERNEL_STACK_SIZE);
         ProcessorBlock = &InitialProcessorBlock;
     }
 
@@ -165,7 +166,7 @@ AR::ProcSup::InitializeProcessor(IN PVOID ProcessorStructures)
     /* Initialize GDT, IDT and TSS */
     InitializeGdt(ProcessorBlock);
     InitializeIdt(ProcessorBlock);
-    InitializeTss(ProcessorBlock, KernelBootStack, KernelFaultStack);
+    InitializeTss(ProcessorBlock, KernelBootStack, KernelFaultStack, KernelNmiStack);
 
     /* Set GDT and IDT descriptors */
     GdtDescriptor.Base = Gdt;
@@ -174,9 +175,9 @@ AR::ProcSup::InitializeProcessor(IN PVOID ProcessorStructures)
     IdtDescriptor.Limit = (IDT_ENTRIES * sizeof(KIDTENTRY)) - 1;
 
     /* Load GDT, IDT and TSS */
-    CpuFunc::LoadGlobalDescriptorTable(&GdtDescriptor.Limit);
-    CpuFunc::LoadInterruptDescriptorTable(&IdtDescriptor.Limit);
-    CpuFunc::LoadTaskRegister((UINT)KGDT_SYS_TSS);
+    AR::CpuFunc::LoadGlobalDescriptorTable(&GdtDescriptor.Limit);
+    AR::CpuFunc::LoadInterruptDescriptorTable(&IdtDescriptor.Limit);
+    AR::CpuFunc::LoadTaskRegister((UINT)KGDT_SYS_TSS);
 
     /* Enter passive IRQ level */
     HL::RunLevel::SetRunLevel(PASSIVE_LEVEL);
@@ -215,9 +216,9 @@ AR::ProcSup::InitializeGdt(IN PKPROCESSOR_BLOCK ProcessorBlock)
     SetGdtEntry(ProcessorBlock->GdtBase, KGDT_R0_PB, (ULONG_PTR)ProcessorBlock, sizeof(KPROCESSOR_BLOCK), KGDT_TYPE_DATA, KGDT_DPL_SYSTEM, 2);
     SetGdtEntry(ProcessorBlock->GdtBase, KGDT_R3_TEB, 0x0, 0xFFF, KGDT_TYPE_DATA | KGDT_DESCRIPTOR_ACCESSED, KGDT_DPL_USER, 2);
     SetGdtEntry(ProcessorBlock->GdtBase, KGDT_VDM_TILE, 0x0400, 0xFFFF, KGDT_TYPE_DATA, KGDT_DPL_USER, 0);
-    SetGdtEntry(ProcessorBlock->GdtBase, KGDT_R0_LDT, 0x0, 0x0, KGDT_TYPE_NONE, KGDT_DPL_SYSTEM, 0);
+    SetGdtEntry(ProcessorBlock->GdtBase, KGDT_R0_LDT, 0x0, 0x0, I686_LDT, KGDT_DPL_SYSTEM, 0);
     SetGdtEntry(ProcessorBlock->GdtBase, KGDT_DF_TSS, 0x20000, 0xFFFF, I686_TSS, KGDT_DPL_SYSTEM, 0);
-    SetGdtEntry(ProcessorBlock->GdtBase, KGDT_NMI_TSS, 0x20000, 0xFFFF, KGDT_TYPE_CODE, KGDT_DPL_SYSTEM, 0);
+    SetGdtEntry(ProcessorBlock->GdtBase, KGDT_NMI_TSS, 0x20000, 0xFFFF, I686_TSS, KGDT_DPL_SYSTEM, 0);
     SetGdtEntry(ProcessorBlock->GdtBase, KGDT_VDBS, 0xB8000, 0x3FFF, KGDT_TYPE_DATA, KGDT_DPL_SYSTEM, 0);
     SetGdtEntry(ProcessorBlock->GdtBase, KGDT_ALIAS, (ULONG_PTR)ProcessorBlock->GdtBase, (GDT_ENTRIES * sizeof(KGDTENTRY)) - 1, KGDT_TYPE_DATA, KGDT_DPL_SYSTEM, 0);
 }
@@ -242,34 +243,35 @@ AR::ProcSup::InitializeIdt(IN PKPROCESSOR_BLOCK ProcessorBlock)
     for(Vector = 0; Vector < IDT_ENTRIES; Vector++)
     {
         /* Set the IDT to handle unexpected interrupts */
-        SetIdtGate(ProcessorBlock->IdtBase, Vector, (PVOID)ArTrap0xFF, KGDT_R0_CODE, 0, KIDT_INTERRUPT | KIDT_ACCESS_RING0);
+        SetIdtGate(ProcessorBlock->IdtBase, Vector, (PVOID)ArInterruptEntry[Vector],
+                   KGDT_R0_CODE, 0, KIDT_ACCESS_RING0, I686_INTERRUPT_GATE);
     }
 
     /* Setup IDT handlers for known interrupts and traps */
-    SetIdtGate(ProcessorBlock->IdtBase, 0x00, (PVOID)ArTrap0x00, KGDT_R0_CODE, 0, KIDT_INTERRUPT | KIDT_ACCESS_RING0);
-    SetIdtGate(ProcessorBlock->IdtBase, 0x01, (PVOID)ArTrap0x01, KGDT_R0_CODE, 0, KIDT_INTERRUPT | KIDT_ACCESS_RING0);
-    SetIdtGate(ProcessorBlock->IdtBase, 0x02, (PVOID)ArTrap0x02, KGDT_R0_CODE, 0, KIDT_INTERRUPT | KIDT_ACCESS_RING0);
-    SetIdtGate(ProcessorBlock->IdtBase, 0x03, (PVOID)ArTrap0x03, KGDT_R0_CODE, 0, KIDT_INTERRUPT | KIDT_ACCESS_RING3);
-    SetIdtGate(ProcessorBlock->IdtBase, 0x04, (PVOID)ArTrap0x04, KGDT_R0_CODE, 0, KIDT_INTERRUPT | KIDT_ACCESS_RING3);
-    SetIdtGate(ProcessorBlock->IdtBase, 0x05, (PVOID)ArTrap0x05, KGDT_R0_CODE, 0, KIDT_INTERRUPT | KIDT_ACCESS_RING0);
-    SetIdtGate(ProcessorBlock->IdtBase, 0x06, (PVOID)ArTrap0x06, KGDT_R0_CODE, 0, KIDT_INTERRUPT | KIDT_ACCESS_RING0);
-    SetIdtGate(ProcessorBlock->IdtBase, 0x07, (PVOID)ArTrap0x07, KGDT_R0_CODE, 0, KIDT_INTERRUPT | KIDT_ACCESS_RING0);
-    SetIdtGate(ProcessorBlock->IdtBase, 0x08, (PVOID)ArTrap0x08, KGDT_R0_CODE, 0, KIDT_INTERRUPT | KIDT_ACCESS_RING0);
-    SetIdtGate(ProcessorBlock->IdtBase, 0x09, (PVOID)ArTrap0x09, KGDT_R0_CODE, 0, KIDT_INTERRUPT | KIDT_ACCESS_RING0);
-    SetIdtGate(ProcessorBlock->IdtBase, 0x0A, (PVOID)ArTrap0x0A, KGDT_R0_CODE, 0, KIDT_INTERRUPT | KIDT_ACCESS_RING0);
-    SetIdtGate(ProcessorBlock->IdtBase, 0x0B, (PVOID)ArTrap0x0B, KGDT_R0_CODE, 0, KIDT_INTERRUPT | KIDT_ACCESS_RING0);
-    SetIdtGate(ProcessorBlock->IdtBase, 0x0C, (PVOID)ArTrap0x0C, KGDT_R0_CODE, 0, KIDT_INTERRUPT | KIDT_ACCESS_RING0);
-    SetIdtGate(ProcessorBlock->IdtBase, 0x0D, (PVOID)ArTrap0x0D, KGDT_R0_CODE, 0, KIDT_INTERRUPT | KIDT_ACCESS_RING0);
-    SetIdtGate(ProcessorBlock->IdtBase, 0x0E, (PVOID)ArTrap0x0E, KGDT_R0_CODE, 0, KIDT_INTERRUPT | KIDT_ACCESS_RING0);
-    SetIdtGate(ProcessorBlock->IdtBase, 0x10, (PVOID)ArTrap0x10, KGDT_R0_CODE, 0, KIDT_INTERRUPT | KIDT_ACCESS_RING0);
-    SetIdtGate(ProcessorBlock->IdtBase, 0x11, (PVOID)ArTrap0x11, KGDT_R0_CODE, 0, KIDT_INTERRUPT | KIDT_ACCESS_RING0);
-    SetIdtGate(ProcessorBlock->IdtBase, 0x12, (PVOID)ArTrap0x12, KGDT_R0_CODE, 0, KIDT_INTERRUPT | KIDT_ACCESS_RING0);
-    SetIdtGate(ProcessorBlock->IdtBase, 0x13, (PVOID)ArTrap0x13, KGDT_R0_CODE, 0, KIDT_INTERRUPT | KIDT_ACCESS_RING0);
-    SetIdtGate(ProcessorBlock->IdtBase, 0x2A, (PVOID)ArTrap0x2A, KGDT_R0_CODE, 0, KIDT_INTERRUPT | KIDT_ACCESS_RING3);
-    SetIdtGate(ProcessorBlock->IdtBase, 0x2B, (PVOID)ArTrap0x2B, KGDT_R0_CODE, 0, KIDT_INTERRUPT | KIDT_ACCESS_RING3);
-    SetIdtGate(ProcessorBlock->IdtBase, 0x2C, (PVOID)ArTrap0x2C, KGDT_R0_CODE, 0, KIDT_INTERRUPT | KIDT_ACCESS_RING3);
-    SetIdtGate(ProcessorBlock->IdtBase, 0x2D, (PVOID)ArTrap0x2D, KGDT_R0_CODE, 0, KIDT_INTERRUPT | KIDT_ACCESS_RING3);
-    SetIdtGate(ProcessorBlock->IdtBase, 0x2E, (PVOID)ArTrap0x2E, KGDT_R0_CODE, 0, KIDT_INTERRUPT | KIDT_ACCESS_RING3);
+    SetIdtGate(ProcessorBlock->IdtBase, 0x00, (PVOID)ArTrapEntry[0x00], KGDT_R0_CODE, 0, KIDT_ACCESS_RING0, I686_INTERRUPT_GATE);
+    SetIdtGate(ProcessorBlock->IdtBase, 0x01, (PVOID)ArTrapEntry[0x01], KGDT_R0_CODE, 0, KIDT_ACCESS_RING0, I686_INTERRUPT_GATE);
+    SetIdtGate(ProcessorBlock->IdtBase, 0x02, (PVOID)ArTrapEntry[0x02], KGDT_R0_CODE, 0, KIDT_ACCESS_RING0, I686_TASK_GATE);
+    SetIdtGate(ProcessorBlock->IdtBase, 0x03, (PVOID)ArTrapEntry[0x03], KGDT_R0_CODE, 0, KIDT_ACCESS_RING3, I686_INTERRUPT_GATE);
+    SetIdtGate(ProcessorBlock->IdtBase, 0x04, (PVOID)ArTrapEntry[0x04], KGDT_R0_CODE, 0, KIDT_ACCESS_RING3, I686_INTERRUPT_GATE);
+    SetIdtGate(ProcessorBlock->IdtBase, 0x05, (PVOID)ArTrapEntry[0x05], KGDT_R0_CODE, 0, KIDT_ACCESS_RING0, I686_INTERRUPT_GATE);
+    SetIdtGate(ProcessorBlock->IdtBase, 0x06, (PVOID)ArTrapEntry[0x06], KGDT_R0_CODE, 0, KIDT_ACCESS_RING0, I686_INTERRUPT_GATE);
+    SetIdtGate(ProcessorBlock->IdtBase, 0x07, (PVOID)ArTrapEntry[0x07], KGDT_R0_CODE, 0, KIDT_ACCESS_RING0, I686_INTERRUPT_GATE);
+    SetIdtGate(ProcessorBlock->IdtBase, 0x08, (PVOID)ArTrapEntry[0x08], KGDT_R0_CODE, 0, KIDT_ACCESS_RING0, I686_TASK_GATE);
+    SetIdtGate(ProcessorBlock->IdtBase, 0x09, (PVOID)ArTrapEntry[0x09], KGDT_R0_CODE, 0, KIDT_ACCESS_RING0, I686_INTERRUPT_GATE);
+    SetIdtGate(ProcessorBlock->IdtBase, 0x0A, (PVOID)ArTrapEntry[0x0A], KGDT_R0_CODE, 0, KIDT_ACCESS_RING0, I686_INTERRUPT_GATE);
+    SetIdtGate(ProcessorBlock->IdtBase, 0x0B, (PVOID)ArTrapEntry[0x0B], KGDT_R0_CODE, 0, KIDT_ACCESS_RING0, I686_INTERRUPT_GATE);
+    SetIdtGate(ProcessorBlock->IdtBase, 0x0C, (PVOID)ArTrapEntry[0x0C], KGDT_R0_CODE, 0, KIDT_ACCESS_RING0, I686_INTERRUPT_GATE);
+    SetIdtGate(ProcessorBlock->IdtBase, 0x0D, (PVOID)ArTrapEntry[0x0D], KGDT_R0_CODE, 0, KIDT_ACCESS_RING0, I686_INTERRUPT_GATE);
+    SetIdtGate(ProcessorBlock->IdtBase, 0x0E, (PVOID)ArTrapEntry[0x0E], KGDT_R0_CODE, 0, KIDT_ACCESS_RING0, I686_INTERRUPT_GATE);
+    SetIdtGate(ProcessorBlock->IdtBase, 0x10, (PVOID)ArTrapEntry[0x10], KGDT_R0_CODE, 0, KIDT_ACCESS_RING0, I686_INTERRUPT_GATE);
+    SetIdtGate(ProcessorBlock->IdtBase, 0x11, (PVOID)ArTrapEntry[0x11], KGDT_R0_CODE, 0, KIDT_ACCESS_RING0, I686_INTERRUPT_GATE);
+    SetIdtGate(ProcessorBlock->IdtBase, 0x12, (PVOID)ArTrapEntry[0x12], KGDT_R0_CODE, 0, KIDT_ACCESS_RING0, I686_INTERRUPT_GATE);
+    SetIdtGate(ProcessorBlock->IdtBase, 0x13, (PVOID)ArTrapEntry[0x13], KGDT_R0_CODE, 0, KIDT_ACCESS_RING0, I686_INTERRUPT_GATE);
+    SetIdtGate(ProcessorBlock->IdtBase, 0x2A, (PVOID)ArTrapEntry[0x2A], KGDT_R0_CODE, 0, KIDT_ACCESS_RING3, I686_INTERRUPT_GATE);
+    SetIdtGate(ProcessorBlock->IdtBase, 0x2B, (PVOID)ArTrapEntry[0x2B], KGDT_R0_CODE, 0, KIDT_ACCESS_RING3, I686_INTERRUPT_GATE);
+    SetIdtGate(ProcessorBlock->IdtBase, 0x2C, (PVOID)ArTrapEntry[0x2C], KGDT_R0_CODE, 0, KIDT_ACCESS_RING3, I686_INTERRUPT_GATE);
+    SetIdtGate(ProcessorBlock->IdtBase, 0x2D, (PVOID)ArTrapEntry[0x2D], KGDT_R0_CODE, 0, KIDT_ACCESS_RING3, I686_INTERRUPT_GATE);
+    SetIdtGate(ProcessorBlock->IdtBase, 0x2E, (PVOID)ArTrapEntry[0x2E], KGDT_R0_CODE, 0, KIDT_ACCESS_RING3, I686_INTERRUPT_GATE);
 }
 
 /**
@@ -342,10 +344,10 @@ VOID
 AR::ProcSup::InitializeProcessorRegisters(VOID)
 {
     /* Clear EFLAGS register */
-    CpuFunc::WriteEflagsRegister(0);
+    AR::CpuFunc::WriteEflagsRegister(0);
 
     /* Enable write-protection */
-    CpuFunc::WriteControlRegister(0, CpuFunc::ReadControlRegister(0) | CR0_WP);
+    AR::CpuFunc::WriteControlRegister(0, AR::CpuFunc::ReadControlRegister(0) | CR0_WP);
 }
 
 /**
@@ -380,7 +382,8 @@ AR::ProcSup::InitializeProcessorStructures(IN PVOID ProcessorStructures,
                                            OUT PKTSS *Tss,
                                            OUT PKPROCESSOR_BLOCK *ProcessorBlock,
                                            OUT PVOID *KernelBootStack,
-                                           OUT PVOID *KernelFaultStack)
+                                           OUT PVOID *KernelFaultStack,
+                                           OUT PVOID *KernelNmiStack)
 {
     UINT_PTR Address;
 
@@ -391,8 +394,12 @@ AR::ProcSup::InitializeProcessorStructures(IN PVOID ProcessorStructures,
     *KernelBootStack = (PVOID)Address;
     Address += KERNEL_STACK_SIZE;
 
-    /* Assign a space for kernel fault stack, no advance needed as stack grows down */
+    /* Assign a space for kernel fault stack and advance */
     *KernelFaultStack = (PVOID)Address;
+    Address += KERNEL_STACK_SIZE;
+
+    /* Assign a space for kernel NMI stack, no advance needed as stack grows down */
+    *KernelNmiStack = (PVOID)Address;
 
     /* Assign a space for GDT and advance */
     *Gdt = (PKGDTENTRY)(PVOID)Address;
@@ -418,10 +425,12 @@ VOID
 AR::ProcSup::InitializeSegments(VOID)
 {
     /* Initialize segments */
-    CpuFunc::LoadSegment(SEGMENT_CS, KGDT_R0_CODE);
-    CpuFunc::LoadSegment(SEGMENT_DS, KGDT_R3_DATA | RPL_MASK);
-    CpuFunc::LoadSegment(SEGMENT_ES, KGDT_R3_DATA | RPL_MASK);
-    CpuFunc::LoadSegment(SEGMENT_FS, KGDT_R0_PB);
+    AR::CpuFunc::LoadSegment(SEGMENT_CS, KGDT_R0_CODE);
+    AR::CpuFunc::LoadSegment(SEGMENT_DS, KGDT_R3_DATA | RPL_MASK);
+    AR::CpuFunc::LoadSegment(SEGMENT_ES, KGDT_R3_DATA | RPL_MASK);
+    AR::CpuFunc::LoadSegment(SEGMENT_FS, KGDT_R0_PB);
+    AR::CpuFunc::LoadSegment(SEGMENT_GS, 0);
+    AR::CpuFunc::LoadSegment(SEGMENT_SS, KGDT_R0_DATA);
 }
 
 /**
@@ -438,8 +447,19 @@ XTAPI
 VOID
 AR::ProcSup::InitializeTss(IN PKPROCESSOR_BLOCK ProcessorBlock,
                            IN PVOID KernelBootStack,
-                           IN PVOID KernelFaultStack)
+                           IN PVOID KernelFaultStack,
+                           IN PVOID KernelNmiStack)
 {
+    PKGDTENTRY TssEntry;
+
+    /* Setup System TSS entry in Global Descriptor Table */
+    TssEntry = (PKGDTENTRY)(&(ProcessorBlock->GdtBase[KGDT_SYS_TSS / sizeof(KGDTENTRY)]));
+    TssEntry->LimitLow = sizeof(KTSS) - 1;
+    TssEntry->Bits.LimitHigh = 0;
+    TssEntry->Bits.Dpl = 0;
+    TssEntry->Bits.Present = 1;
+    TssEntry->Bits.Type = I686_TSS;
+
     /* Clear I/O map */
     RtlSetMemory(ProcessorBlock->TssBase->IoMaps[0].IoMap, 0xFF, IOPM_FULL_SIZE);
 
@@ -461,16 +481,16 @@ AR::ProcSup::InitializeTss(IN PKPROCESSOR_BLOCK ProcessorBlock,
 
     /* Set I/O map base and disable traps */
     ProcessorBlock->TssBase->IoMapBase = sizeof(KTSS);
-    ProcessorBlock->TssBase->Esp0 = (ULONG_PTR)KernelBootStack;
     ProcessorBlock->TssBase->Flags = 0;
 
-    /* Set LDT and SS */
-    ProcessorBlock->TssBase->LDT = KGDT_R0_LDT;
+    /* Set CR3, LDT and SS */
+    ProcessorBlock->TssBase->CR3 = AR::CpuFunc::ReadControlRegister(3);
+    ProcessorBlock->TssBase->LDT = 0;
     ProcessorBlock->TssBase->Ss0 = KGDT_R0_DATA;
 
     /* Initialize task gates for DoubleFault and NMI traps */
     SetDoubleFaultTssEntry(ProcessorBlock, KernelFaultStack);
-    SetNonMaskableInterruptTssEntry(ProcessorBlock, KernelFaultStack);
+    SetNonMaskableInterruptTssEntry(ProcessorBlock, KernelNmiStack);
 }
 
 /**
@@ -502,24 +522,24 @@ AR::ProcSup::SetDoubleFaultTssEntry(IN PKPROCESSOR_BLOCK ProcessorBlock,
     Tss = (PKTSS)DoubleFaultTss;
     Tss->IoMapBase = sizeof(KTSS);
     Tss->Flags = 0;
-    Tss->LDT = KGDT_R0_LDT;
-    Tss->CR3 = CpuFunc::ReadControlRegister(3);
+    Tss->LDT = 0;
+    Tss->CR3 = AR::CpuFunc::ReadControlRegister(3);
     Tss->Esp = (ULONG_PTR)KernelFaultStack;
     Tss->Esp0 = (ULONG_PTR)KernelFaultStack;
-    Tss->Eip = PtrToUlong(ArTrap0x08);
+    Tss->Eip = (ULONG)(ULONG_PTR)ArTrapEntry[0x08];
     Tss->Cs = KGDT_R0_CODE;
     Tss->Ds = KGDT_R3_DATA | RPL_MASK;
     Tss->Es = KGDT_R3_DATA | RPL_MASK;
     Tss->Fs = KGDT_R0_PB;
+    Tss->Ss = KGDT_R0_DATA;
     Tss->Ss0 = KGDT_R0_DATA;
-    CpuFunc::StoreSegment(SEGMENT_SS, (PVOID)&Tss->Ss);
 
     /* Setup DoubleFault TSS entry in Global Descriptor Table */
     TssEntry = (PKGDTENTRY)(&(ProcessorBlock->GdtBase[KGDT_DF_TSS / sizeof(KGDTENTRY)]));
     TssEntry->BaseLow = ((ULONG_PTR)Tss & 0xFFFF);
     TssEntry->Bytes.BaseMiddle = ((ULONG_PTR)Tss >> 16);
     TssEntry->Bytes.BaseHigh = ((ULONG_PTR)Tss >> 24);
-    TssEntry->LimitLow = sizeof(KTSS) - 1;
+    TssEntry->LimitLow = 0x68;
     TssEntry->Bits.LimitHigh = 0;
     TssEntry->Bits.Dpl = 0;
     TssEntry->Bits.Present = 1;
@@ -656,6 +676,9 @@ AR::ProcSup::SetGdtEntryBase(IN PKGDTENTRY Gdt,
  * @param Access
  *        Supplies the gate access rights.
  *
+ * @param Type
+ *        Supplies the gate type.
+ *
  * @return This routine does not return any value.
  *
  * @since XT 1.0
@@ -667,13 +690,21 @@ AR::ProcSup::SetIdtGate(IN PKIDTENTRY Idt,
                         IN PVOID Handler,
                         IN USHORT Selector,
                         IN USHORT Ist,
-                        IN USHORT Access)
+                        IN USHORT Dpl,
+                        IN USHORT Type)
 {
-    /* Setup the gate */
+    /* Set the handler's address */
     Idt[Vector].Offset = (USHORT)((ULONG)Handler & 0xFFFF);
     Idt[Vector].ExtendedOffset = (USHORT)((ULONG)Handler >> 16);
-    Idt[Vector].Access = 0x8000 | (Access << 8);
+
+    /* Set the code segment selector */
     Idt[Vector].Selector = Selector;
+
+    /* Initialize the gate's attributes and flags */
+    Idt[Vector].Access = 0;
+    Idt[Vector].Dpl = Dpl;
+    Idt[Vector].Present = 1;
+    Idt[Vector].Type = Type;
 }
 
 /**
@@ -689,7 +720,7 @@ AR::ProcSup::SetIdtGate(IN PKIDTENTRY Idt,
 XTAPI
 VOID
 AR::ProcSup::SetNonMaskableInterruptTssEntry(IN PKPROCESSOR_BLOCK ProcessorBlock,
-                                             IN PVOID KernelFaultStack)
+                                             IN PVOID KernelNmiStack)
 {
     PKGDTENTRY TaskGateEntry, TssEntry;
     PKTSS Tss;
@@ -705,23 +736,24 @@ AR::ProcSup::SetNonMaskableInterruptTssEntry(IN PKPROCESSOR_BLOCK ProcessorBlock
     Tss = (PKTSS)NonMaskableInterruptTss;
     Tss->IoMapBase = sizeof(KTSS);
     Tss->Flags = 0;
-    Tss->LDT = KGDT_R0_LDT;
-    Tss->CR3 = CpuFunc::ReadControlRegister(3);
-    Tss->Esp = (ULONG_PTR)KernelFaultStack;
-    Tss->Esp0 = (ULONG_PTR)KernelFaultStack;
-    Tss->Eip = PtrToUlong(ArTrap0x02);
+    Tss->LDT = 0;
+    Tss->CR3 = AR::CpuFunc::ReadControlRegister(3);
+    Tss->Esp = (ULONG_PTR)KernelNmiStack;
+    Tss->Esp0 = (ULONG_PTR)KernelNmiStack;
+    Tss->Eip = (ULONG)(ULONG_PTR)ArTrapEntry[0x02];
     Tss->Cs = KGDT_R0_CODE;
     Tss->Ds = KGDT_R3_DATA | RPL_MASK;
     Tss->Es = KGDT_R3_DATA | RPL_MASK;
     Tss->Fs = KGDT_R0_PB;
-    CpuFunc::StoreSegment(SEGMENT_SS, (PVOID)&Tss->Ss);
+    Tss->Ss = KGDT_R0_DATA;
+    Tss->Ss0 = KGDT_R0_DATA;
 
     /* Setup NMI TSS entry in Global Descriptor Table */
     TssEntry = (PKGDTENTRY)(&(ProcessorBlock->GdtBase[KGDT_NMI_TSS / sizeof(KGDTENTRY)]));
     TssEntry->BaseLow = ((ULONG_PTR)Tss & 0xFFFF);
     TssEntry->Bytes.BaseMiddle = ((ULONG_PTR)Tss >> 16);
     TssEntry->Bytes.BaseHigh = ((ULONG_PTR)Tss >> 24);
-    TssEntry->LimitLow = sizeof(KTSS) - 1;
+    TssEntry->LimitLow = 0x68;
     TssEntry->Bits.LimitHigh = 0;
     TssEntry->Bits.Dpl = 0;
     TssEntry->Bits.Present = 1;

xtoskrnl/ar/i686/traps.cc

@@ -9,6 +9,44 @@
 #include <xtos.hh>
 
 
+/**
+ * Dispatches the interrupt provided by common interrupt handler.
+ *
+ * @param TrapFrame
+ *        Supplies a kernel trap frame pushed by common interrupt handler on the stack.
+ *
+ * @return This routine does not return any value.
+ *
+ * @since XT 1.0
+ */
+XTCDECL
+VOID
+AR::Traps::DispatchInterrupt(IN PKTRAP_FRAME TrapFrame)
+{
+    PINTERRUPT_HANDLER Handler;
+
+    /* Read the handler pointer from the CPU's interrupt dispatch table */
+    Handler = (PINTERRUPT_HANDLER)AR::CpuFunc::ReadFSDualWord(FIELD_OFFSET(KPROCESSOR_BLOCK, InterruptDispatchTable) +
+                                                              (TrapFrame->Vector * sizeof(PINTERRUPT_HANDLER)));
+
+    /* Check if the interrupt has a handler registered */
+    if(Handler != NULLPTR)
+    {
+        /* Call the handler */
+        Handler(TrapFrame);
+    }
+    else if(UnhandledInterruptRoutine != NULLPTR)
+    {
+        /* Call the unhandled interrupt routine */
+        UnhandledInterruptRoutine(TrapFrame);
+    }
+    else
+    {
+        /* Dispatcher not initialized, print a debug message */
+        DebugPrint(L"ERROR: Caught unhandled interrupt: 0x%.2lX\n", TrapFrame->Vector);
+    }
+}
+
 /**
  * Dispatches the trap provided by common trap handler.
  *
@@ -195,7 +233,6 @@ VOID
 AR::Traps::HandleTrap02(IN PKTRAP_FRAME TrapFrame)
 {
     DebugPrint(L"Handled Non-Maskable-Interrupt (0x02)!\n");
-    KE::Crash::Panic(0x02);
 }
 
 /**
@@ -592,19 +629,19 @@ AR::Traps::HandleTrapFF(IN PKTRAP_FRAME TrapFrame)
 }
 
 /**
- * C-linkage wrapper for dispatching the trap provided by common trap handler.
+ * Sets the unhandled interrupt routine used for vectors that have no handler registered.
  *
- * @param TrapFrame
- *        Supplies a kernel trap frame pushed by common trap handler on the stack.
+ * @param Handler
+ *        Supplies the pointer to the interrupt handler routine.
  *
  * @return This routine does not return any value.
  *
  * @since XT 1.0
  */
-XTCLINK
 XTCDECL
 VOID
-ArDispatchTrap(IN PKTRAP_FRAME TrapFrame)
+AR::Traps::SetUnhandledInterruptRoutine(PINTERRUPT_HANDLER Handler)
 {
-    AR::Traps::DispatchTrap(TrapFrame);
+    /* Set the unhandled interrupt routine */
+    UnhandledInterruptRoutine = Handler;
 }

xtoskrnl/hl/acpi.cc

@@ -4,6 +4,7 @@
  * FILE:            xtoskrnl/hl/x86/acpi.cc
  * DESCRIPTION:     Advanced Configuration and Power Interface (ACPI) support
  * DEVELOPERS:      Rafal Kupiec <belliash@codingworkshop.eu.org>
+ *                  Aiken Harris <harraiken91@gmail.com>
  */
 
 #include <xtos.hh>
@@ -25,8 +26,21 @@ HL::Acpi::CacheAcpiTable(IN PACPI_DESCRIPTION_HEADER AcpiTable)
 {
     PACPI_CACHE_LIST AcpiCache;
 
-    /* Create new ACPI table cache entry */
-    AcpiCache = CONTAIN_RECORD(AcpiTable, ACPI_CACHE_LIST, Header);
+    /* Check if there are free slots in static early-boot cache array */
+    if(CacheCount >= ACPI_MAX_CACHED_TABLES)
+    {
+        /* Cache is full, the table is mapped but not cached */
+        return;
+    }
+
+    /* Get the next available static cache entry */
+    AcpiCache = &CacheEntries[CacheCount];
+    CacheCount++;
+
+    /* Store the pointer to the mapped ACPI table */
+    AcpiCache->Table = AcpiTable;
+
+    /* Insert entry into the global ACPI cache list */
     RTL::LinkedList::InsertTailList(&CacheList, &AcpiCache->ListEntry);
 }
 
@@ -196,14 +210,23 @@ HL::Acpi::InitializeAcpiSystemDescriptionTable(OUT PACPI_DESCRIPTION_HEADER *Acp
     AcpiResource = (PSYSTEM_RESOURCE_ACPI)ResourceHeader;
     RsdpAddress.QuadPart = (LONGLONG)AcpiResource->Header.PhysicalAddress;
 
-    /* Map RSDP and mark it as CD/WT to avoid delays in write-back cache */
+    /* Map RSDP using hardware memory pool */
     Status = MM::HardwarePool::MapHardwareMemory(RsdpAddress, 1, TRUE, (PVOID *)&RsdpStructure);
+    if(Status != STATUS_SUCCESS)
+    {
+        /* Failed to map RSDP, return error */
+        return Status;
+    }
+
+    /* Mark RSDP as CD/WT to avoid delays in write-back cache */
     MM::HardwarePool::MarkHardwareMemoryWriteThrough(RsdpStructure, 1);
 
     /* Validate RSDP signature */
-    if(Status != STATUS_SUCCESS || RsdpStructure->Signature != ACPI_RSDP_SIGNATURE)
+    if(RsdpStructure->Signature != ACPI_RSDP_SIGNATURE)
     {
-        /* Not mapped correctly or invalid RSDP signature, return error */
+        /* Invalid RSDP signature, unmap and return error */
+        MM::HardwarePool::UnmapHardwareMemory(RsdpStructure, 1, TRUE);
+        RsdpStructure = NULLPTR;
         return STATUS_INVALID_PARAMETER;
     }
 
@@ -219,34 +242,40 @@ HL::Acpi::InitializeAcpiSystemDescriptionTable(OUT PACPI_DESCRIPTION_HEADER *Acp
         RsdtAddress.QuadPart = (LONGLONG)RsdpStructure->RsdtAddress;
     }
 
-    /* Map RSDT/XSDT as CD/WT */
+    /* Map RSDT/XSDT using hardware memory pool */
     Status = MM::HardwarePool::MapHardwareMemory(RsdtAddress, 2, TRUE, (PVOID *)&Rsdt);
+    if(Status != STATUS_SUCCESS)
+    {
+        /* Failed to map RSDT/XSDT, return error */
+        return Status;
+    }
+
+    /* Mark RSDT/XSDT as CD/WT */
     MM::HardwarePool::MarkHardwareMemoryWriteThrough(Rsdt, 2);
 
     /* Validate RSDT/XSDT signature */
-    if((Status != STATUS_SUCCESS) ||
-       (Rsdt->Header.Signature != ACPI_RSDT_SIGNATURE &&
-        Rsdt->Header.Signature != ACPI_XSDT_SIGNATURE))
+    if(Rsdt->Header.Signature != ACPI_RSDT_SIGNATURE && Rsdt->Header.Signature != ACPI_XSDT_SIGNATURE)
     {
-        /* Not mapped correctly or invalid RSDT/XSDT signature, return error */
+        /* Not mapped correctly or invalid RSDT/XSDT signature, unmap and return error */
+        MM::HardwarePool::UnmapHardwareMemory(Rsdt, 2, TRUE);
         return STATUS_INVALID_PARAMETER;
     }
 
     /* Calculate the length of all available ACPI tables and remap it if needed */
-    RsdtPages = ((RsdtAddress.LowPart & (MM_PAGE_SIZE - 1)) + Rsdt->Header.Length + (MM_PAGE_SIZE - 1)) >> MM_PAGE_SHIFT;
+    RsdtPages = (((RsdtAddress.LowPart & (MM_PAGE_SIZE - 1)) + Rsdt->Header.Length + (MM_PAGE_SIZE - 1)) >> MM_PAGE_SHIFT);
     if(RsdtPages != 2)
     {
         /* RSDT/XSDT needs less or more than 2 pages, remap it */
         MM::HardwarePool::UnmapHardwareMemory(Rsdt, 2, TRUE);
         Status = MM::HardwarePool::MapHardwareMemory(RsdtAddress, RsdtPages, TRUE, (PVOID *)&Rsdt);
-        MM::HardwarePool::MarkHardwareMemoryWriteThrough(Rsdt, RsdtPages);
-
-        /* Make sure remapping was successful */
         if(Status != STATUS_SUCCESS)
         {
             /* Remapping failed, return error */
             return STATUS_INSUFFICIENT_RESOURCES;
         }
+
+        /* Mark remapped RSDT/XSDT as CD/WT */
+        MM::HardwarePool::MarkHardwareMemoryWriteThrough(Rsdt, RsdtPages);
     }
 
     /* Get ACPI table header and return success */
@@ -267,6 +296,7 @@ HL::Acpi::InitializeAcpiSystemInformation(VOID)
 {
     PACPI_MADT_LOCAL_X2APIC LocalX2Apic;
     PACPI_MADT_LOCAL_APIC LocalApic;
+    PACPI_SUBTABLE_HEADER SubTable;
     ULONG_PTR MadtTable;
     PACPI_MADT Madt;
     XTSTATUS Status;
@@ -293,11 +323,20 @@ HL::Acpi::InitializeAcpiSystemInformation(VOID)
     CpuCount = 0;
 
     /* Traverse all MADT tables to get system information */
-    while(MadtTable <= ((ULONG_PTR)Madt + Madt->Header.Length))
+    while(MadtTable < ((ULONG_PTR)Madt + Madt->Header.Length))
     {
+        /* Get current MADT subtable header */
+        SubTable = (PACPI_SUBTABLE_HEADER)MadtTable;
+
+        /* Prevent infinite loops if BIOS provides 0 length */
+        if(SubTable->Length == 0)
+        {
+            /* Broken ACPI table, abort traversal */
+            break;
+        }
+
         /* Check if this is a local APIC subtable */
-        if((((PACPI_SUBTABLE_HEADER)MadtTable)->Type == ACPI_MADT_TYPE_LOCAL_APIC) &&
-           (((PACPI_SUBTABLE_HEADER)MadtTable)->Length == sizeof(ACPI_MADT_LOCAL_APIC)))
+        if(SubTable->Type == ACPI_MADT_TYPE_LOCAL_APIC && SubTable->Length >= sizeof(ACPI_MADT_LOCAL_APIC))
         {
             /* Get local APIC subtable */
             LocalApic = (PACPI_MADT_LOCAL_APIC)MadtTable;
@@ -313,12 +352,8 @@ HL::Acpi::InitializeAcpiSystemInformation(VOID)
                 /* Increment number of CPUs */
                 CpuCount++;
             }
-
-            /* Go to the next MADT table */
-            MadtTable += ((PACPI_SUBTABLE_HEADER)MadtTable)->Length;
         }
-        else if((((PACPI_SUBTABLE_HEADER)MadtTable)->Type == ACPI_MADT_TYPE_LOCAL_X2APIC) &&
-                (((PACPI_SUBTABLE_HEADER)MadtTable)->Length == sizeof(ACPI_MADT_LOCAL_X2APIC)))
+        else if(SubTable->Type == ACPI_MADT_TYPE_LOCAL_X2APIC && SubTable->Length >= sizeof(ACPI_MADT_LOCAL_X2APIC))
         {
             /* Get local X2APIC subtable */
             LocalX2Apic = (PACPI_MADT_LOCAL_X2APIC)MadtTable;
@@ -334,15 +369,10 @@ HL::Acpi::InitializeAcpiSystemInformation(VOID)
                 /* Increment number of CPUs */
                 CpuCount++;
             }
+        }
 
-            /* Go to the next MADT table */
-            MadtTable += ((PACPI_SUBTABLE_HEADER)MadtTable)->Length;
-        }
-        else
-        {
-            /* Any other MADT table, try to go to the next one byte-by-byte */
-            MadtTable += 1;
-        }
+        /* Safely advance pointer using proper subtable length */
+        MadtTable += SubTable->Length;
     }
 
     /* Store number of CPUs */
@@ -522,10 +552,10 @@ HL::Acpi::QueryAcpiCache(IN ULONG Signature,
         AcpiCache = CONTAIN_RECORD(ListEntry, ACPI_CACHE_LIST, ListEntry);
 
         /* Check if ACPI table signature matches */
-        if(AcpiCache->Header.Signature == Signature)
+        if(AcpiCache->Table->Signature == Signature)
         {
             /* ACPI table found in cache, return it */
-            TableHeader = &AcpiCache->Header;
+            TableHeader = AcpiCache->Table;
             break;
         }
 
@@ -596,18 +626,31 @@ HL::Acpi::QueryAcpiTables(IN ULONG Signature,
         /* Check if DSDT or FACS table requested */
         if(Signature == ACPI_DSDT_SIGNATURE)
         {
-            /* Get DSDT address */
-            TableAddress.LowPart = Fadt->Dsdt;
+            /* Prefer 64-bit address on ACPI 2.0+ */
+            if(Fadt->Header.Revision >= 2 && Fadt->XDsdt.QuadPart != 0)
+            {
+                TableAddress.QuadPart = Fadt->XDsdt.QuadPart;
+            }
+            else
+            {
+                TableAddress.LowPart = Fadt->Dsdt;
+                TableAddress.HighPart = 0;
+            }
         }
         else
         {
-            /* Get FACS address */
-            TableAddress.LowPart = Fadt->FirmwareCtrl;
+            /* Prefer 64-bit address on ACPI 2.0+ */
+            if(Fadt->Header.Revision >= 2 && Fadt->XFirmwareCtrl.QuadPart != 0)
+            {
+                TableAddress.QuadPart = Fadt->XFirmwareCtrl.QuadPart;
+            }
+            else
+            {
+                TableAddress.LowPart = Fadt->FirmwareCtrl;
+                TableAddress.HighPart = 0;
+            }
         }
 
-        /* Fill in high part of ACPI table address */
-        TableAddress.HighPart = 0;
-
         /* Map table using hardware memory pool */
         Status = MM::HardwarePool::MapHardwareMemory(TableAddress, 2, TRUE, (PVOID*)&TableHeader);
         if(Status != STATUS_SUCCESS)
@@ -618,11 +661,12 @@ HL::Acpi::QueryAcpiTables(IN ULONG Signature,
     }
     else
     {
-        /* Query cache for XSDP table */
+        /* Query cache for XSDT table */
         Status = QueryAcpiCache(ACPI_XSDT_SIGNATURE, (PACPI_DESCRIPTION_HEADER*)&Xsdt);
         if(Status != STATUS_SUCCESS)
         {
-            /* XSDP not found, query cache for RSDP table */
+            /* XSDT not found, query cache for RSDT table */
+            Xsdt = NULLPTR;
             Status = QueryAcpiCache(ACPI_RSDT_SIGNATURE, (PACPI_DESCRIPTION_HEADER*)&Rsdt);
         }
 
@@ -633,22 +677,22 @@ HL::Acpi::QueryAcpiTables(IN ULONG Signature,
             return Status;
         }
 
-        /* Get table count depending on root table type */
+        /* Get table count depending on root table type securely */
         if(Xsdt != NULLPTR)
         {
-            /* Get table count from XSDT */
+            if(Xsdt->Header.Length < sizeof(ACPI_DESCRIPTION_HEADER)) return STATUS_INVALID_PARAMETER;
             TableCount = (Xsdt->Header.Length - sizeof(ACPI_DESCRIPTION_HEADER)) / 8;
         }
         else
         {
-            /* Get table count from RSDT */
+            if(Rsdt->Header.Length < sizeof(ACPI_DESCRIPTION_HEADER)) return STATUS_INVALID_PARAMETER;
             TableCount = (Rsdt->Header.Length - sizeof(ACPI_DESCRIPTION_HEADER)) / 4;
         }
 
         /* Iterate over all ACPI tables */
         for(TableIndex = 0; TableIndex < TableCount; TableIndex++)
         {
-            /* Check if XSDP or RSDT is used */
+            /* Check if XSDT or RSDT is used */
             if(Xsdt != NULLPTR)
             {
                 /* Get table header physical address from XSDT */
@@ -661,13 +705,6 @@ HL::Acpi::QueryAcpiTables(IN ULONG Signature,
                 TableAddress.HighPart = 0;
             }
 
-            /* Check whether some table is already mapped */
-            if(TableHeader != NULLPTR)
-            {
-                /* Unmap previous table */
-                MM::HardwarePool::UnmapHardwareMemory(TableHeader, 2, TRUE);
-            }
-
             /* Map table using hardware memory pool */
             Status = MM::HardwarePool::MapHardwareMemory(TableAddress, 2, TRUE, (PVOID*)&TableHeader);
             if(Status != STATUS_SUCCESS)
@@ -682,25 +719,31 @@ HL::Acpi::QueryAcpiTables(IN ULONG Signature,
                 /* Found requested ACPI table */
                 break;
             }
+
+            /* Unmap non-matching table and try next one */
+            MM::HardwarePool::UnmapHardwareMemory(TableHeader, 2, TRUE);
+            TableHeader = NULLPTR;
         }
     }
 
-    /* Make sure table was found */
-    if(TableHeader->Signature != Signature)
+    /* Ensure the table was actually found and mapped */
+    if(TableHeader == NULLPTR)
     {
-        /* ACPI table not found, check if cleanup is needed */
-        if(TableHeader != NULLPTR)
-        {
-            /* Unmap non-matching ACPI table */
-            MM::HardwarePool::UnmapHardwareMemory(TableHeader, 2, TRUE);
-        }
-
-        /* Return error */
+        /* ACPI table not found, return error */
         return STATUS_NOT_FOUND;
     }
 
-    /* Don't validate FADT on old, broken firmwares with ACPI 2.0 or older */
-    if(TableHeader->Signature != ACPI_FADT_SIGNATURE || TableHeader->Revision > 2)
+    /* Check if we broke out of the loop with the wrong table (safety check) */
+    if(TableHeader->Signature != Signature)
+    {
+        /* Unmap non-matching ACPI table and return error */
+        MM::HardwarePool::UnmapHardwareMemory(TableHeader, 2, TRUE);
+        return STATUS_NOT_FOUND;
+    }
+
+    /* Don't validate FACS and FADT on old, broken firmwares with ACPI 2.0 or older */
+    if((TableHeader->Signature != ACPI_FADT_SIGNATURE || TableHeader->Revision > 2) &&
+       (TableHeader->Signature != ACPI_FACS_SIGNATURE))
     {
         /* Validate table checksum */
         if(!ValidateAcpiTable(TableHeader, TableHeader->Length))
@@ -712,7 +755,7 @@ HL::Acpi::QueryAcpiTables(IN ULONG Signature,
     }
 
     /* Calculate the length of ACPI table and remap it if needed */
-    TablePages = (((ULONG_PTR)TableHeader & (MM_PAGE_SIZE - 1)) + TableHeader->Length + (MM_PAGE_SIZE - 1)) >> MM_PAGE_SHIFT;
+    TablePages = (((TableAddress.LowPart & (MM_PAGE_SIZE - 1)) + TableHeader->Length + (MM_PAGE_SIZE - 1)) >> MM_PAGE_SHIFT);
     if(TablePages != 2)
     {
         /* ACPI table needs less or more than 2 pages, remap it */

xtoskrnl/hl/amd64/irq.cc

@@ -0,0 +1,162 @@
+/**
+ * PROJECT:         ExectOS
+ * COPYRIGHT:       See COPYING.md in the top level directory
+ * FILE:            xtoskrnl/hl/amd64/irq.cc
+ * DESCRIPTION:     Interrupts support for AMD64 architecture
+ * DEVELOPERS:      Rafal Kupiec <belliash@codingworkshop.eu.org>
+ *                  Aiken Harris <harraiken91@gmail.com>
+ */
+
+#include <xtos.hh>
+
+
+/**
+ * Handles profiling interrupt.
+ *
+ * @param TrapFrame
+ *        Supplies a kernel trap frame pushed by common interrupt handler.
+ *
+ * @return This routine does not return any value.
+ *
+ * @since XT 1.0
+ */
+XTCDECL
+VOID
+HL::Irq::HandleProfileInterrupt(IN PKTRAP_FRAME TrapFrame)
+{
+    /* Send EOI*/
+    HL::Pic::SendEoi();
+}
+
+/**
+ * Handles unexpected or unmapped system interrupts.
+ *
+ * @param TrapFrame
+ *        Supplies a kernel trap frame pushed by common interrupt handler.
+ *
+ * @return This routine does not return any value.
+ *
+ * @since XT 1.0
+ */
+XTCDECL
+VOID
+HL::Irq::HandleUnexpectedInterrupt(IN PKTRAP_FRAME TrapFrame)
+{
+    UNIMPLEMENTED;
+
+    /* Disable interrupts */
+    AR::CpuFunc::ClearInterruptFlag();
+
+    /* Print debug message and raise kernel panic */
+    DebugPrint(L"ERROR: Caught unexpected interrupt (0x%.2llX)!\n", TrapFrame->Vector);
+    KE::Crash::Panic(0x47, TrapFrame->Vector, 0, 0, 0);
+}
+
+/**
+ * Returns the registered interrupt handler for the specified IDT vector.
+ *
+ * @param Vector
+ *        Supplies the interrupt vector number.
+ *
+ * @return This routine returns the pointer to the IDT interrupt handler routine.
+ *
+ * @since XT 1.0
+ */
+XTAPI
+PVOID
+HL::Irq::QueryInterruptHandler(IN ULONG Vector)
+{
+    PKPROCESSOR_BLOCK ProcessorBlock;
+    PKIDTENTRY IdtEntry;
+
+    /* Get current processor block and IDT entry */
+    ProcessorBlock = KE::Processor::GetCurrentProcessorBlock();
+    IdtEntry = &ProcessorBlock->IdtBase[Vector];
+
+    /* Return address of the interrupt handler */
+    return (PVOID)((ULONGLONG)IdtEntry->OffsetHigh << 32 |
+                   (ULONGLONG)IdtEntry->OffsetMiddle << 16 |
+                   (ULONGLONG)IdtEntry->OffsetLow);
+}
+
+/**
+ * Returns the registered interrupt handler for the specified vector.
+ *
+ * @param Vector
+ *        Supplies the interrupt vector number.
+ *
+ * @return This routine returns the pointer to the interrupt handler routine.
+ *
+ * @since XT 1.0
+ */
+XTAPI
+PVOID
+HL::Irq::QuerySystemInterruptHandler(IN ULONG Vector)
+{
+    PKPROCESSOR_BLOCK ProcessorBlock;
+
+    /* Get current processor block */
+    ProcessorBlock = KE::Processor::GetCurrentProcessorBlock();
+
+    return (PVOID)ProcessorBlock->InterruptDispatchTable[Vector];
+}
+
+/**
+ * Registers new interrupt handler for the existing IDT entry.
+ *
+ * @param HalVector
+ *        Supplies the interrupt vector number.
+ *
+ * @param Handler
+ *        Supplies the pointer to the interrupt handler routine.
+ *
+ * @return This routine does not return any value.
+ *
+ * @since XT 1.0
+ */
+XTAPI
+VOID
+HL::Irq::RegisterInterruptHandler(IN ULONG Vector,
+                                  IN PVOID Handler)
+{
+    PKPROCESSOR_BLOCK ProcessorBlock;
+
+    /* Get current processor block */
+    ProcessorBlock = KE::Processor::GetCurrentProcessorBlock();
+
+    /* Update interrupt handler */
+    AR::ProcSup::SetIdtGate(ProcessorBlock->IdtBase,
+                            Vector,
+                            Handler,
+                            KGDT_R0_CODE,
+                            0,
+                            KIDT_ACCESS_RING0,
+                            AMD64_INTERRUPT_GATE);
+}
+
+/**
+ * Registers the interrupt handler for the specified vector.
+ *
+ * @param HalVector
+ *        Supplies the interrupt vector number.
+ *
+ * @param Handler
+ *        Supplies the pointer to the interrupt handler routine.
+ *
+ * @return This routine does not return any value.
+ *
+ * @since XT 1.0
+ */
+XTAPI
+VOID
+HL::Irq::RegisterSystemInterruptHandler(IN ULONG Vector,
+                                        IN PINTERRUPT_HANDLER Handler)
+{
+    PKPROCESSOR_BLOCK ProcessorBlock;
+
+    /* Get current processor block */
+    ProcessorBlock = KE::Processor::GetCurrentProcessorBlock();
+
+    /* Update interrupt handler in the processor's interrupt dispatch table */
+    ProcessorBlock->InterruptDispatchTable[Vector] = Handler;
+}

xtoskrnl/hl/amd64/timer.cc

@@ -0,0 +1,13 @@
+/**
+ * PROJECT:         ExectOS
+ * COPYRIGHT:       See COPYING.md in the top level directory
+ * FILE:            xtoskrnl/hl/amd64/timer.cc
+ * DESCRIPTION:     APIC Timer for AMD64 support
+ * DEVELOPERS:      Aiken Harris <harraiken91@gmail.com>
+ */
+
+#include <xtos.hh>
+
+
+/* Include common Timer interface */
+#include ARCH_COMMON(timer.cc)

xtoskrnl/hl/data.cc

@@ -9,6 +9,12 @@
 #include <xtos.hh>
 
 
+/* ACPI tables cache count */
+ULONG HL::Acpi::CacheCount = 0;
+
+/* ACPI tables cache entries */
+ACPI_CACHE_LIST HL::Acpi::CacheEntries[ACPI_MAX_CACHED_TABLES];
+
 /* ACPI tables cache list */
 LIST_ENTRY HL::Acpi::CacheList;
 
@@ -32,3 +38,27 @@ HL_SCROLL_REGION_DATA HL::FrameBuffer::ScrollRegionData;
 
 /* APIC mode */
 APIC_MODE HL::Pic::ApicMode;
+
+/* Number of I/O APIC controllers */
+ULONG HL::Pic::ControllerCount;
+
+/* I/O APIC controllers information */
+IOAPIC_DATA HL::Pic::Controllers[IOAPIC_MAX_CONTROLLERS];
+
+/* Number of I/O APIC overrides */
+ULONG HL::Pic::IrqOverrideCount;
+
+/* I/O APIC overrides information */
+ACPI_MADT_INTERRUPT_OVERRIDE HL::Pic::IrqOverrides[IOAPIC_MAX_OVERRIDES];
+
+/* Mapped interrupt vectors */
+UCHAR HL::Pic::MappedVectors[256];
+
+/* Kernel profiling interval */
+ULONG HL::Timer::ProfilingInterval;
+
+/* Timer capabilities */
+TIMER_CAPABILITIES HL::Timer::TimerCapabilities = {0};
+
+/* APIC timer frequency */
+ULONG HL::Timer::TimerFrequency;

xtoskrnl/hl/i686/irq.cc

@@ -0,0 +1,160 @@
+/**
+ * PROJECT:         ExectOS
+ * COPYRIGHT:       See COPYING.md in the top level directory
+ * FILE:            xtoskrnl/hl/i686/irq.cc
+ * DESCRIPTION:     Interrupts support for i686 architecture
+ * DEVELOPERS:      Rafal Kupiec <belliash@codingworkshop.eu.org>
+ *                  Aiken Harris <harraiken91@gmail.com>
+ */
+
+#include <xtos.hh>
+
+
+/**
+ * Handles profiling interrupt.
+ *
+ * @param TrapFrame
+ *        Supplies a kernel trap frame pushed by common interrupt handler.
+ *
+ * @return This routine does not return any value.
+ *
+ * @since XT 1.0
+ */
+XTCDECL
+VOID
+HL::Irq::HandleProfileInterrupt(IN PKTRAP_FRAME TrapFrame)
+{
+    /* Send EOI*/
+    HL::Pic::SendEoi();
+}
+
+/**
+ * Handles unexpected or unmapped system interrupts.
+ *
+ * @param TrapFrame
+ *        Supplies a kernel trap frame pushed by common interrupt handler.
+ *
+ * @return This routine does not return any value.
+ *
+ * @since XT 1.0
+ */
+XTCDECL
+VOID
+HL::Irq::HandleUnexpectedInterrupt(IN PKTRAP_FRAME TrapFrame)
+{
+    UNIMPLEMENTED;
+
+    /* Disable interrupts */
+    AR::CpuFunc::ClearInterruptFlag();
+
+    /* Print debug message and raise kernel panic */
+    DebugPrint(L"ERROR: Caught unexpected interrupt (0x%.2lX)!\n", TrapFrame->Vector);
+    KE::Crash::Panic(0x47, TrapFrame->Vector, 0, 0, 0);
+}
+
+/**
+ * Returns the registered interrupt handler for the specified IDT vector.
+ *
+ * @param Vector
+ *        Supplies the interrupt vector number.
+ *
+ * @return This routine returns the pointer to the IDT interrupt handler routine.
+ *
+ * @since XT 1.0
+ */
+XTAPI
+PVOID
+HL::Irq::QueryInterruptHandler(IN ULONG Vector)
+{
+    PKPROCESSOR_BLOCK ProcessorBlock;
+    PKIDTENTRY IdtEntry;
+
+    /* Get current processor block and IDT entry */
+    ProcessorBlock = KE::Processor::GetCurrentProcessorBlock();
+    IdtEntry = &ProcessorBlock->IdtBase[Vector];
+
+    /* Return address of the interrupt handler */
+    return (PVOID)(((IdtEntry->ExtendedOffset << 16) & 0xFFFF0000) | (IdtEntry->Offset & 0xFFFF));
+}
+
+/**
+ * Returns the registered interrupt handler for the specified vector.
+ *
+ * @param Vector
+ *        Supplies the interrupt vector number.
+ *
+ * @return This routine returns the pointer to the interrupt handler routine.
+ *
+ * @since XT 1.0
+ */
+XTAPI
+PVOID
+HL::Irq::QuerySystemInterruptHandler(IN ULONG Vector)
+{
+    PKPROCESSOR_BLOCK ProcessorBlock;
+
+    /* Get current processor block */
+    ProcessorBlock = KE::Processor::GetCurrentProcessorBlock();
+
+    return (PVOID)ProcessorBlock->InterruptDispatchTable[Vector];
+}
+
+/**
+ * Registers new interrupt handler for the existing IDT entry.
+ *
+ * @param HalVector
+ *        Supplies the interrupt vector number.
+ *
+ * @param Handler
+ *        Supplies the pointer to the interrupt handler routine.
+ *
+ * @return This routine does not return any value.
+ *
+ * @since XT 1.0
+ */
+XTAPI
+VOID
+HL::Irq::RegisterInterruptHandler(IN ULONG Vector,
+                                  IN PVOID Handler)
+{
+    PKPROCESSOR_BLOCK ProcessorBlock;
+
+    /* Get current processor block */
+    ProcessorBlock = KE::Processor::GetCurrentProcessorBlock();
+
+    /* Update interrupt handler */
+    AR::ProcSup::SetIdtGate(ProcessorBlock->IdtBase,
+                            Vector,
+                            Handler,
+                            KGDT_R0_CODE,
+                            0,
+                            KIDT_ACCESS_RING0,
+                            I686_INTERRUPT_GATE);
+}
+
+/**
+ * Registers the interrupt handler for the specified vector.
+ *
+ * @param HalVector
+ *        Supplies the interrupt vector number.
+ *
+ * @param Handler
+ *        Supplies the pointer to the interrupt handler routine.
+ *
+ * @return This routine does not return any value.
+ *
+ * @since XT 1.0
+ */
+XTAPI
+VOID
+HL::Irq::RegisterSystemInterruptHandler(IN ULONG Vector,
+                                        IN PINTERRUPT_HANDLER Handler)
+{
+    PKPROCESSOR_BLOCK ProcessorBlock;
+
+    /* Get current processor block */
+    ProcessorBlock = KE::Processor::GetCurrentProcessorBlock();
+
+    /* Update interrupt handler in the processor's interrupt dispatch table */
+    ProcessorBlock->InterruptDispatchTable[Vector] = Handler;
+}

xtoskrnl/hl/i686/timer.cc

@@ -0,0 +1,13 @@
+/**
+ * PROJECT:         ExectOS
+ * COPYRIGHT:       See COPYING.md in the top level directory
+ * FILE:            xtoskrnl/hl/i686/timer.cc
+ * DESCRIPTION:     APIC Timer for i686 support
+ * DEVELOPERS:      Aiken Harris <harraiken91@gmail.com>
+ */
+
+#include <xtos.hh>
+
+
+/* Include common Timer interface */
+#include ARCH_COMMON(timer.cc)

xtoskrnl/hl/init.cc

@@ -23,14 +23,14 @@ HL::Init::InitializeSystem(VOID)
     XTSTATUS Status;
 
     /* Initialize ACPI */
-    Status = Acpi::InitializeAcpi();
+    Status = HL::Acpi::InitializeAcpi();
     if(Status != STATUS_SUCCESS)
     {
         return Status;
     }
 
     /* Get system information from ACPI */
-    Status = Acpi::InitializeAcpiSystemInformation();
+    Status = HL::Acpi::InitializeAcpiSystemInformation();
     if(Status != STATUS_SUCCESS)
     {
         return Status;

xtoskrnl/hl/x86/cpu.cc

@@ -40,8 +40,11 @@ HL::Cpu::InitializeProcessor(VOID)
     ActiveProcessors |= Affinity;
 
     /* Initialize APIC for this processor */
-    Pic::InitializePic();
+    HL::Pic::InitializePic();
 
     /* Set the APIC running level */
     HL::RunLevel::SetRunLevel(KE::Processor::GetCurrentProcessorBlock()->RunLevel);
+
+    /* Initialize timer */
+    HL::Timer::InitializeTimer();
 }

xtoskrnl/hl/x86/pic.cc

@@ -9,6 +9,97 @@
 #include <xtos.hh>
 
 
+/**
+ * Allocates, maps and commits a requested system interrupt level internally.
+ *
+ * @param RunLevel
+ *        Supplies the actual system run level to allocate.
+ *
+ * @param Vector
+ *        Supplies the interrupt handler vector assigned to process requests originating on the line.
+ *
+ * @return This routine returns the configured target vector.
+ *
+ * @since XT 1.0
+ */
+XTAPI
+VOID
+HL::Pic::AllocateSystemInterrupt(IN UCHAR Irq,
+                                 IN UCHAR RunLevel,
+                                 IN UCHAR Vector)
+{
+    IOAPIC_REDIRECTION_REGISTER Register;
+    PIOAPIC_DATA Controller;
+    ULONG EntryNumber, Gsi;
+    XTSTATUS Status;
+    USHORT Flags;
+
+    /* Determine the GSI and flags for the requested IRQ */
+    ResolveInterruptOverride(Irq, &Gsi, &Flags);
+
+    /* Find the APIC controller for the GSI */
+    Status = GetIoApicController(Gsi, &Controller, &EntryNumber);
+    if(Status != STATUS_SUCCESS)
+    {
+        /* GSI maps to an invalid controller, return */
+        DebugPrint(L"ERROR: Hardware IRQ / GSI maps to an invalid controller!\n");
+        return;
+    }
+
+    /* Model a logical connection */
+    Register.DeliveryMode = APIC_DM_LOWPRIO;
+    Register.DeliveryStatus = 0;
+    Register.Destination = HL::Pic::ReadApicRegister(APIC_ID) >> 24;
+    Register.DestinationMode = APIC_DM_Physical;
+    Register.Mask = 1;
+    Register.PinPolarity = ((Flags & 0x03) == 0x03) ? 1 : 0;
+    Register.RemoteIRR = 0;
+    Register.Reserved = 0;
+    Register.TriggerMode = (((Flags >> 2) & 0x03) == 0x03) ? APIC_TGM_LEVEL : APIC_TGM_EDGE;
+    Register.Vector = Vector;
+
+    /* Flash logical rules back into the hardware configuration index */
+    WriteRedirectionEntry(Controller, EntryNumber, Register);
+
+    /* Persist the allocated slot so standard routing algorithms don't overlap it */
+    MappedVectors[Vector] = RunLevel;
+}
+
+/**
+ * Checks whether the APIC is supported by the processor.
+ *
+ * @return This routine returns TRUE if APIC is supported, or FALSE otherwise.
+ *
+ * @since XT 1.0
+ */
+XTAPI
+BOOLEAN
+HL::Pic::CheckApicSupport(VOID)
+{
+    CPUID_REGISTERS CpuRegisters;
+
+    /* Prepare CPUID registers */
+    CpuRegisters.Leaf = CPUID_GET_STANDARD1_FEATURES;
+    CpuRegisters.SubLeaf = 0;
+    CpuRegisters.Eax = 0;
+    CpuRegisters.Ebx = 0;
+    CpuRegisters.Ecx = 0;
+    CpuRegisters.Edx = 0;
+
+    /* Get CPUID */
+    AR::CpuFunc::CpuId(&CpuRegisters);
+
+    /* Check APIC status from the CPUID results */
+    if(!(CpuRegisters.Edx & CPUID_FEATURES_EDX_APIC))
+    {
+        /* APIC is not supported */
+        return FALSE;
+    }
+
+    /* APIC is supported */
+    return TRUE;
+}
+
 /**
  * Checks whether the x2APIC extension is supported by the processor.
  *
@@ -62,6 +153,105 @@ HL::Pic::ClearApicErrors(VOID)
     WriteApicRegister(APIC_ESR, 0);
 }
 
+/**
+ * Searches the ACPI MADT tables for the I/O APIC controllers.
+ *
+ * @return This routine returns the status code.
+ *
+ * @since XT 1.0
+ */
+XTAPI
+XTSTATUS
+HL::Pic::DetectIoApicControllers(VOID)
+{
+    PACPI_MADT_INTERRUPT_OVERRIDE OverrideDescriptor;
+    PACPI_MADT_IOAPIC IoApicDescriptor;
+    PACPI_SUBTABLE_HEADER SubTable;
+    ULONG_PTR MadtTable;
+    PACPI_MADT Madt;
+    XTSTATUS Status;
+
+    /* Initialize number of I/O APIC Controllers */
+    ControllerCount = 0;
+
+    /* Get Multiple APIC Description Table (MADT) */
+    Status = HL::Acpi::GetAcpiTable(ACPI_MADT_SIGNATURE, (PACPI_DESCRIPTION_HEADER*)&Madt);
+    if(Status == STATUS_SUCCESS && Madt != NULLPTR)
+    {
+        /* Set APIC table traverse pointer */
+        MadtTable = (ULONG_PTR)Madt->ApicTables;
+
+        /* Traverse all MADT tables to discover IOAPIC configurations */
+        while(MadtTable < ((ULONG_PTR)Madt + Madt->Header.Length))
+        {
+            /* Extract active header element */
+            SubTable = (PACPI_SUBTABLE_HEADER)MadtTable;
+
+            /* Prevent infinite traversal loops on corrupted firmware definitions */
+            if(SubTable->Length == 0)
+            {
+                /* Invalid MADT table, break loop */
+                break;
+            }
+
+            /* Test specifically for I/O APIC component identity */
+            if(SubTable->Type == ACPI_MADT_TYPE_IOAPIC &&
+               SubTable->Length >= sizeof(ACPI_MADT_IOAPIC))
+            {
+                /* Extract I/O APIC descriptor */
+                IoApicDescriptor = (PACPI_MADT_IOAPIC)MadtTable;
+
+                /* Set information about this I/O APIC Controller */
+                Controllers[ControllerCount].GsiBase = IoApicDescriptor->GlobalIrqBase;
+                Controllers[ControllerCount].Identifier = IoApicDescriptor->IoApicId;
+                Controllers[ControllerCount].PhysicalAddress.QuadPart = IoApicDescriptor->IoApicAddress;
+
+                /* Increment I/O APIC controller index */
+                ControllerCount++;
+            }
+            else if(SubTable->Type == ACPI_MADT_TYPE_INT_OVERRIDE &&
+                    SubTable->Length >= sizeof(ACPI_MADT_INTERRUPT_OVERRIDE))
+            {
+                /* Check if maximum number of interrupt overrides has not been reached */
+                if(IrqOverrideCount < IOAPIC_MAX_OVERRIDES)
+                {
+                    /* Extract interrupt override descriptor */
+                    OverrideDescriptor = (PACPI_MADT_INTERRUPT_OVERRIDE)MadtTable;
+
+                    /* Save information about this interrupt override */
+                    IrqOverrides[IrqOverrideCount].Bus = OverrideDescriptor->Bus;
+                    IrqOverrides[IrqOverrideCount].Flags = OverrideDescriptor->Flags;
+                    IrqOverrides[IrqOverrideCount].GlobalSystemInterrupt = OverrideDescriptor->GlobalSystemInterrupt;
+                    IrqOverrides[IrqOverrideCount].SourceIrq = OverrideDescriptor->SourceIrq;
+
+                    /* Increment interrupt override index */
+                    IrqOverrideCount++;
+                }
+            }
+
+            /* Ensure, maximum number of I/O APIC controllers has not been reached */
+            if(ControllerCount >= IOAPIC_MAX_CONTROLLERS)
+            {
+                /* No more I/O APIC controllers supported, break loop */
+                break;
+            }
+
+            /* Go to the next subtable */
+            MadtTable += SubTable->Length;
+        }
+    }
+
+    /* Check if any I/O APIC controllers were found */
+    if(ControllerCount == 0)
+    {
+        /* No I/O APIC controllers found, return failure */
+        return STATUS_NOT_FOUND;
+    }
+
+    /* Return success */
+    return STATUS_SUCCESS;
+}
+
 /**
  * Gets the local APIC ID of the current processor.
  *
@@ -83,29 +273,45 @@ HL::Pic::GetCpuApicId(VOID)
 }
 
 /**
- * Allows an APIC spurious interrupts to end up.
+ * Gets the I/O APIC controller information for the specified GSI.
  *
- * @return This routine does not return any value.
+ * @param Gsi
+ *        Supplies the GSI to get the I/O APIC controller information for.
+ *
+ * @param Controller
+ *        Supplies a pointer to the memory area where the I/O APIC controller information will be stored.
+ *
+ * @param EntryNumber
+ *        Supplies a pointer to the memory area where the entry number will be stored.
+ *
+ * @return This routine returns the status code.
  *
  * @since XT 1.0
  */
-XTCDECL
-VOID
-HL::Pic::HandleApicSpuriousService(VOID)
+XTAPI
+XTSTATUS
+HL::Pic::GetIoApicController(IN ULONG Gsi,
+                             OUT PIOAPIC_DATA *Controller,
+                             OUT PULONG EntryNumber)
 {
-}
+    ULONG ControllerIndex;
 
-/**
- * Allows a PIC spurious interrupts to end up.
- *
- * @return This routine does not return any value.
- *
- * @since XT 1.0
- */
-XTCDECL
-VOID
-HL::Pic::HandlePicSpuriousService(VOID)
-{
+    /* Iterate over all available I/O APIC controllers */
+    for(ControllerIndex = 0; ControllerIndex < ControllerCount; ControllerIndex++)
+    {
+        /* Check if the GSI belongs to this I/O APIC controller */
+        if(Gsi >= Controllers[ControllerIndex].GsiBase &&
+           Gsi < (Controllers[ControllerIndex].GsiBase + Controllers[ControllerIndex].LineCount))
+        {
+            /* Return I/O APIC controller information */
+            *Controller = &Controllers[ControllerIndex];
+            *EntryNumber = (ULONG)(Gsi - Controllers[ControllerIndex].GsiBase);
+            return STATUS_SUCCESS;
+        }
+    }
+
+    /* GSI does not belong to any I/O APIC controller, return failure */
+    return STATUS_NOT_FOUND;
 }
 
 /**
@@ -124,6 +330,14 @@ HL::Pic::InitializeApic(VOID)
     APIC_LVT_REGISTER LvtRegister;
     ULONG CpuNumber;
 
+    /* Check APIC support */
+    if(!CheckApicSupport())
+    {
+        /* APIC is not supported, raise kernel panic */
+        DebugPrint(L"ERROR: Local APIC not present.\n");
+        KE::Crash::Panic(0x5D, CPUID_GET_STANDARD1_FEATURES, 0x0, 0x0, CPUID_FEATURES_EDX_APIC);
+    }
+
     /* Determine APIC mode (xAPIC compatibility or x2APIC) */
     if(CheckX2ApicSupport())
     {
@@ -206,8 +420,8 @@ HL::Pic::InitializeApic(VOID)
     WriteApicRegister(APIC_LINT1, LvtRegister.Long);
 
     /* Register interrupt handlers */
-    KE::Irq::SetInterruptHandler(APIC_VECTOR_SPURIOUS, (PVOID)HandleApicSpuriousService);
-    KE::Irq::SetInterruptHandler(PIC1_VECTOR_SPURIOUS, (PVOID)HandlePicSpuriousService);
+    HL::Irq::RegisterInterruptHandler(APIC_VECTOR_SPURIOUS, (PVOID)ArHandleSpuriousInterrupt);
+    HL::Irq::RegisterSystemInterruptHandler(APIC_VECTOR_PROFILE, HL::Irq::HandleProfileInterrupt);
 
     /* Clear any pre-existing errors */
     WriteApicRegister(APIC_ESR, 0);
@@ -216,6 +430,84 @@ HL::Pic::InitializeApic(VOID)
     WriteApicRegister(APIC_TPR, 0x00);
 }
 
+/**
+ * Initializes the global I/O APIC controller setup over the entire redirection span.
+ *
+ * @return This routine does not return any value.
+ *
+ * @since XT 1.0
+ */
+XTAPI
+VOID
+HL::Pic::InitializeIOApic(VOID)
+{
+    ULONG ControllerIndex, LineIndex, Vector, VersionRegister;
+    IOAPIC_REDIRECTION_REGISTER Register;
+    XTSTATUS Status;
+
+    /* Detect I/O APIC controllers */
+    Status = DetectIoApicControllers();
+    if(Status != STATUS_SUCCESS)
+    {
+        DebugPrint(L"ERROR: I/O APIC Controller not present.\n");
+        KE::Crash::Panic(0x5D, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF);
+    }
+
+    /* Iterate over all I/O APIC controllers */
+    ControllerIndex = 0;
+    while(ControllerIndex < ControllerCount)
+    {
+        /* Map the I/O APIC controller memory into hardware space */
+        MM::HardwarePool::MapHardwareMemory(Controllers[ControllerIndex].PhysicalAddress,
+                                            1,
+                                            FALSE,
+                                            (PVOID*)&Controllers[ControllerIndex].VirtualAddress);
+
+        /* Perform a memory barrier */
+        AR::CpuFunc::MemoryBarrier();
+        AR::CpuFunc::ReadWriteBarrier();
+
+        /* Read the version register and calculate the maximum number of redirection entries */
+        VersionRegister = ReadIOApicRegister(&Controllers[ControllerIndex], IOAPIC_VER);
+        Controllers[ControllerIndex].LineCount = ((VersionRegister >> 16) & 0xFF) + 1;
+
+        /* Set up the default redirection entry for this controller */
+        Register.DeliveryMode = APIC_DM_FIXED;
+        Register.DeliveryStatus = 0;
+        Register.Destination = ReadIOApicRegister(&Controllers[ControllerIndex], IOAPIC_ID) >> 24;
+        Register.DestinationMode = 0;
+        Register.Mask = 1;
+        Register.PinPolarity = 0;
+        Register.RemoteIRR = 0;
+        Register.Reserved = 0;
+        Register.TriggerMode = APIC_TGM_EDGE;
+        Register.Vector = IOAPIC_VECTOR_FREE;
+
+        /* Propagate defaults across the array of potential handlers */
+        for(LineIndex = 0; LineIndex < Controllers[ControllerIndex].LineCount; LineIndex++)
+        {
+            /* Write default values into the redirection table */
+            WriteRedirectionEntry(&Controllers[ControllerIndex], LineIndex, Register);
+        }
+
+        /* Print information about the I/O APIC controller */
+        DebugPrint(L"Initialized I/O APIC Controller #%lu at 0x%llX (ID: %lu, GSI Base: %lu, Line Count: %lu)\n",
+                   ControllerIndex, Controllers[ControllerIndex].VirtualAddress,
+                   Controllers[ControllerIndex].Identifier, Controllers[ControllerIndex].GsiBase,
+                   Controllers[ControllerIndex].LineCount);
+
+        /* Go to the next I/O APIC controller */
+        ControllerIndex++;
+    }
+
+    /* Assign initial clean state for mapping translations */
+    for(Vector = 0; Vector <= 255; Vector++)
+    {
+        /* Set vector to free */
+        MappedVectors[Vector] = IOAPIC_VECTOR_FREE;
+    }
+}
+
 /**
  * Initializes the legacy PIC interrupt controller.
  *
@@ -289,6 +581,9 @@ HL::Pic::InitializeLegacyPic(VOID)
 
     /* Mask all interrupts on PIC2 port */
     HL::IoPort::WritePort8(PIC2_DATA_PORT, 0xFF);
+
+    /* Register interrupt handler */
+    HL::Irq::RegisterInterruptHandler(PIC1_VECTOR_SPURIOUS, (PVOID)ArHandleSpuriousInterrupt);
 }
 
 /**
@@ -333,10 +628,108 @@ HL::Pic::ReadApicRegister(IN APIC_REGISTER Register)
     else
     {
         /* Read from xAPIC */
-        return IoRegister::ReadRegister32((PULONG)(APIC_BASE + (Register << 4)));
+        return HL::IoRegister::ReadRegister32((PULONG)(APIC_BASE + (Register << 4)));
     }
 }
 
+/**
+ * Reads from the I/O APIC register.
+ *
+ * @param Controller
+ *        Supplies the I/O APIC controller to read from.
+ *
+ * @param Register
+ *        Supplies the I/O APIC register to read from.
+ *
+ * @return This routine returns the value read from the given IO APIC register.
+ *
+ * @since XT 1.0
+ */
+XTFASTCALL
+ULONG
+HL::Pic::ReadIOApicRegister(IN PIOAPIC_DATA Controller,
+                            IN UCHAR Register)
+{
+    /* Write the target address into the index register */
+    HL::IoRegister::WriteRegister32((PULONG)(Controller->VirtualAddress + IOAPIC_IOREGSEL), Register);
+
+    /* Fetch the resultant value from the data window */
+    return HL::IoRegister::ReadRegister32((PULONG)(Controller->VirtualAddress + IOAPIC_IOWIN));
+}
+
+/**
+ * Reads a configuration entry from the I/O APIC redirection table.
+ *
+ * @param Controller
+ *        Supplies the I/O APIC controller to read from.
+ *
+ * @param EntryNumber
+ *        Supplies the redirection table entry number to read.
+ *
+ * @return This routine returns the populated redirection table entry.
+ *
+ * @since XT 1.0
+ */
+XTFASTCALL
+IOAPIC_REDIRECTION_REGISTER
+HL::Pic::ReadRedirectionEntry(IN PIOAPIC_DATA Controller,
+                              IN ULONG EntryNumber)
+{
+    IOAPIC_REDIRECTION_REGISTER Register;
+    ULONG Offset;
+
+    /* Derive the offset corresponding to the index */
+    Offset = IOAPIC_REDTBL + (EntryNumber * IOAPIC_RTE_SIZE);
+
+    /* Read the low and high portions mapping to the 64-bit construct */
+    Register.Base = ReadIOApicRegister(Controller, Offset);
+    Register.Extended = ReadIOApicRegister(Controller, Offset + 1);
+
+    /* Return the redirection table entry */
+    return Register;
+}
+
+/**
+ * Resolves the GSI and flags for the specified IRQ.
+ *
+ * @param Irq
+ *        Supplies the IRQ number to get the GSI and flags for.
+ *
+ * @param Gsi
+ *        Supplies a pointer to the memory area where the GSI will be stored.
+ *
+ * @param Flags
+ *        Supplies a pointer to the memory area where the flags will be stored.
+ *
+ * @return This routine does not return any value.
+ *
+ * @since XT 1.0
+ */
+XTAPI
+VOID
+HL::Pic::ResolveInterruptOverride(IN UCHAR Irq,
+                                  OUT PULONG Gsi,
+                                  OUT PUSHORT Flags)
+{
+    ULONG Index;
+
+    /* Iterate over all I/O APIC overrides */
+    for(Index = 0; Index < IrqOverrideCount; Index++)
+    {
+        /* Check if this IRQ has been overridden */
+        if(IrqOverrides[Index].SourceIrq == Irq)
+        {
+            /* Return overridden GSI and flags */
+            *Flags = IrqOverrides[Index].Flags;
+            *Gsi = IrqOverrides[Index].GlobalSystemInterrupt;
+        }
+    }
+
+    /* Return original IRQ number as GSI and no flags */
+    *Flags = 0;
+    *Gsi = (ULONG)Irq;
+}
+
 /**
  * Signals to the APIC that handling an interrupt is complete.
  *
@@ -367,8 +760,8 @@ HL::Pic::SendEoi(VOID)
  */
 XTAPI
 VOID
-HL::Pic::SendIpi(ULONG ApicId,
-                 ULONG Vector)
+HL::Pic::SendIpi(IN ULONG ApicId,
+                 IN ULONG Vector)
 {
     /* Check current APIC mode */
     if(ApicMode == APIC_MODE_X2APIC)
@@ -384,6 +777,96 @@ HL::Pic::SendIpi(ULONG ApicId,
     }
 }
 
+/**
+ * Sends a Self-IPI (Inter-Processor Interrupt) to the current CPU.
+ *
+ * @param Vector
+ *        Supplies the IPI vector to send.
+ *
+ * @return This routine does not return any value.
+ *
+ * @since XT 1.0
+ */
+XTAPI
+VOID
+HL::Pic::SendSelfIpi(IN ULONG Vector)
+{
+    BOOLEAN Interrupts;
+
+    /* Check whether interrupts are enabled */
+    Interrupts = AR::CpuFunc::InterruptsEnabled();
+
+    /* Disable interrupts */
+    AR::CpuFunc::ClearInterruptFlag();
+
+    /* Check current APIC mode */
+    if(ApicMode == APIC_MODE_X2APIC)
+    {
+        /* In x2APIC mode, a dedicated Self-IPI register is used */
+        WriteApicRegister(APIC_SIPI, Vector);
+    }
+    else
+    {
+        /* Wait for the APIC to clear the delivery status */
+        while((ReadApicRegister(APIC_ICR0) & 0x1000) != 0)
+        {
+            /* Yield the processor */
+            AR::CpuFunc::YieldProcessor();
+        }
+
+        /* In xAPIC compatibility mode, ICR0 is used */
+        WriteApicRegister(APIC_ICR0, Vector | (1 << 18));
+    }
+
+    /* Wait for the APIC to complete delivery of the IPI */
+    while((ReadApicRegister(APIC_ICR0) & 0x1000) != 0)
+    {
+        /* Yield the processor */
+        AR::CpuFunc::YieldProcessor();
+    }
+
+    /* Check whether interrupts need to be re-enabled */
+    if(Interrupts)
+    {
+        /* Re-enable interrupts */
+        AR::CpuFunc::SetInterruptFlag();
+    }
+}
+
+/**
+ * Translates a given Global System Interrupt (GSI) into an active system interrupt vector.
+ *
+ * @param Gsi
+ *        Supplies the GSI to translate.
+ *
+ * @return This routine returns the underlying associated system vector mapping.
+ *
+ * @since XT 1.0
+ */
+XTFASTCALL
+UCHAR
+HL::Pic::TranslateGsiToVector(IN ULONG Gsi)
+{
+    IOAPIC_REDIRECTION_REGISTER Register;
+    PIOAPIC_DATA Controller;
+    ULONG EntryNumber;
+    XTSTATUS Status;
+
+    /* Find the APIC controller for the GSI */
+    Status = GetIoApicController(Gsi, &Controller, &EntryNumber);
+    if(Status != STATUS_SUCCESS)
+    {
+        /* GSI maps to an invalid controller, return free */
+        return IOAPIC_VECTOR_FREE;
+    }
+
+    /* Read the redirection table entry */
+    Register.Base = ReadIOApicRegister(Controller, IOAPIC_REDTBL + (EntryNumber * IOAPIC_RTE_SIZE));
+
+    /* Return the vector */
+    return (UCHAR)Register.Vector;
+}
+
 /**
  * Writes to the APIC register.
  *
@@ -410,6 +893,70 @@ HL::Pic::WriteApicRegister(IN APIC_REGISTER Register,
     else
     {
         /* Write to xAPIC */
-        IoRegister::WriteRegister32((PULONG)(APIC_BASE + (Register << 4)), Value);
+        HL::IoRegister::WriteRegister32((PULONG)(APIC_BASE + (Register << 4)), Value);
     }
 }
+
+/**
+ * Writes a value to the I/O APIC register.
+ *
+ * @param Controller
+ *        Supplies the I/O APIC controller to write to.
+ *
+ * @param Register
+ *        Supplies the I/O APIC register to write to.
+ *
+ * @param DataValue
+ *        Supplies the value to write to the designated I/O APIC register.
+ *
+ * @return This routine does not return any value.
+ *
+ * @since XT 1.0
+ */
+XTFASTCALL
+VOID
+HL::Pic::WriteIOApicRegister(IN PIOAPIC_DATA Controller,
+                             IN UCHAR Register,
+                             IN ULONG DataValue)
+{
+    /* Provide the index to the control port */
+    HL::IoRegister::WriteRegister32((PULONG)(Controller->VirtualAddress + IOAPIC_IOREGSEL), Register);
+
+    /* Commit the value via the data port */
+    HL::IoRegister::WriteRegister32((PULONG)(Controller->VirtualAddress + IOAPIC_IOWIN), DataValue);
+}
+
+/**
+ * Writes a configuration entry into the I/O APIC redirection table.
+ *
+ * @param Controller
+ *        Supplies the I/O APIC controller to write to.
+ *
+ * @param EntryNumber
+ *        Supplies the redirection table entry number to write.
+ *
+ * @param EntryData
+ *        Supplies the redirection table entry data to write.
+ *
+ * @return This routine does not return any value.
+ *
+ * @since XT 1.0
+ */
+XTFASTCALL
+VOID
+HL::Pic::WriteRedirectionEntry(IN PIOAPIC_DATA Controller,
+                               IN ULONG EntryNumber,
+                               IN IOAPIC_REDIRECTION_REGISTER EntryData)
+{
+    ULONG Offset;
+
+    /* Calculate the offset of the redirection entry */
+    Offset = IOAPIC_REDTBL + (EntryNumber * IOAPIC_RTE_SIZE);
+
+    /* Mask the entry to prevent spurious interrupts */
+    WriteIOApicRegister(Controller, Offset, IOAPIC_RTE_MASKED);
+
+    /* Write the lower and upper chunks of the entry */
+    WriteIOApicRegister(Controller, Offset + 1, EntryData.Extended);
+    WriteIOApicRegister(Controller, Offset, EntryData.Base);
+}

xtoskrnl/hl/x86/timer.cc

@@ -0,0 +1,439 @@
+/**
+ * PROJECT:         ExectOS
+ * COPYRIGHT:       See COPYING.md in the top level directory
+ * FILE:            xtoskrnl/hl/x86/timer.cc
+ * DESCRIPTION:     APIC Timer support for x86 (i686/AMD64) support
+ * DEVELOPERS:      Aiken Harris <harraiken91@gmail.com>
+ */
+
+#include <xtos.hh>
+
+
+/**
+ * Calibrates the Local APIC timer frequency.
+ *
+ * @return This routine returns a status code.
+ *
+ * @since XT 1.0
+ */
+XTAPI
+XTSTATUS
+HL::Timer::CalibrateApicTimer()
+{
+    ULONG CurrentCount, Frequency, InitialCount;
+
+    /* Get APIC timer frequency from the Core Crystal Clock */
+    if(TimerCapabilities.Art && TimerCapabilities.TimerFrequency != 0)
+    {
+        /* CCC available, use it as the source of APIC timer frequency */
+        Frequency = TimerCapabilities.TimerFrequency;
+    }
+    else
+    {
+        /* CCC unavailable, fallback to PIT calibration */
+        InitialCount = 0xFFFFFFFF;
+
+        /* Load the initial count into the APIC Timer and begin the countdown */
+        HL::Pic::WriteApicRegister(APIC_TICR, InitialCount);
+
+        /* Wait for 10ms */
+        StallExecution(10000);
+
+        /* Read current tick count from APIC timer and clear APIC timer */
+        CurrentCount = HL::Pic::ReadApicRegister(APIC_TCCR);
+        HL::Pic::WriteApicRegister(APIC_TICR, 0);
+
+        /* Calculate APIC timer frequency based on ticks passed */
+        Frequency = (InitialCount - CurrentCount) * 100;
+
+        /* Verify APIC timer frequency */
+        if(Frequency == 0)
+        {
+            /* Unable to calibrate APIC timer, return error */
+            return STATUS_UNSUCCESSFUL;
+        }
+    }
+
+    /* Save APIC timer frequency */
+    TimerFrequency = Frequency;
+
+    /* Print APIC timer frequency and return success */
+    DebugPrint(L"APIC Timer calibrated: %u Ticks/s\n", TimerFrequency);
+    return STATUS_SUCCESS;
+}
+
+/**
+ * Initializes and calibrates the Local APIC Timer.
+ *
+ * @return This routine does not return any value.
+ *
+ * @since XT 1.0
+ */
+XTAPI
+VOID
+HL::Timer::InitializeApicTimer(VOID)
+{
+    XTSTATUS Status;
+
+    /* Set APIC timer to divide by 1 */
+    HL::Pic::WriteApicRegister(APIC_TDCR, TIMER_DivideBy1);
+
+    /* Calibrate the APIC timer */
+    Status = CalibrateApicTimer();
+    if(Status != STATUS_SUCCESS)
+    {
+        /* System cannot operate without a calibrated system timer, raise kernel panic */
+        KE::Crash::Panic(0);
+    }
+
+    /* Set the default system profile interval */
+    HL::Timer::SetProfileInterval(1000);
+
+    /* Program the APIC timer for periodic mode */
+    StopProfileInterrupt(ProfileXtKernel);
+}
+
+/**
+ * Performs a basic Timer initialization.
+ *
+ * @return This routine does not return any value.
+ *
+ * @since XT 1.0
+ */
+XTAPI
+VOID
+HL::Timer::InitializeTimer(VOID)
+{
+    /* Query timer capabilities */
+    QueryTimerCapabilities();
+
+    /* Initialize the APIC timer */
+    InitializeApicTimer();
+}
+
+/**
+ * Stalls the CPU execution for a specified duration (maximum 3 seconds) using the legacy PIT timer.
+ *
+ * @param MicroSeconds
+ *        Specifies the number of microseconds to stall execution.
+ *
+ * @return This routine does not return any value.
+ *
+ * @since XT 1.0
+ */
+XTAPI
+VOID
+HL::Timer::PitStallExecution(IN ULONG MicroSeconds)
+{
+    USHORT CurrentCount, PreviousCount;
+    ULONG TargetTicks, TickCounter;
+
+    /* Validate input parameter */
+    if(MicroSeconds == 0)
+    {
+        /* Nothing to do */
+        return;
+    }
+    else if(MicroSeconds > 3000000)
+    {
+        /* Cap execution stall to 3 seconds */
+        MicroSeconds = 3000000;
+    }
+
+    /* Convert us to PIT ticks and initialize tick counter */
+    TargetTicks = (MicroSeconds * 1193) / 1000;
+    TickCounter = 0;
+
+    /* Configure PIT Channel 0: Read/Write LSB then MSB, Mode 0 (Interrupt on Terminal Count) */
+    HL::IoPort::WritePort8(PIT_COMMAND_PORT, 0x30);
+
+    /* Initialize the PIT counter with the maximum possible value (0xFFFF) */
+    HL::IoPort::WritePort8(PIT_DATA_PORT0, 0xFF);
+    HL::IoPort::WritePort8(PIT_DATA_PORT0, 0xFF);
+
+    /* Latch and read the initial counter value */
+    HL::IoPort::WritePort8(PIT_COMMAND_PORT, 0x00);
+    PreviousCount = HL::IoPort::ReadPort8(PIT_DATA_PORT0);
+    PreviousCount |= (HL::IoPort::ReadPort8(PIT_DATA_PORT0) << 8);
+
+    /* Poll the PIT */
+    while(TickCounter < TargetTicks)
+    {
+        /* Latch the current counter value without stopping the timer */
+        HL::IoPort::WritePort8(PIT_COMMAND_PORT, 0x00);
+        CurrentCount = HL::IoPort::ReadPort8(PIT_DATA_PORT0);
+        CurrentCount |= (HL::IoPort::ReadPort8(PIT_DATA_PORT0) << 8);
+
+        /* Calculate elapsed ticks since the last read */
+        TickCounter += (PreviousCount - CurrentCount) & 0xFFFF;
+
+        /* Update the tracking variable */
+        PreviousCount = CurrentCount;
+    }
+}
+
+/**
+ * Probes the processor via CPUID to detect available modern timing and clock generation features.
+ *
+ * @return This routine does not return any value.
+ *
+ * @since XT 1.0
+ */
+XTAPI
+VOID
+HL::Timer::QueryTimerCapabilities(VOID)
+{
+    CPUID_REGISTERS CpuRegisters;
+    ULONG MaxStandardLeaf;
+    ULONG MaxExtendedLeaf;
+
+    /* Query maximum standard CPUID leaf */
+    CpuRegisters.Leaf = CPUID_GET_VENDOR_STRING;
+    CpuRegisters.SubLeaf = 0;
+    CpuRegisters.Eax = 0;
+    CpuRegisters.Ebx = 0;
+    CpuRegisters.Ecx = 0;
+    CpuRegisters.Edx = 0;
+    AR::CpuFunc::CpuId(&CpuRegisters);
+
+    /* Save maximum supported standard CPUID leaf */
+    MaxStandardLeaf = CpuRegisters.Eax;
+
+    /* Query maximum extended CPUID leaf */
+    CpuRegisters.Leaf = CPUID_GET_EXTENDED_MAX;
+    CpuRegisters.SubLeaf = 0;
+    CpuRegisters.Eax = 0;
+    CpuRegisters.Ebx = 0;
+    CpuRegisters.Ecx = 0;
+    CpuRegisters.Edx = 0;
+    AR::CpuFunc::CpuId(&CpuRegisters);
+
+    /* Save maximum supported extended CPUID leaf */
+    MaxExtendedLeaf = CpuRegisters.Eax;
+
+    /* Check TSC-Deadline mode if leaf supported */
+    if(MaxStandardLeaf >= CPUID_GET_STANDARD1_FEATURES)
+    {
+        CpuRegisters.Leaf = CPUID_GET_STANDARD1_FEATURES;
+        CpuRegisters.SubLeaf = 0;
+        CpuRegisters.Eax = 0;
+        CpuRegisters.Ebx = 0;
+        CpuRegisters.Ecx = 0;
+        CpuRegisters.Edx = 0;
+        AR::CpuFunc::CpuId(&CpuRegisters);
+
+        /* Verify TSC-Deadline support */
+        if(CpuRegisters.Ecx & CPUID_FEATURES_ECX_TSC_DEADLINE)
+        {
+            TimerCapabilities.TscDeadline = TRUE;
+        }
+    }
+
+    /* Check Always Running APIC Timer - ARAT if leaf supported */
+    if(MaxStandardLeaf >= CPUID_GET_POWER_MANAGEMENT)
+    {
+        CpuRegisters.Leaf = CPUID_GET_POWER_MANAGEMENT;
+        CpuRegisters.SubLeaf = 0;
+        CpuRegisters.Eax = 0;
+        CpuRegisters.Ebx = 0;
+        CpuRegisters.Ecx = 0;
+        CpuRegisters.Edx = 0;
+        AR::CpuFunc::CpuId(&CpuRegisters);
+
+        /* Verify ARAT support */
+        if(CpuRegisters.Eax & CPUID_FEATURES_EAX_ARAT)
+        {
+            TimerCapabilities.Arat = TRUE;
+        }
+    }
+
+    /* Check Always Running Timer - ART if leaf supported */
+    if(MaxStandardLeaf >= CPUID_GET_TSC_CRYSTAL_CLOCK)
+    {
+        CpuRegisters.Leaf = CPUID_GET_TSC_CRYSTAL_CLOCK;
+        CpuRegisters.SubLeaf = 0;
+        CpuRegisters.Eax = 0;
+        CpuRegisters.Ebx = 0;
+        CpuRegisters.Ecx = 0;
+        CpuRegisters.Edx = 0;
+        AR::CpuFunc::CpuId(&CpuRegisters);
+
+        /* Verify ART support */
+        if(CpuRegisters.Eax != 0 && CpuRegisters.Ebx != 0)
+        {
+            TimerCapabilities.Art = TRUE;
+
+            /* Save the TSC scaling ratios */
+            TimerCapabilities.TscDenominator = CpuRegisters.Eax;
+            TimerCapabilities.TscNumerator = CpuRegisters.Ebx;
+
+            /* Check if ECX contains the nominal frequency of the core crystal clock */
+            if(CpuRegisters.Ecx != 0)
+            {
+                /* Save the base frequency for the APIC Timer */
+                TimerCapabilities.TimerFrequency = CpuRegisters.Ecx;
+            }
+        }
+    }
+
+    /* Check RDTSCP instruction support if leaf supported */
+    if(MaxExtendedLeaf >= CPUID_GET_EXTENDED_FEATURES)
+    {
+        CpuRegisters.Leaf = CPUID_GET_EXTENDED_FEATURES;
+        CpuRegisters.SubLeaf = 0;
+        CpuRegisters.Eax = 0;
+        CpuRegisters.Ebx = 0;
+        CpuRegisters.Ecx = 0;
+        CpuRegisters.Edx = 0;
+        AR::CpuFunc::CpuId(&CpuRegisters);
+
+        /* Verify RDTSCP support */
+        if(CpuRegisters.Edx & CPUID_FEATURES_EDX_RDTSCP)
+        {
+            TimerCapabilities.RDTSCP = TRUE;
+        }
+    }
+
+    /* Check Invariant TSC if leaf supported */
+    if(MaxExtendedLeaf >= CPUID_GET_ADVANCED_POWER_MANAGEMENT)
+    {
+        CpuRegisters.Leaf = CPUID_GET_ADVANCED_POWER_MANAGEMENT;
+        CpuRegisters.SubLeaf = 0;
+        CpuRegisters.Eax = 0;
+        CpuRegisters.Ebx = 0;
+        CpuRegisters.Ecx = 0;
+        CpuRegisters.Edx = 0;
+        AR::CpuFunc::CpuId(&CpuRegisters);
+
+        /* Verify Invariant TSC support */
+        if(CpuRegisters.Edx & CPUID_FEATURES_EDX_TSCI)
+        {
+            TimerCapabilities.InvariantTsc = TRUE;
+        }
+    }
+}
+
+/**
+ * Sets the profile interrupt interval. The interval may be bounded by hardware capabilities.
+ *
+ * @param Interval
+ *        Supplies the requested profile interval in 100-nanosecond units.
+ *
+ * @return This routine returns the actual profile interval that was set.
+ *
+ * @since XT 1.0
+ */
+XTAPI
+ULONG_PTR
+HL::Timer::SetProfileInterval(IN ULONG_PTR Interval)
+{
+    /* Validate and bound the requested profile interval against hardware limits */
+    if(Interval < MIN_PROFILE_INTERVAL)
+    {
+        /* Enforce the minimum profile interval limit */
+        Interval = MIN_PROFILE_INTERVAL;
+    }
+    else if(Interval > MAX_PROFILE_INTERVAL)
+    {
+        /* Enforce the maximum profile interval limit */
+        Interval = MAX_PROFILE_INTERVAL;
+    }
+
+    /* Calculate the number of APIC timer ticks required for the requested interval */
+    ProfilingInterval = (TimerFrequency / 10000) * (Interval / 1000);
+
+    /* Update the APIC Timer Initial Count Register (TICR) to apply the new interval immediately */
+    HL::Pic::WriteApicRegister(APIC_TICR, ProfilingInterval);
+
+    /* Return the actual interval */
+    return Interval;
+}
+
+/**
+ * Stalls the CPU execution for a specified duration.
+ *
+ * @param MicroSeconds
+ *        Supplies the number of microseconds to stall execution.
+ *
+ * @return This routine does not return any value.
+ *
+ * @since XT 1.0
+ */
+XTAPI
+VOID
+HL::Timer::StallExecution(IN ULONG MicroSeconds)
+{
+    UNIMPLEMENTED;
+
+    /* ACPI PM Timer not supported, fall back to PIT */
+    PitStallExecution(MicroSeconds);
+}
+
+/**
+ * Enables the profile interrupt for the specified profile source.
+ *
+ * @param ProfileSource
+ *        Supplies the source of the profile interrupt to start.
+ *
+ * @return This routine does not return any value.
+ *
+ * @since XT 1.0
+ */
+XTAPI
+VOID
+HL::Timer::StartProfileInterrupt(IN KPROFILE_SOURCE ProfileSource)
+{
+    APIC_LVT_REGISTER LvtRegister;
+
+    /* Handle only ProfileTime and ProfileXtKernel */
+    if(ProfileSource != ProfileTime && ProfileSource != ProfileXtKernel)
+    {
+        /* Invalid profile source, do nothing */
+        return;
+    }
+
+    /* Set the interval */
+    HL::Pic::WriteApicRegister(APIC_TICR, ProfilingInterval);
+
+    /* Unmask interrupt */
+    LvtRegister.Long = 0;
+    LvtRegister.Mask = 0;
+    LvtRegister.DeliveryMode = APIC_DM_FIXED;
+    LvtRegister.TimerMode = 1;
+    LvtRegister.TriggerMode = APIC_TGM_EDGE;
+    LvtRegister.Vector = APIC_VECTOR_PROFILE;
+    HL::Pic::WriteApicRegister(APIC_TMRLVTR, LvtRegister.Long);
+}
+
+/**
+ * Disables the profile interrupt for the specified profile source.
+ *
+ * @param ProfileSource
+ *        Supplies the source of the profile interrupt to stop.
+ *
+ * @return This routine does not return any value.
+ *
+ * @since XT 1.0
+ */
+XTAPI
+VOID
+HL::Timer::StopProfileInterrupt(IN KPROFILE_SOURCE ProfileSource)
+{
+    APIC_LVT_REGISTER LvtRegister;
+
+    /* Handle only ProfileTime and ProfileXtKernel */
+    if(ProfileSource != ProfileTime && ProfileSource != ProfileXtKernel)
+    {
+        /* Invalid profile source, do nothing */
+        return;
+    }
+
+    /* Mask interrupt */
+    LvtRegister.Long = 0;
+    LvtRegister.Mask = 1;
+    LvtRegister.DeliveryMode = APIC_DM_FIXED;
+    LvtRegister.TimerMode = 1;
+    LvtRegister.TriggerMode = APIC_TGM_EDGE;
+    LvtRegister.Vector = APIC_VECTOR_PROFILE;
+    HL::Pic::WriteApicRegister(APIC_TMRLVTR, LvtRegister.Long);
+}

xtoskrnl/includes/ar.hh

@@ -11,7 +11,7 @@
 
 #include <xtos.hh>
 
-#include XTOS_ARCH_HEADER(ar, assembly.hh)
+#include XTOS_ARCH_HEADER(ar, asmsup.hh)
 #include XTOS_ARCH_HEADER(ar, cpufunc.hh)
 #include XTOS_ARCH_HEADER(ar, procsup.hh)
 #include XTOS_ARCH_HEADER(ar, traps.hh)

xtoskrnl/includes/ar/amd64/asmsup.h

@@ -1,64 +0,0 @@
-/**
- * PROJECT:         ExectOS
- * COPYRIGHT:       See COPYING.md in the top level directory
- * FILE:            xtoskrnl/includes/amd64/asm.h
- * DESCRIPTION:     AMD64 architecture assembly definitions
- * DEVELOPERS:      Rafal Kupiec <belliash@codingworkshop.eu.org>
- */
-
-#ifndef __XTOSKRNL_AMD64_ASMSUP_H
-#define __XTOSKRNL_AMD64_ASMSUP_H
-
-
-/* Control Register bit definitions */
-#define CR0_PG                                  0x80000000
-#define CR4_PGE                                 0x00000080
-#define CR4_LA57                                0x00001000
-#define CR4_PCIDE                               0x00020000
-
-/* GDT selectors */
-#define GDT_R0_CMCODE                           0x08
-#define GDT_R0_CODE                             0x10
-#define GDT_R0_DATA                             0x18
-
-/* MSR registers */
-#define X86_MSR_EFER                            0xC0000080
-#define X86_MSR_EFER_LME                        (1 <<  8)
-
-/* KTRAP_FRAME structure offsets */
-#define TrapXmm0                                0
-#define TrapXmm1                                16
-#define TrapXmm2                                32
-#define TrapXmm3                                48
-#define TrapXmm4                                64
-#define TrapXmm5                                80
-#define TrapXmm6                                96
-#define TrapXmm7                                112
-#define TrapXmm8                                128
-#define TrapXmm9                                144
-#define TrapXmm10                               160
-#define TrapXmm11                               176
-#define TrapXmm12                               192
-#define TrapXmm13                               208
-#define TrapXmm14                               224
-#define TrapXmm15                               240
-#define TrapMxCsr                               256
-#define TrapPreviousMode                        260
-#define TrapCr2                                 264
-#define TrapCr3                                 272
-#define TrapDr0                                 280
-#define TrapDr1                                 288
-#define TrapDr2                                 296
-#define TrapDr3                                 304
-#define TrapDr6                                 312
-#define TrapDr7                                 320
-#define TrapSegDs                               328
-#define TrapSegEs                               330
-#define TrapSegFs                               332
-#define TrapSegGs                               334
-
-/* KTRAP_FRAME length related definitions */
-#define TRAP_FRAME_SIZE                         512
-#define TRAP_REGISTERS_SIZE                     176
-
-#endif /* __XTOSKRNL_AMD64_ASMSUP_H */

xtoskrnl/includes/ar/amd64/asmsup.hh

@@ -0,0 +1,43 @@
+/**
+ * PROJECT:         ExectOS
+ * COPYRIGHT:       See COPYING.md in the top level directory
+ * FILE:            xtoskrnl/includes/ar/amd64/asmsup.hh
+ * DESCRIPTION:     Architecture-specific assembler prototypes
+ * DEVELOPERS:      Aiken Harris <harraiken91@gmail.com>
+ */
+
+#ifndef __XTOSKRNL_AR_ASMSUP_HH
+#define __XTOSKRNL_AR_ASMSUP_HH
+
+#include <xtos.hh>
+
+
+/* TrampolineEnableXpa end address to calculate trampoline size */
+XTCLINK PVOID ArEnableExtendedPhysicalAddressingEnd[];
+
+/* External array of pointers to the interrupt handlers */
+XTCLINK ULONG_PTR ArInterruptEntry[256];
+
+/* TrampolineApStartup end address to calculate trampoline size */
+XTCLINK PVOID ArStartApplicationProcessorEnd[];
+
+/* External array of pointers to the trap handlers */
+XTCLINK ULONG_PTR ArTrapEntry[256];
+
+/* Forward reference for assembler code */
+XTCLINK
+XTCDECL
+VOID
+ArEnableExtendedPhysicalAddressing(IN ULONG_PTR PageMap);
+
+XTCLINK
+XTCDECL
+VOID
+ArHandleSpuriousInterrupt(VOID);
+
+XTCLINK
+XTCDECL
+VOID
+ArStartApplicationProcessor(VOID);
+
+#endif /* __XTOSKRNL_AR_ASMSUP_HH */

xtoskrnl/includes/ar/amd64/assembly.hh

@@ -1,158 +0,0 @@
-/**
- * PROJECT:         ExectOS
- * COPYRIGHT:       See COPYING.md in the top level directory
- * FILE:            xtoskrnl/includes/ar/amd64/assembly.hh
- * DESCRIPTION:     Architecture-specific assembler prototypes
- * DEVELOPERS:      Aiken Harris <harraiken91@gmail.com>
- */
-
-#ifndef __XTOSKRNL_AR_ASSEMBLY_HH
-#define __XTOSKRNL_AR_ASSEMBLY_HH
-
-#include <xtos.hh>
-
-
-/* TrampolineEnableXpa end address to calculate trampoline size */
-XTCLINK PVOID ArEnableExtendedPhysicalAddressingEnd[];
-
-/* TrampolineApStartup end address to calculate trampoline size */
-XTCLINK PVOID ArStartApplicationProcessorEnd[];
-
-
-/* Forward reference for assembler code */
-XTCLINK
-XTCDECL
-VOID
-ArEnableExtendedPhysicalAddressing(IN ULONG_PTR PageMap);
-
-XTCLINK
-XTCDECL
-VOID
-ArStartApplicationProcessor(VOID);
-
-XTCLINK
-XTCDECL
-VOID
-ArTrap0x00(VOID);
-
-XTCLINK
-XTCDECL
-VOID
-ArTrap0x01(VOID);
-
-XTCLINK
-XTCDECL
-VOID
-ArTrap0x02(VOID);
-
-XTCLINK
-XTCDECL
-VOID
-ArTrap0x03(VOID);
-
-XTCLINK
-XTCDECL
-VOID
-ArTrap0x04(VOID);
-
-XTCLINK
-XTCDECL
-VOID
-ArTrap0x05(VOID);
-
-XTCLINK
-XTCDECL
-VOID
-ArTrap0x06(VOID);
-
-XTCLINK
-XTCDECL
-VOID
-ArTrap0x07(VOID);
-
-XTCLINK
-XTCDECL
-VOID
-ArTrap0x08(VOID);
-
-XTCLINK
-XTCDECL
-VOID
-ArTrap0x09(VOID);
-
-XTCLINK
-XTCDECL
-VOID
-ArTrap0x0A(VOID);
-
-XTCLINK
-XTCDECL
-VOID
-ArTrap0x0B(VOID);
-
-XTCLINK
-XTCDECL
-VOID
-ArTrap0x0C(VOID);
-
-XTCLINK
-XTCDECL
-VOID
-ArTrap0x0D(VOID);
-
-XTCLINK
-XTCDECL
-VOID
-ArTrap0x0E(VOID);
-
-XTCLINK
-XTCDECL
-VOID
-ArTrap0x10(VOID);
-
-XTCLINK
-XTCDECL
-VOID
-ArTrap0x11(VOID);
-
-XTCLINK
-XTCDECL
-VOID
-ArTrap0x12(VOID);
-
-XTCLINK
-XTCDECL
-VOID
-ArTrap0x13(VOID);
-
-XTCLINK
-XTCDECL
-VOID
-ArTrap0x1F(VOID);
-
-XTCLINK
-XTCDECL
-VOID
-ArTrap0x2C(VOID);
-
-XTCLINK
-XTCDECL
-VOID
-ArTrap0x2D(VOID);
-
-XTCLINK
-XTCDECL
-VOID
-ArTrap0x2F(VOID);
-
-XTCLINK
-XTCDECL
-VOID
-ArTrap0xE1(VOID);
-
-XTCLINK
-XTCDECL
-VOID
-ArTrap0xFF(VOID);
-
-#endif /* __XTOSKRNL_AR_ASSEMBLY_HH */

xtoskrnl/includes/ar/amd64/procsup.hh

@@ -24,6 +24,7 @@ namespace AR
             STATIC KIDTENTRY InitialIdt[IDT_ENTRIES];
             STATIC KPROCESSOR_BLOCK InitialProcessorBlock;
             STATIC KTSS InitialTss;
+            STATIC UCHAR NmiStack[KERNEL_STACK_SIZE];
 
         public:
             STATIC XTAPI PVOID GetBootStack(VOID);
@@ -31,6 +32,13 @@ namespace AR
                                                        OUT PVOID *TrampolineCode,
                                                        OUT PULONG_PTR TrampolineSize);
             STATIC XTAPI VOID InitializeProcessor(IN PVOID ProcessorStructures);
+            STATIC XTAPI VOID SetIdtGate(IN PKIDTENTRY Idt,
+                                         IN USHORT Vector,
+                                         IN PVOID Handler,
+                                         IN USHORT Selector,
+                                         IN USHORT Ist,
+                                         IN USHORT Dpl,
+                                         IN USHORT Type);
 
         private:
             STATIC XTAPI VOID IdentifyProcessor(VOID);
@@ -47,11 +55,13 @@ namespace AR
                                                             OUT PKTSS *Tss,
                                                             OUT PKPROCESSOR_BLOCK *ProcessorBlock,
                                                             OUT PVOID *KernelBootStack,
-                                                            OUT PVOID *KernelFaultStack);
+                                                            OUT PVOID *KernelFaultStack,
+                                                            OUT PVOID *KernelNmiStack);
             STATIC XTAPI VOID InitializeSegments(VOID);
             STATIC XTAPI VOID InitializeTss(IN PKPROCESSOR_BLOCK ProcessorBlock,
                                             IN PVOID KernelBootStack,
-                                            IN PVOID KernelFaultStack);
+                                            IN PVOID KernelFaultStack,
+                                            IN PVOID KernelNmiStack);
             STATIC XTAPI VOID SetGdtEntry(IN PKGDTENTRY Gdt,
                                           IN USHORT Selector,
                                           IN ULONG_PTR Base,
@@ -62,12 +72,6 @@ namespace AR
             STATIC XTAPI VOID SetGdtEntryBase(IN PKGDTENTRY Gdt,
                                               IN USHORT Selector,
                                               IN ULONG_PTR Base);
-            STATIC XTAPI VOID SetIdtGate(IN PKIDTENTRY Idt,
-                                         IN USHORT Vector,
-                                         IN PVOID Handler,
-                                         IN USHORT Selector,
-                                         IN USHORT Ist,
-                                         IN USHORT Access);
     };
 }