Refactor XPA detection API

Co-authored-by: Pedro Valadés <perikiyoxd@gmail.com>
Co-committed-by: Pedro Valadés <perikiyoxd@gmail.com>

boot/bootsect/CMakeLists.txt

@@ -1,6 +1,8 @@
 # XT Boot Sector
 PROJECT(BOOTSECT)
 
+add_definitions("-DARCH_ESP_SOURCE=\\\"${ARCH}/cpu.S\\\"")
+
 # Compile boot sectors
 compile_bootsector(mbrboot ${BOOTSECT_SOURCE_DIR}/mbrboot.S 0x7C00 Start)
 compile_bootsector(espboot ${BOOTSECT_SOURCE_DIR}/espboot.S 0x7C00 Start)

boot/bootsect/amd64/cpu.S

@@ -0,0 +1,144 @@
+/**
+ * PROJECT:         ExectOS
+ * COPYRIGHT:       See COPYING.md in the top level directory
+ * FILE:            boot/bootsect/amd64/cpu.S
+ * DESCRIPTION:     Low-level support for CPU initialization
+ * DEVELOPERS:      Aiken Harris <harraiken91@gmail.com>
+ */
+
+
+BuildPageMap:
+    /* Generate page map for first 1GB of memory */
+    pushaw
+    pushw %es
+    cld
+    movw $(0x1000 / 16), %ax
+    movw %ax, %es
+    xorw %di, %di
+    movl $(0x2000 | 0x07), %eax
+    stosl
+    xorl %eax, %eax
+    movw $1021, %cx
+    rep stosl
+    movw $(0x2000 / 16), %ax
+    movw %ax, %es
+    xorw %di, %di
+    movl $(0x3000 | 0x07), %eax
+    stosl
+    xorl %eax, %eax
+    movw $1021, %cx
+    rep stosl
+    movw $(0x3000 / 16), %ax
+    movw %ax, %es
+    xorw %di, %di
+    movw $512, %cx
+    movl $0x00000083, %eax
+.BuildPageMapLoop:
+    /* Identity map 512 pages of 2MB */
+    movl %eax, %es:(%di)
+    addl $2097152, %eax
+    addw $0x08, %di
+    loop .BuildPageMapLoop
+    popw %es
+    popaw
+    ret
+
+InitializeCpu:
+    /* Check if CPU supports CPUID, long mode and PAE */
+    pushal
+    pushfl
+    popl %eax
+    movl %eax, %ebx
+    xorl $0x00200000, %eax
+    pushl %eax
+    popfl
+    pushfl
+    popl %eax
+    cmpl %ebx, %eax
+    je CpuUnsupported
+    movl $0x01, %eax
+    cpuid
+    testl $0x40, %edx
+    jz CpuUnsupported
+    movl $0x80000000, %eax
+    cpuid
+    cmpl $0x80000000, %eax
+    jbe CpuUnsupported
+    movl $0x80000001, %eax
+    cpuid
+    testl $0x20000000, %edx
+    jz CpuUnsupported
+    popal
+    call LoadGdt
+    ret
+
+LoadGdt:
+    /* Load Global Descriptor Table */
+    lgdt .GdtPointer
+    ret
+
+RunStage2:
+    /* Switch to long mode and pass control to Stage 2 */
+    call BuildPageMap
+    call ParseExecutableHeader
+    xorl %edx, %edx
+    pushl %edx
+    pushl %eax
+    cli
+    xorw %ax, %ax
+    movw %ax, %ds
+    movw %ax, %es
+    movw %ax, %fs
+    movw %ax, %gs
+    movw %ax, %ss
+    movl %cr4, %eax
+    orl $0x00A0, %eax
+    movl %eax, %cr4
+    movl $0x00001000, %eax
+    movl %eax, %cr3
+    movl $0xC0000080, %ecx
+    rdmsr
+    orl $0x00000100, %eax
+    wrmsr
+    movl %cr0, %eax
+    orl $0x80000001, %eax
+    movl %eax, %cr0
+    ljmp $0x10, $.Stage2LongMode
+.code64
+.Stage2LongMode:
+    /* Set segments and stack, then jump to Stage 2 */
+    movw $0x18, %ax
+    movw %ax, %ds
+    movw %ax, %es
+    movw %ax, %ss
+    xorw %ax, %ax
+    movw %ax, %fs
+    movw %ax, %gs
+    popq %rax
+    xorq %rbx, %rbx
+    xorq %rcx, %rcx
+    xorq %rdx, %rdx
+    xorq %rsi, %rsi
+    xorq %rdi, %rdi
+    xorq %rbp, %rbp
+    jmp *%rax
+
+.code16
+.GdtDescriptor:
+    /* Global Descriptor Table */
+    .quad 0x0000000000000000
+    .quad 0x0000000000000000
+    .quad 0x00AF9A000000FFFF
+    .quad 0x00CF92000000FFFF
+    .quad 0x00009E000000FFFF
+    .quad 0x000092000000FFFF
+    .quad 0x00CF9B000000FFFF
+
+.GdtPointer:
+    /* Pointer to Global Descriptor Table */
+    .word .GdtPointer - .GdtDescriptor - 1
+    .long .GdtDescriptor
+
+.Stage2FileName:
+    /* Name of Stage 2 executable file */
+    .ascii "BOOTX64 EFI"

boot/bootsect/espboot.S

@@ -121,15 +121,15 @@ VerifyBiosParameterBlock:
     ja FsError
 
 ReadExtraCode:
-    /* Read second VBR sector with extra boot code */
+    /* Read second VBR sector with extra boot code (3 sectors starting from sector 2) */
     movl HiddenSectors - Start(%bp), %eax
     addl $0x02, %eax
-    movw $0x01, %cx
+    movw $0x03, %cx
     xorw %bx, %bx
     movw %bx, %es
     movw $0x7E00, %bx
     call ReadSectors
-    jmp StartSectors
+    jmp StartExtraCode
 
 ReadSectors:
     /* Check for extended BIOS functions and use it only if available */
@@ -139,18 +139,22 @@ ReadSectors:
     movw $0x55AA, %bx
     movb DriveNumber - Start(%bp), %dl
     int $0x13
-    jc ReadCHS
+    jc .ReadCHS
     cmpw $0xAA55, %bx
-    jne ReadCHS
+    jne .ReadCHS
     testb $0x01, %cl
-    jz ReadCHS
+    jz .ReadCHS
 
     /* Verify drive size and determine whether to use CHS or LBA */
     cmpl %edi, %eax
-    jnb ReadLBA
+    jnb .ReadLBA
 
-ReadCHS:
+.ReadCHS:
     /* Read sectors using CHS */
+    popal
+
+.CHSLoop:
+    /* Read sector by sector using CHS */
     pushw %cx
     pushal
     xorl %edx, %edx
@@ -176,11 +180,11 @@ ReadCHS:
     movw %es, %dx
     addw $0x20, %dx
     movw %dx, %es
-    loop ReadCHS
+    loop .CHSLoop
     popw %es
     ret
 
-ReadLBA:
+.ReadLBA:
     /* Prepare DAP packet and read sectors using LBA */
     popal
     pushw %cx
@@ -209,19 +213,19 @@ ReadLBA:
     movw %dx, %es
     popw %bx
     subw %si, %cx
-    jnz ReadLBA
+    jnz .ReadLBA
     popw %es
     ret
 
 DiskError:
     /* Display disk error message and reboot */
-    movw $msgDiskError, %si
+    movw $.MsgDiskError, %si
     call Print
     jmp Reboot
 
 FsError:
     /* Display FS error message and reboot */
-    movw $msgFsError, %si
+    movw $.MsgFsError, %si
     call Print
     jmp Reboot
 
@@ -229,48 +233,297 @@ Print:
     /* Simple routine to print messages */
     lodsb
     orb     %al, %al
-    jz      DonePrint
+    jz      .DonePrint
     movb    $0x0E, %ah
     movw    $0x07, %bx
     int     $0x10
     jmp     Print
-DonePrint:
+.DonePrint:
     retw
 
 Reboot:
     /* Display a message, wait for a key press and reboot */
-    movw $msgAnyKey, %si
+    movw $.MsgAnyKey, %si
     call Print
     xorw %ax, %ax
     int $0x16
     int $0x19
 
-msgAnyKey:
-    .ascii "Press any key to restart\r\n"
+.MsgAnyKey:
+    .ascii "Press any key to restart...\r\n\0"
 
-msgDiskError:
-    .ascii "Disk error\r\n"
+.MsgDiskError:
+    .ascii "Disk error!\r\n\0"
 
-msgFsError:
-    .ascii "File system error\r\n"
+.MsgFsError:
+    .ascii "File system error!\r\n\0"
 
 /* Fill the rest of the VBR with zeros and add VBR signature at the end */
 .fill (510 - (. - Start)), 1, 0
 .word 0xAA55
 
 
-StartSectors:
-    /* Print message */
-    movw $msgUnavailable, %si
+StartExtraCode:
+    /* Load XTLDR file from disk */
+    call LoadStage2
+
+    /* Enable A20 gate */
+    call EnableA20
+
+    /* Call architecture specific initialization code */
+    call InitializeCpu
+
+    /* Jump to Stage2 */
+    call RunStage2
+
+Clear8042:
+    /* Clear 8042 PS/2 buffer */
+    nop
+    nop
+    nop
+    nop
+    inb $0x64, %al
+    cmpb $0xff, %al
+    je .Clear8042_Done
+    testb $0x02, %al
+    jnz Clear8042
+.Clear8042_Done:
+    ret
+
+EnableA20:
+    /* Enable A20 gate */
+    pushaw
+    call Clear8042
+    movb $0xD1, %al
+    outb %al, $0x64
+    call Clear8042
+    movb $0xDF, %al
+    outb %al, $0x60
+    call Clear8042
+    movb $0xFF, %al
+    outb %al, $0x64
+    call Clear8042
+    popaw
+    ret
+
+FindFatEntry:
+    /* Find a file or directory in the FAT table */
+    pushw %bx
+    pushw %cx
+    pushw %dx
+    pushw %si
+    pushw %di
+.FindFatCluster:
+    /* Find FAT32 cluster holding the entry */
+    cmp $0x0FFFFFF8, %eax
+    jae .FindEntryFail
+    pushl %eax
+    movw $0x0200, %bx
+    movw %bx, %es
+    call ReadCluster
+    popl %eax
+    movb SectorsPerCluster - Start(%bp), %cl
+    shlw $0x04, %cx
+    xorw %di, %di
+.FindEntryLoop:
+    /* Find the entry */
+    movb %es:(%di), %al
+    cmpb $0x00, %al
+    je .FindEntryFail
+    cmpb $0xE5, %al
+    je .FindSkipEntry
+    movb %es:0x0B(%di), %ah
+    cmpb $0x0F, %ah
+    je .FindSkipEntry
+    pushw %di
+    pushw %si
+    pushw %cx
+    movw $0x0B, %cx
+    repe cmpsb
+    popw %cx
+    popw %si
+    popw %di
+    jnz .FindSkipEntry
+    movw %es:0x1A(%di), %ax
+    movw %es:0x14(%di), %dx
+    shll $0x10, %edx
+    orl %edx, %eax
+    clc
+    jmp .FindEntryDone
+.FindSkipEntry:
+    /* Skip to the next entry */
+    addw $0x20, %di
+    decw %cx
+    jnz .FindEntryLoop
+    call GetFatEntry
+    jmp .FindFatCluster
+.FindEntryFail:
+    /* Error, file/directory not found */
+    stc
+.FindEntryDone:
+    /* Clean up the stack */
+    popw %di
+    popw %si
+    popw %dx
+    popw %cx
+    popw %bx
+    ret
+
+GetFatEntry:
+    /* Get FAT32 sector and offset from FAT table */
+    shll $0x02, %eax
+    movl %eax, %ecx
+    xorl %edx, %edx
+    movzwl BytesPerSector - Start(%bp), %ebx
+    pushl %ebx
+    divl %ebx
+    movzwl ReservedSectors - Start(%bp), %ebx
+    addl %ebx, %eax
+    movl HiddenSectors - Start(%bp), %ebx
+    addl %ebx, %eax
+    popl %ebx
+    decl %ebx
+    andl %ebx, %ecx
+    movzwl ExtendedFlags - Start(%bp), %ebx
+    andw $0x0F, %bx
+    jz LoadFatSector
+    cmpb FatCopies - Start(%bp), %bl
+    jae FsError
+    pushl %eax
+    movl BigSectorsPerFat - Start(%bp), %eax
+    mull %ebx
+    popl %edx
+    addl %edx, %eax
+
+LoadFatSector:
+    /* Load FAT32 sector from disk */
+    pushl %ecx
+    movw $0x9000, %bx
+    movw %bx, %es
+    cmpl %esi, %eax
+    je .LoadFatSectorDone
+    movl %eax, %esi
+    xorw %bx, %bx
+    movw $0x01, %cx
+    call ReadSectors
+.LoadFatSectorDone:
+    /* Clean up the stack */
+    popl %ecx
+    movl %es:(%ecx), %eax
+    andl $0x0FFFFFFF, %eax
+    ret
+
+LoadStage2:
+    /* Load Stage2 executable, first find file in the path */
+    movl $0xFFFFFFFF, %esi
+    pushl %esi
+    movl 0x7C2C, %eax
+    movw $.EfiDirName, %si
+    call FindFatEntry
+    jc Stage2NotLoaded
+    movw $.BootDirName, %si
+    call FindFatEntry
+    jc Stage2NotLoaded
+    movw $.Stage2FileName, %si
+    call FindFatEntry
+    jc Stage2NotLoaded
+    popl %esi
+    /* Load XTLDR file from disk */
+    cmpl $0x02, %eax
+    jb FileNotFound
+    cmpl $0x0FFFFFF8, %eax
+    jae FileNotFound
+    movw $(0xF800 / 16), %bx
+    movw %bx, %es
+.LoadStage2Loop:
+    /* Load file data from disk */
+    pushl %eax
+    xorw %bx, %bx
+    pushw %es
+    call ReadCluster
+    popw %es
+    xorw %bx, %bx
+    movb SectorsPerCluster - Start(%bp), %bl
+    shlw $0x05, %bx
+    movw %es, %ax
+    addw %bx, %ax
+    movw %ax, %es
+    popl %eax
+    pushw %es
+    call GetFatEntry
+    popw %es
+    cmpl $0x0FFFFFF8, %eax
+    jb .LoadStage2Loop
+    ret
+
+ParseExecutableHeader:
+    /* Parse Stage2 PE/COFF executable header */
+    pushw %es
+    movw $(0xF800 / 16), %ax
+    movw %ax, %es
+    movl %es:60, %eax
+    addl $(4 + 20), %eax
+    movl %es:16(%eax), %eax
+    addl $0xF800, %eax
+    popw %es
+    ret
+
+ReadCluster:
+    /* Read FAT32 cluster from disk */
+    decl %eax
+    decl %eax
+    xorl %edx, %edx
+    movzbl SectorsPerCluster - Start(%bp), %ebx
+    mull %ebx
+    pushl %eax
+    xorl %edx, %edx
+    movzbl FatCopies - Start(%bp), %eax
+    mull BigSectorsPerFat - Start(%bp)
+    movzwl ReservedSectors - Start(%bp), %ebx
+    addl %ebx, %eax
+    addl HiddenSectors - Start(%bp), %eax
+    popl %ebx
+    addl %ebx, %eax
+    xorw %bx, %bx
+    movzbw SectorsPerCluster - Start(%bp), %cx
+    call ReadSectors
+    ret
+
+/* Include architecture specific code */
+.include ARCH_ESP_SOURCE
+
+CpuUnsupported:
+    /* Display CPU unsupported message and reboot */
+    popal
+    movw $.MsgCpuUnsupported, %si
     call Print
+    jmp Reboot
 
-    /* Wait for key press and reboot */
-    xorw %ax, %ax
-    int $0x16
-    int $0x19
+FileNotFound:
+    /* Display XTLDR not found message and reboot */
+    movw $.MsgXtLdrNotFound, %si
+    call Print
+    jmp Reboot
 
-msgUnavailable:
-    .ascii "XTLDR requires EFI-based system!\r\nPress any key to restart\r\n"
+Stage2NotLoaded:
+    /* Clean up the stack and display XTLDR not found message and reboot */
+    popl %esi
+    jmp FileNotFound
 
-/* Fill the rest of the extra VBR with zeros */
-.fill (1024 - (. - Start)), 1, 0
+.BootDirName:
+    /* Boot directory name */
+    .ascii "BOOT       "
+
+.EfiDirName:
+    /* EFI directory name */
+    .ascii "EFI        "
+
+.MsgCpuUnsupported:
+    .ascii "CPU not supported!\r\n\0"
+
+.MsgXtLdrNotFound:
+    .ascii "XTLDR Stage2 not found!\r\n\0"
+
+/* Fill the rest of the extra VBR with zeros and add signature */
+.fill (2043 - (. - Start)), 1, 0
+.ascii "XTLDR"

boot/bootsect/i686/cpu.S

@@ -0,0 +1,124 @@
+/**
+ * PROJECT:         ExectOS
+ * COPYRIGHT:       See COPYING.md in the top level directory
+ * FILE:            boot/bootsect/i686/cpu.S
+ * DESCRIPTION:     Low-level support for CPU initialization
+ * DEVELOPERS:      Aiken Harris <harraiken91@gmail.com>
+ */
+
+
+BuildPageMap:
+    /* Generate page map for first 16MB of memory */
+    pushaw
+    pushw %es
+    cld
+    movw $(0x1000 >> 0x04), %ax
+    movw %ax, %es
+    xorw %di, %di
+    movl $(0x2000 | 0x03), %eax
+    stosl
+    movl $(0x3000 | 0x03), %eax
+    stosl
+    movl $(0x4000 | 0x03), %eax
+    stosl
+    movl $(0x5000 | 0x03), %eax
+    stosl
+    xorl %eax, %eax
+    movw $(1024 - 4), %cx
+    rep stosl
+    movl $0x00000003, %eax
+    movl $4, %edx
+    movw $(0x2000 >> 0x04), %bx
+.BuildPageMapLoop:
+    /* Identity map 1024 pages of 4KB */
+    movw %bx, %es
+    xorw %di, %di
+    pushl %edx
+    movw $1024, %cx
+.FillPageMapTable:
+    /* Fill the page table */
+    movl %eax, %es:(%di)
+    addl $4096, %eax
+    addw $0x04, %di
+    loop .FillPageMapTable
+    popl %edx
+    addw $(0x1000 >> 0x04), %bx
+    decl %edx
+    jnz .BuildPageMapLoop
+    popw %es
+    popaw
+    ret
+
+InitializeCpu:
+    /* Check if CPU supports CPUID */
+    pushal
+    pushfl
+    popl %eax
+    movl %eax, %ebx
+    xorl $0x00200000, %eax
+    pushl %eax
+    popfl
+    pushfl
+    popl %eax
+    cmpl %ebx, %eax
+    je CpuUnsupported
+    popal
+    call LoadGdt
+    ret
+
+LoadGdt:
+    /* Load Global Descriptor Table */
+    lgdt .GdtPointer
+    ret
+
+RunStage2:
+    /* Switch to protected mode and pass control to Stage 2 */
+    call BuildPageMap
+    call ParseExecutableHeader
+    pushl %eax
+    cli
+    movl %cr0, %eax
+    orl $0x01, %eax
+    movl %eax, %cr0
+    ljmp $0x08, $.Stage2ProtectedMode
+.code32
+.Stage2ProtectedMode:
+    /* Set segments and stack, then jump to Stage 2 */
+    movw $0x10, %ax
+    movw %ax, %ds
+    movw %ax, %es
+    movw %ax, %ss
+    xorw %ax, %ax
+    movw %ax, %fs
+    movw %ax, %gs
+    popl %eax
+    xorl %ebx, %ebx
+    xorl %ecx, %ecx
+    xorl %edx, %edx
+    xorl %esi, %esi
+    xorl %edi, %edi
+    xorl %ebp, %ebp
+    movl $0x1000, %ebx
+    movl %ebx, %cr3
+    movl %cr0, %ebx
+    orl $0x80000000, %ebx
+    movl %ebx, %cr0
+    jmp *%eax
+
+.code16
+.GdtDescriptor:
+    /* Global Descriptor Table */
+    .quad 0x0000000000000000
+    .quad 0x00CF9A000000FFFF
+    .quad 0x00CF92000000FFFF
+    .quad 0x00009E000000FFFF
+    .quad 0x000092000000FFFF
+
+.GdtPointer:
+    /* Pointer to Global Descriptor Table */
+    .word .GdtPointer - .GdtDescriptor - 1
+    .long .GdtDescriptor
+
+.Stage2FileName:
+    /* Name of Stage 2 executable file */
+    .ascii "BOOTIA32EFI"

boot/bootsect/mbrboot.S

@@ -4,6 +4,7 @@
  * FILE:            boot/bootsect/amd64/mbrboot.S
  * DESCRIPTION:     XT Boot Loader MBR boot code
  * DEVELOPERS:      Rafal Kupiec <belliash@codingworkshop.eu.org>
+ *                  Aiken Harris <aiken@codingworkshop.eu.org>
  */
 
 .text
@@ -41,7 +42,7 @@ RealStart:
     movw %ax, %ss
 
     /* Print welcome message */
-    leaw msgXtosBoot, %si
+    leaw .MsgXtosBoot, %si
     call Print
 
     /* Get BIOS boot drive and partition table offset */
@@ -90,19 +91,19 @@ PartitionFound:
 
 InvalidSignature:
     /* Invalid signature error */
-    leaw msgInvalidSignature, %si
+    leaw .MsgInvalidSignature, %si
     call Print
     jmp HaltSystem
 
 PartitionNotFound:
     /* Active partition not found error */
-    leaw msgPartitionNotFound, %si
+    leaw .MsgPartitionNotFound, %si
     call Print
     jmp HaltSystem
 
 VbrReadFail:
     /* VBR read failed error */
-    leaw msgVbrReadFail, %si
+    leaw .MsgVbrReadFail, %si
     call Print
     jmp HaltSystem
 
@@ -136,16 +137,16 @@ DonePrint:
     /* Storage for the LBA start */
     .long 0
 
-msgInvalidSignature:
+.MsgInvalidSignature:
     .asciz "Invalid partition signature!"
 
-msgPartitionNotFound:
+.MsgPartitionNotFound:
     .asciz "Bootable partition not found!"
 
-msgVbrReadFail:
+.MsgVbrReadFail:
     .asciz "VBR read failed!"
 
-msgXtosBoot:
+.MsgXtosBoot:
     .asciz "Starting XTOS boot loader...\r\n"
 
 /* Fill the rest of the MBR with zeros and add MBR signature at the end */

boot/xtldr/CMakeLists.txt

@@ -16,6 +16,7 @@ list(APPEND LIBXTLDR_SOURCE
 # Specify list of source code files
 list(APPEND XTLDR_SOURCE
     ${XTLDR_SOURCE_DIR}/arch/${ARCH}/memory.cc
+    ${XTLDR_SOURCE_DIR}/biosutil.cc
     ${XTLDR_SOURCE_DIR}/bootutil.cc
     ${XTLDR_SOURCE_DIR}/config.cc
     ${XTLDR_SOURCE_DIR}/console.cc
@@ -38,6 +39,9 @@ add_executable(xtldr ${XTLDR_SOURCE})
 # Add linker libraries
 target_link_libraries(xtldr libxtos)
 
+# Add linker options
+target_link_options(xtldr PRIVATE /ALIGN:512)
+
 # Set proper binary name and install target
 if(ARCH STREQUAL "i686")
 	set(BINARY_NAME "bootia32")
@@ -49,5 +53,6 @@ set_install_target(xtldr efi/boot)
 
 # Set loader entrypoint and subsystem
 set_entrypoint(xtldr "BlStartXtLoader")
+set_imagebase(xtldr ${BASEADDRESS_XTLDR})
 set_linker_map(xtldr TRUE)
 set_subsystem(xtldr efi_application)

boot/xtldr/biosutil.cc

@@ -0,0 +1,190 @@
+/**
+ * PROJECT:         ExectOS
+ * COPYRIGHT:       See COPYING.md in the top level directory
+ * FILE:            xtldr/biosutil.cc
+ * DESCRIPTION:     Legacy BIOS support
+ * DEVELOPERS:      Aiken Harris <harraiken91@gmail.com>
+ */
+
+#include <xtldr.hh>
+
+
+/**
+ * Clears the entire screen and moves the cursor to the top-left corner.
+ *
+ * @return This routine does not return any value.
+ *
+ * @since XT 1.0
+ */
+XTCDECL
+VOID
+BiosUtils::ClearScreen()
+{
+    VOLATILE PUSHORT VgaBuffer = (PUSHORT)0xB8000;
+    USHORT Blank;
+    UINT Index;
+
+    /* Set blank character */
+    Blank = (0x0F << 8) | L' ';
+
+    /* Fill the entire screen with blank characters */
+    for(Index = 0; Index < VgaWidth * VgaHeight; Index++)
+    {
+        VgaBuffer[Index] = Blank;
+    }
+
+    /* Reset cursor position to the top-left corner */
+    CursorX = 0;
+    CursorY = 0;
+
+    /* Update the hardware cursor position */
+    UpdateCursor();
+}
+
+/**
+ * Formats the input string and prints it out to the screen.
+ *
+ * @param Format
+ *        The formatted string that is to be written to the output.
+ *
+ * @param ...
+ *        Depending on the format string, this routine might expect a sequence of additional arguments.
+ *
+ * @return This routine does not return any value.
+ *
+ * @since XT 1.0
+ */
+XTCDECL
+VOID
+BiosUtils::Print(IN PCWSTR Format,
+                 IN ...)
+{
+    RTL_PRINT_CONTEXT PrintContext;
+    VA_LIST Arguments;
+
+    /* Initialise the print contexts */
+    PrintContext.WriteWideCharacter = PutChar;
+
+    /* Initialise the va_list */
+    VA_START(Arguments, Format);
+
+    /* Format and print the string to the stdout */
+    RTL::WideString::FormatWideString(&PrintContext, (PWCHAR)Format, Arguments);
+
+    /* Clean up the va_list */
+    VA_END(Arguments);
+}
+
+/**
+ * Writes a single wide character to the screen using legacy BIOS VGA text mode.
+ *
+ * @param Character
+ *        The wide character to be printed.
+ *
+ * @return This routine returns a status code.
+ *
+ * @since XT 1.0
+ */
+XTCDECL
+XTSTATUS
+BiosUtils::PutChar(IN WCHAR Character)
+{
+    VOLATILE PUSHORT VgaBuffer = (PUSHORT)0xB8000;
+    USHORT VgaCharacter;
+
+    /* Handle special characters */
+    if(Character == L'\n')
+    {
+        /* Move to the next line */
+        CursorX = 0;
+        CursorY++;
+    }
+    else if(Character == L'\r')
+    {
+        /* Move to the beginning of the current line */
+        CursorX = 0;
+    }
+    else
+    {
+        /* Print character and move cursor to the right */
+        VgaCharacter = (0x0F << 8) | (Character & 0xFF);
+        VgaBuffer[CursorY * VgaWidth + CursorX] = VgaCharacter;
+        CursorX++;
+    }
+
+    /* Handle moving to the next line if cursor is at the end of the line */
+    if(CursorX >= VgaWidth)
+    {
+        CursorX = 0;
+        CursorY++;
+    }
+
+    /* Handle scrolling if cursor is at the end of the screen */
+    if(CursorY >= VgaHeight)
+    {
+        ScrollScreen();
+        CursorY = VgaHeight - 1;
+    }
+
+    /* Update the hardware cursor position */
+    UpdateCursor();
+
+    /* Return success */
+    return STATUS_EFI_SUCCESS;
+}
+
+/**
+ * Scrolls the entire screen content up by one line and clears the last line.
+ *
+ * @return This routine does not return any value.
+ *
+ * @since XT 1.0
+ */
+XTCDECL
+VOID
+BiosUtils::ScrollScreen()
+{
+    VOLATILE PUSHORT VgaBuffer = (PUSHORT)0xB8000;
+    USHORT Blank;
+    UINT Index;
+
+    /* Set blank character */
+    Blank = (0x0F << 8) | L' ';
+
+    /* Move every line up by one */
+    for(Index = 0; Index < (VgaHeight - 1) * VgaWidth; Index++)
+    {
+        VgaBuffer[Index] = VgaBuffer[Index + VgaWidth];
+    }
+
+    /* Clear the last line */
+    for(Index = (VgaHeight - 1) * VgaWidth; Index < VgaHeight * VgaWidth; Index++)
+    {
+        VgaBuffer[Index] = Blank;
+    }
+}
+
+/**
+ * Updates the hardware cursor position on the screen.
+ *
+ * @return This routine does not return any value.
+ *
+ * @since XT 1.0
+ */
+XTCDECL
+VOID
+BiosUtils::UpdateCursor()
+{
+    USHORT Position;
+
+    /* Calculate cursor position */
+    Position = CursorY * VgaWidth + CursorX;
+
+    /* Send command to set the high byte of the cursor position */
+    HL::IoPort::WritePort8(0x3D4, 0x0E);
+    HL::IoPort::WritePort8(0x3D5, (UCHAR)((Position >> 8) & 0xFF));
+
+    /* Send command to set the low byte of the cursor position */
+    HL::IoPort::WritePort8(0x3D4, 0x0F);
+    HL::IoPort::WritePort8(0x3D5, (UCHAR)(Position & 0xFF));
+}

boot/xtldr/data.cc

@@ -10,6 +10,18 @@
 #include <xtldr.hh>
 
 
+/* Legacy BIOS cursor X position */
+USHORT BiosUtils::CursorX = 0;
+
+/* Legacy BIOS cursor Y position */
+USHORT BiosUtils::CursorY = 0;
+
+/* Legacy BIOS screen height */
+CONST USHORT BiosUtils::VgaHeight = 25;
+
+/* Legacy BIOS screen width */
+CONST USHORT BiosUtils::VgaWidth = 80;
+
 /* XT Boot Loader menu list */
 PLIST_ENTRY Configuration::BootMenuList = NULLPTR;
 

boot/xtldr/includes/xtldr.hh

@@ -15,6 +15,25 @@
 #include <libxtos.hh>
 
 
+class BiosUtils
+{
+    private:
+        STATIC USHORT CursorX;
+        STATIC USHORT CursorY;
+        STATIC CONST USHORT VgaHeight;
+        STATIC CONST USHORT VgaWidth;
+
+    public:
+        STATIC XTCDECL VOID ClearScreen();
+        STATIC XTCDECL VOID Print(IN PCWSTR Format,
+                                  IN ...);
+        STATIC XTCDECL XTSTATUS PutChar(IN WCHAR Character);
+
+    private:
+        STATIC XTCDECL VOID ScrollScreen();
+        STATIC XTCDECL VOID UpdateCursor();
+};
+
 class BootUtils
 {
     public:

boot/xtldr/xtldr.cc

@@ -236,6 +236,15 @@ BlStartXtLoader(IN EFI_HANDLE ImageHandle,
     PWCHAR Modules;
     EFI_STATUS Status;
 
+    /* Check if system is EFI-based and provided parameters are valid */
+    if(ImageHandle == NULLPTR || SystemTable == NULLPTR)
+    {
+        /* Invalid parameters, print error message using BIOS calls and hang */
+        BiosUtils::ClearScreen();
+        BiosUtils::Print(L"XTLDR requires EFI-based system!");
+        for(;;);
+    }
+
     /* Initialize XTLDR and */
     XtLoader::InitializeBootLoader(ImageHandle, SystemTable);
 

sdk/cmake/baseaddress/amd64.cmake

@@ -1,2 +1,3 @@
 # Set base addresses for all modules
+set(BASEADDRESS_XTLDR    0x000000000000F800)
 set(BASEADDRESS_XTOSKRNL 0x0000000140000000)

sdk/cmake/baseaddress/i686.cmake

@@ -1,2 +1,3 @@
 # Set base addresses for all modules
+set(BASEADDRESS_XTLDR    0x0000F800)
 set(BASEADDRESS_XTOSKRNL 0x00400000)

sdk/cmake/functions.cmake

@@ -64,11 +64,17 @@ function(compile_bootsector NAME SOURCE BASEADDR ENTRYPOINT)
     set(BINARY_NAME "${NAME}.bin")
     set(OBJECT_NAME "${NAME}.obj")
 
+    get_directory_property(DEFS COMPILE_DEFINITIONS)
+    foreach(def ${DEFS})
+        list(APPEND ASM_DEFS "-D${def}")
+    endforeach()
+
     add_custom_command(
         OUTPUT ${CMAKE_CURRENT_BINARY_DIR}/${BINARY_NAME}
         COMMAND ${CMAKE_ASM_COMPILER}
             /nologo
             --target=i386-none-elf
+            ${ASM_DEFS}
             -I${CMAKE_CURRENT_SOURCE_DIR}
             /Fo${CMAKE_CURRENT_BINARY_DIR}/${OBJECT_NAME}
             -c -- ${SOURCE}

sdk/xtdk/amd64/ketypes.h

@@ -272,11 +272,18 @@ typedef struct _KIDTENTRY
 {
     USHORT OffsetLow;
     USHORT Selector;
-    USHORT IstIndex:3;
-    USHORT Reserved0:5;
-    USHORT Type:5;
-    USHORT Dpl:2;
-    USHORT Present:1;
+    union
+    {
+        struct
+        {
+            USHORT IstIndex:3;
+            USHORT Reserved0:5;
+            USHORT Type:5;
+            USHORT Dpl:2;
+            USHORT Present:1;
+        };
+        USHORT Access;
+    };
     USHORT OffsetMiddle;
     ULONG OffsetHigh;
     ULONG Reserved1;

sdk/xtdk/amd64/mmtypes.h

@@ -25,11 +25,15 @@
 #define MM_PXE_BASE                                0xFFFFF6FB7DBED000ULL
 
 /* Page directory and page base addresses for 5-level paging */
-#define MM_PTE_LA57_BASE                           0xFFFF000000000000ULL
-#define MM_PDE_LA57_BASE                           0xFFFF010000000000ULL
-#define MM_PPE_LA57_BASE                           0xFFFF010800000000ULL
-#define MM_PXE_LA57_BASE                           0xFFFF010840000000ULL
-#define MM_P5E_LA57_BASE                           0xFFFF010840200000ULL
+#define MM_PTE_LA57_BASE                           0xFFED000000000000ULL
+#define MM_PDE_LA57_BASE                           0xFFEDF68000000000ULL
+#define MM_PPE_LA57_BASE                           0xFFEDF6FB40000000ULL
+#define MM_PXE_LA57_BASE                           0xFFEDF6FB7DA00000ULL
+#define MM_P5E_LA57_BASE                           0xFFEDF6FB7DBED000ULL
+
+/* Self map address */
+#define MM_PML4_SELF_MAP_ADDRESS                   0xFFFFF6FB7DBEDF68ULL
+#define MM_PML5_SELF_MAP_ADDRESS                   0xFFEDF6FB7DBEDF68ULL
 
 /* PTE shift values */
 #define MM_PTE_SHIFT                               3
@@ -45,6 +49,46 @@
 #define MM_PPE_PER_PAGE                            512
 #define MM_PXE_PER_PAGE                            512
 
+/* PTE state flags */
+#define MM_PTE_VALID                               0x0000000000000001ULL
+#define MM_PTE_ACCESSED                            0x0000000000000020ULL
+#define MM_PTE_DIRTY                               0x0000000000000040ULL
+
+/* PTE scope flags */
+#define MM_PTE_LARGE_PAGE                          0x0000000000000080ULL
+#define MM_PTE_GLOBAL                              0x0000000000000100ULL
+
+/* PTE access flags */
+#define MM_PTE_NOACCESS                            0x0000000000000000ULL
+#define MM_PTE_READONLY                            0x0000000000000000ULL
+#define MM_PTE_EXECUTE                             0x0000000000000000ULL
+#define MM_PTE_EXECUTE_READ                        0x0000000000000000ULL
+#define MM_PTE_READWRITE                           0x8000000000000002ULL
+#define MM_PTE_WRITECOPY                           0x8000000000000200ULL
+#define MM_PTE_EXECUTE_READWRITE                   0x0000000000000002ULL
+#define MM_PTE_EXECUTE_WRITECOPY                   0x0000000000000200ULL
+
+/* PTE protection flags */
+#define MM_PTE_NOEXECUTE                           0x8000000000000000ULL
+#define MM_PTE_PROTECT                             0x8000000000000612ULL
+
+/* PTE cache flags */
+#define MM_PTE_CACHE_ENABLE                        0x0000000000000000ULL
+#define MM_PTE_CACHE_DISABLE                       0x0000000000000010ULL
+#define MM_PTE_CACHE_WRITECOMBINED                 0x0000000000000010ULL
+#define MM_PTE_CACHE_WRITETHROUGH                  0x0000000000000008ULL
+
+/* PTE software flags */
+#define MM_PTE_COPY_ON_WRITE                       0x0000000000000200ULL
+#define MM_PTE_PROTOTYPE                           0x0000000000000400ULL
+#define MM_PTE_TRANSITION                          0x0000000000000800ULL
+
+/* PTE protection bits */
+#define MM_PTE_PROTECTION_BITS                     5
+
+/* Base address of the system page table */
+#define MM_SYSTEM_PTE_BASE                         KSEG0_BASE
+
 /* Minimum number of physical pages needed by the system */
 #define MM_MINIMUM_PHYSICAL_PAGES                  2048
 
@@ -99,6 +143,7 @@ typedef struct _HARDWARE_PTE
 typedef struct _MMPAGEMAP_INFO
 {
     BOOLEAN Xpa;
+    ULONGLONG EmptyPteList;
     ULONGLONG PteBase;
     ULONGLONG PdeBase;
     ULONGLONG PpeBase;
@@ -252,6 +297,7 @@ typedef struct _MMPFN
             USHORT ReferenceCount;
         } e2;
     } u3;
+    ULONG UsedPageTableEntries;
     union
     {
         MMPTE OriginalPte;
@@ -262,12 +308,11 @@ typedef struct _MMPFN
         ULONG_PTR EntireFrame;
         struct
         {
-            ULONG_PTR PteFrame:58;
+            ULONG_PTR PteFrame:57;
             ULONG_PTR InPageError:1;
             ULONG_PTR VerifierAllocation:1;
             ULONG_PTR AweAllocation:1;
-            ULONG_PTR LockCharged:1;
-            ULONG_PTR KernelStack:1;
+            ULONG_PTR Priority:3;
             ULONG_PTR MustBeCached:1;
         };
     } u4;

sdk/xtdk/i686/ketypes.h

@@ -58,12 +58,6 @@
 #define KIDT_ACCESS_RING0                 0x00
 #define KIDT_ACCESS_RING3                 0x60
 
-/* IDT gate types */
-#define KIDT_TASK                         0x05
-#define KIDT_CALL                         0x0C
-#define KIDT_INTERRUPT                    0x0E
-#define KIDT_TRAP                         0x0F
-
 /* TSS Offsets */
 #define KTSS_ESP0                         0x04
 #define KTSS_CR3                          0x1C
@@ -284,7 +278,18 @@ typedef struct _KIDTENTRY
 {
     USHORT Offset;
     USHORT Selector;
-    USHORT Access;
+    union
+    {
+        struct
+        {
+            UCHAR Reserved;
+            UCHAR Type:4;
+            UCHAR Flag:1;
+            UCHAR Dpl:2;
+            UCHAR Present:1;
+        };
+        USHORT Access;
+    };
     USHORT ExtendedOffset;
 } KIDTENTRY, *PKIDTENTRY;
 

sdk/xtdk/i686/mmtypes.h

@@ -35,6 +35,46 @@
 #define MM_PTE_LEGACY_SHIFT                        2
 #define MM_PDI_LEGACY_SHIFT                        22
 
+/* PTE state flags */
+#define MM_PTE_VALID                               0x00000001
+#define MM_PTE_ACCESSED                            0x00000020
+#define MM_PTE_DIRTY                               0x00000040
+
+/* PTE scope flags */
+#define MM_PTE_LARGE_PAGE                          0x00000080
+#define MM_PTE_GLOBAL                              0x00000100
+
+/* PTE access flags */
+#define MM_PTE_NOACCESS                            0x00000000
+#define MM_PTE_READONLY                            0x00000000
+#define MM_PTE_EXECUTE                             0x00000000
+#define MM_PTE_EXECUTE_READ                        0x00000000
+#define MM_PTE_READWRITE                           0x00000002
+#define MM_PTE_WRITECOPY                           0x00000200
+#define MM_PTE_EXECUTE_READWRITE                   0x00000002
+#define MM_PTE_EXECUTE_WRITECOPY                   0x00000200
+
+/* PTE protection flags */
+#define MM_PTE_NOEXECUTE                           0x00000000
+#define MM_PTE_PROTECT                             0x00000612
+
+/* PTE cache flags */
+#define MM_PTE_CACHE_ENABLE                        0x00000000
+#define MM_PTE_CACHE_DISABLE                       0x00000010
+#define MM_PTE_CACHE_WRITECOMBINED                 0x00000010
+#define MM_PTE_CACHE_WRITETHROUGH                  0x00000008
+
+/* PTE software flags */
+#define MM_PTE_COPY_ON_WRITE                       0x00000200
+#define MM_PTE_PROTOTYPE                           0x00000400
+#define MM_PTE_TRANSITION                          0x00000800
+
+/* PTE protection bits */
+#define MM_PTE_PROTECTION_BITS                     5
+
+/* Base address of the system page table */
+#define MM_SYSTEM_PTE_BASE                         NULLPTR
+
 /* Minimum number of physical pages needed by the system */
 #define MM_MINIMUM_PHYSICAL_PAGES                  1100
 
@@ -115,6 +155,7 @@ typedef union _HARDWARE_PTE
 typedef struct _MMPAGEMAP_INFO
 {
     BOOLEAN Xpa;
+    ULONG EmptyPteList;
     ULONG PteBase;
     ULONG PdeBase;
     ULONG PdiShift;
@@ -202,11 +243,11 @@ typedef union _MMPML2_PTE
 {
     ULONG Long;
     HARDWARE_PTE Flush;
-    MMPML2_PTE_HARDWARE Hard;
-    MMPML2_PTE_PROTOTYPE Proto;
-    MMPML2_PTE_SOFTWARE Soft;
-    MMPML2_PTE_TRANSITION Trans;
-    MMPML2_PTE_SUBSECTION Subsect;
+    MMPML2_PTE_HARDWARE Hardware;
+    MMPML2_PTE_PROTOTYPE Prototype;
+    MMPML2_PTE_SOFTWARE Software;
+    MMPML2_PTE_TRANSITION Transition;
+    MMPML2_PTE_SUBSECTION Subsection;
     MMPML2_PTE_LIST List;
 } MMPML2_PTE, *PMMPML2_PTE;
 

sdk/xtdk/ketypes.h

@@ -150,21 +150,23 @@ typedef enum _KTHREAD_STATE
 typedef enum _KSPIN_LOCK_QUEUE_LEVEL
 {
     DispatcherLock,
-    UnusedSpareLock,
+    ExpansionLock,
     PfnLock,
     SystemSpaceLock,
     VacbLock,
     MasterLock,
-    NonPagedPoolLock,
+    NonPagedAllocPoolLock,
     IoCancelLock,
     WorkQueueLock,
     IoVpbLock,
     IoDatabaseLock,
     IoCompletionLock,
-    FsStructLock,
+    FileSystemLock,
     AfdWorkQueueLock,
     BcbLock,
-    MmNonPagedPoolLock,
+    NonPagedPoolLock,
+    ReservedSystemLock,
+    TimerTableLock,
     MaximumLock
 } KSPIN_LOCK_QUEUE_LEVEL, *PKSPIN_LOCK_QUEUE_LEVEL;
 

sdk/xtdk/mmtypes.h

@@ -13,6 +13,27 @@
 #include ARCH_HEADER(xtstruct.h)
 
 
+/* Memory manager page lists */
+typedef enum _MMPAGELISTS
+{
+   ZeroedPageList = 0,
+   FreePageList = 1,
+   StandbyPageList = 2,
+   ModifiedPageList = 3,
+   ModifiedNoWritePageList = 4,
+   BadPageList = 5,
+   ActiveAndValid = 6,
+   TransitionPage = 7
+} MMPAGELISTS, *PMMPAGELISTS;
+
+/* Page table pool types */
+typedef enum _MMSYSTEM_PTE_POOL_TYPE
+{
+    SystemPteSpace,
+    NonPagedPoolExpansion,
+    MaximumPtePoolTypes
+} MMSYSTEM_PTE_POOL_TYPE, *PMMSYSTEM_PTE_POOL_TYPE;
+
 /* Page map routines structure definition */
 typedef CONST STRUCT _CMMPAGEMAP_ROUTINES
 {
@@ -45,4 +66,13 @@ typedef struct _MMPFNENTRY
     USHORT ParityError:1;
 } MMPFNENTRY, *PMMPFNENTRY;
 
+/* Page Frame List structure definition */
+typedef struct _MMPFNLIST
+{
+    PFN_NUMBER Total;
+    MMPAGELISTS ListName;
+    PFN_NUMBER Flink;
+    PFN_NUMBER Blink;
+} MMPFNLIST, *PMMPFNLIST;
+
 #endif /* __XTDK_MMTYPES_H */

sdk/xtdk/xtbase.h

@@ -29,6 +29,9 @@ typedef UCHAR KRUNLEVEL, *PKRUNLEVEL;
 /* Spin locks synchronization mechanism */
 typedef ULONG_PTR KSPIN_LOCK, *PKSPIN_LOCK;
 
+/* Page Frame Number count */
+typedef ULONG PFN_COUNT;
+
 /* Page Frame Number */
 typedef ULONG_PTR PFN_NUMBER, *PPFN_NUMBER;
 

sdk/xtdk/xtcompat.h

@@ -12,8 +12,9 @@
 
 #ifdef __cplusplus
     /* C++ definitions */
-    #define XTCLINK         extern "C"
     #define NULLPTR         nullptr
+    #define VIRTUAL         virtual
+    #define XTCLINK         extern "C"
 
     /* C++ boolean type */
     typedef bool BOOLEAN, *PBOOLEAN;
@@ -24,8 +25,9 @@
     typedef wchar_t wchar;
 #else
     /* C definitions */
-    #define XTCLINK
     #define NULLPTR         ((void *)0)
+    #define VIRTUAL
+    #define XTCLINK
 
     /* C boolean type */
     typedef enum _BOOLEAN

sdk/xtdk/xtstruct.h

@@ -48,6 +48,8 @@ typedef enum _KTHREAD_STATE KTHREAD_STATE, *PKTHREAD_STATE;
 typedef enum _KTIMER_TYPE KTIMER_TYPE, *PKTIMER_TYPE;
 typedef enum _KUBSAN_DATA_TYPE KUBSAN_DATA_TYPE, *PKUBSAN_DATA_TYPE;
 typedef enum _LOADER_MEMORY_TYPE LOADER_MEMORY_TYPE, *PLOADER_MEMORY_TYPE;
+typedef enum _MMPAGELISTS MMPAGELISTS, *PMMPAGELISTS;
+typedef enum _MMSYSTEM_PTE_POOL_TYPE MMSYSTEM_PTE_POOL_TYPE, *PMMSYSTEM_PTE_POOL_TYPE;
 typedef enum _MODE MODE, *PMODE;
 typedef enum _RTL_VARIABLE_TYPE RTL_VARIABLE_TYPE, *PRTL_VARIABLE_TYPE;
 typedef enum _SYSTEM_FIRMWARE_TYPE SYSTEM_FIRMWARE_TYPE, *PSYSTEM_FIRMWARE_TYPE;
@@ -275,6 +277,7 @@ typedef struct _LOADER_MEMORY_DESCRIPTOR LOADER_MEMORY_DESCRIPTOR, *PLOADER_MEMO
 typedef struct _M128 M128, *PM128;
 typedef struct _MMCOLOR_TABLES MMCOLOR_TABLES, *PMMCOLOR_TABLES;
 typedef struct _MMPFNENTRY MMPFNENTRY, *PMMPFNENTRY;
+typedef struct _MMPFNLIST MMPFNLIST, *PMMPFNLIST;
 typedef struct _PCAT_FIRMWARE_INFORMATION PCAT_FIRMWARE_INFORMATION, *PPCAT_FIRMWARE_INFORMATION;
 typedef struct _PCI_BRIDGE_CONTROL_REGISTER PCI_BRIDGE_CONTROL_REGISTER, *PPCI_BRIDGE_CONTROL_REGISTER;
 typedef struct _PCI_COMMON_CONFIG PCI_COMMON_CONFIG, *PPCI_COMMON_CONFIG;

xtoskrnl/CMakeLists.txt

@@ -82,11 +82,12 @@ add_library(libxtos ${XTOSKRNL_SOURCE})
 
 # Link kernel executable
 add_executable(xtoskrnl
-               ${XTOSKRNL_SOURCE}
                ${CMAKE_CURRENT_BINARY_DIR}/xtoskrnl.def)
 
 # Add linker libraries
-target_link_libraries(xtoskrnl)
+target_link_libraries(xtoskrnl
+                      PRIVATE
+                      libxtos)
 
 # Set proper binary name and install target
 set_target_properties(xtoskrnl PROPERTIES SUFFIX .exe)

xtoskrnl/README.md

@@ -4,6 +4,18 @@ within the XTOS kernel space. It is responsible for various core services, such
 management, and process scheduling. The kernel contains the scheduler (sometimes referred to as the Dispatcher), the
 cache, object, and memory managers, the security manager, and other executive components described below.
 
+
+## Kernel Parameters
+Kernel parameters are XTOS boot-time options used to ensure proper initialization and handling of hardware peripherals.
+These parameters can be configured either temporarily by editing the boot entry in the bootloader’s selection menu, or
+permanently by modifying the XTLDR configuration file.
+
+The following is a consolidated list of available kernel parameters:
+ * **NOXPA**: Disables PAE or LA57 support, depending on the CPU architecture. This parameter is handled by the
+   bootloader, which configures paging and selects the appropriate Page Map Level (PML) before transferring control to
+   the kernel.
+
+## Source Code
 The source code of the kernel is organized into subsystem-specific directories. Each directory name also defines the
 corresponding C++ namespace in which the subsystem's classes and routines reside. These subsystems include:
 
@@ -68,8 +80,8 @@ routine:
 For all C++ code inside the kernel the naming model has evolved. Consider the **KE::KThread::InitializeThread()**
 routine:
  * **KE** - The namespace replaces the prefix and indicates the subsystem. Namespaces are written in uppercase and no
-            longer use the trailing p for private routines, because classes use C++ visibility to control access.
+   longer use the trailing p for private routines, because classes use C++ visibility to control access.
  * **KThread** - Within each namespace, related functionality is grouped into classes, which encapsulate variables and
-                 methods.
+   methods.
  * **InitializeThread** - Method names follow the `<Operation><Object>` pattern.
  

xtoskrnl/ar/amd64/procsup.cc

@@ -249,34 +249,34 @@ AR::ProcSup::InitializeIdt(IN PKPROCESSOR_BLOCK ProcessorBlock)
     for(Vector = 0; Vector < IDT_ENTRIES; Vector++)
     {
         /* Set the IDT to handle unexpected interrupts */
-        SetIdtGate(ProcessorBlock->IdtBase, Vector, (PVOID)ArTrap0xFF, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0);
+        SetIdtGate(ProcessorBlock->IdtBase, Vector, (PVOID)ArTrap0xFF, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0, AMD64_INTERRUPT_GATE);
     }
 
     /* Setup IDT handlers for known interrupts and traps */
-    SetIdtGate(ProcessorBlock->IdtBase, 0x00, (PVOID)ArTrap0x00, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0);
-    SetIdtGate(ProcessorBlock->IdtBase, 0x01, (PVOID)ArTrap0x01, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0);
-    SetIdtGate(ProcessorBlock->IdtBase, 0x02, (PVOID)ArTrap0x02, KGDT_R0_CODE, KIDT_IST_PANIC, KIDT_ACCESS_RING0);
-    SetIdtGate(ProcessorBlock->IdtBase, 0x03, (PVOID)ArTrap0x03, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING3);
-    SetIdtGate(ProcessorBlock->IdtBase, 0x04, (PVOID)ArTrap0x04, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING3);
-    SetIdtGate(ProcessorBlock->IdtBase, 0x05, (PVOID)ArTrap0x05, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0);
-    SetIdtGate(ProcessorBlock->IdtBase, 0x06, (PVOID)ArTrap0x06, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0);
-    SetIdtGate(ProcessorBlock->IdtBase, 0x07, (PVOID)ArTrap0x07, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0);
-    SetIdtGate(ProcessorBlock->IdtBase, 0x08, (PVOID)ArTrap0x08, KGDT_R0_CODE, KIDT_IST_PANIC, KIDT_ACCESS_RING0);
-    SetIdtGate(ProcessorBlock->IdtBase, 0x09, (PVOID)ArTrap0x09, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0);
-    SetIdtGate(ProcessorBlock->IdtBase, 0x0A, (PVOID)ArTrap0x0A, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0);
-    SetIdtGate(ProcessorBlock->IdtBase, 0x0B, (PVOID)ArTrap0x0B, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0);
-    SetIdtGate(ProcessorBlock->IdtBase, 0x0C, (PVOID)ArTrap0x0C, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0);
-    SetIdtGate(ProcessorBlock->IdtBase, 0x0D, (PVOID)ArTrap0x0D, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0);
-    SetIdtGate(ProcessorBlock->IdtBase, 0x0E, (PVOID)ArTrap0x0E, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0);
-    SetIdtGate(ProcessorBlock->IdtBase, 0x10, (PVOID)ArTrap0x10, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0);
-    SetIdtGate(ProcessorBlock->IdtBase, 0x11, (PVOID)ArTrap0x11, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0);
-    SetIdtGate(ProcessorBlock->IdtBase, 0x12, (PVOID)ArTrap0x12, KGDT_R0_CODE, KIDT_IST_MCA, KIDT_ACCESS_RING0);
-    SetIdtGate(ProcessorBlock->IdtBase, 0x13, (PVOID)ArTrap0x13, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0);
-    SetIdtGate(ProcessorBlock->IdtBase, 0x1F, (PVOID)ArTrap0x1F, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0);
-    SetIdtGate(ProcessorBlock->IdtBase, 0x2C, (PVOID)ArTrap0x2C, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING3);
-    SetIdtGate(ProcessorBlock->IdtBase, 0x2D, (PVOID)ArTrap0x2D, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING3);
-    SetIdtGate(ProcessorBlock->IdtBase, 0x2F, (PVOID)ArTrap0x2F, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0);
-    SetIdtGate(ProcessorBlock->IdtBase, 0xE1, (PVOID)ArTrap0xE1, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0);
+    SetIdtGate(ProcessorBlock->IdtBase, 0x00, (PVOID)ArTrap0x00, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0, AMD64_TRAP_GATE);
+    SetIdtGate(ProcessorBlock->IdtBase, 0x01, (PVOID)ArTrap0x01, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0, AMD64_TRAP_GATE);
+    SetIdtGate(ProcessorBlock->IdtBase, 0x02, (PVOID)ArTrap0x02, KGDT_R0_CODE, KIDT_IST_PANIC, KIDT_ACCESS_RING0, AMD64_INTERRUPT_GATE);
+    SetIdtGate(ProcessorBlock->IdtBase, 0x03, (PVOID)ArTrap0x03, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING3, AMD64_TRAP_GATE);
+    SetIdtGate(ProcessorBlock->IdtBase, 0x04, (PVOID)ArTrap0x04, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING3, AMD64_TRAP_GATE);
+    SetIdtGate(ProcessorBlock->IdtBase, 0x05, (PVOID)ArTrap0x05, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0, AMD64_TRAP_GATE);
+    SetIdtGate(ProcessorBlock->IdtBase, 0x06, (PVOID)ArTrap0x06, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0, AMD64_TRAP_GATE);
+    SetIdtGate(ProcessorBlock->IdtBase, 0x07, (PVOID)ArTrap0x07, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0, AMD64_TRAP_GATE);
+    SetIdtGate(ProcessorBlock->IdtBase, 0x08, (PVOID)ArTrap0x08, KGDT_R0_CODE, KIDT_IST_PANIC, KIDT_ACCESS_RING0, AMD64_TRAP_GATE);
+    SetIdtGate(ProcessorBlock->IdtBase, 0x09, (PVOID)ArTrap0x09, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0, AMD64_TRAP_GATE);
+    SetIdtGate(ProcessorBlock->IdtBase, 0x0A, (PVOID)ArTrap0x0A, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0, AMD64_TRAP_GATE);
+    SetIdtGate(ProcessorBlock->IdtBase, 0x0B, (PVOID)ArTrap0x0B, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0, AMD64_TRAP_GATE);
+    SetIdtGate(ProcessorBlock->IdtBase, 0x0C, (PVOID)ArTrap0x0C, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0, AMD64_TRAP_GATE);
+    SetIdtGate(ProcessorBlock->IdtBase, 0x0D, (PVOID)ArTrap0x0D, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0, AMD64_TRAP_GATE);
+    SetIdtGate(ProcessorBlock->IdtBase, 0x0E, (PVOID)ArTrap0x0E, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0, AMD64_TRAP_GATE);
+    SetIdtGate(ProcessorBlock->IdtBase, 0x10, (PVOID)ArTrap0x10, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0, AMD64_TRAP_GATE);
+    SetIdtGate(ProcessorBlock->IdtBase, 0x11, (PVOID)ArTrap0x11, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0, AMD64_TRAP_GATE);
+    SetIdtGate(ProcessorBlock->IdtBase, 0x12, (PVOID)ArTrap0x12, KGDT_R0_CODE, KIDT_IST_MCA, KIDT_ACCESS_RING0, AMD64_TRAP_GATE);
+    SetIdtGate(ProcessorBlock->IdtBase, 0x13, (PVOID)ArTrap0x13, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0, AMD64_TRAP_GATE);
+    SetIdtGate(ProcessorBlock->IdtBase, 0x1F, (PVOID)ArTrap0x1F, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0, AMD64_INTERRUPT_GATE);
+    SetIdtGate(ProcessorBlock->IdtBase, 0x2C, (PVOID)ArTrap0x2C, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING3, AMD64_TRAP_GATE);
+    SetIdtGate(ProcessorBlock->IdtBase, 0x2D, (PVOID)ArTrap0x2D, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING3, AMD64_TRAP_GATE);
+    SetIdtGate(ProcessorBlock->IdtBase, 0x2F, (PVOID)ArTrap0x2F, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0, AMD64_INTERRUPT_GATE);
+    SetIdtGate(ProcessorBlock->IdtBase, 0xE1, (PVOID)ArTrap0xE1, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0, AMD64_INTERRUPT_GATE);
 }
 
 /**
@@ -636,6 +636,9 @@ AR::ProcSup::SetGdtEntryBase(IN PKGDTENTRY Gdt,
  * @param Access
  *        Supplies the gate access rights.
  *
+ * @param Type
+ *        Supplies the gate type.
+ *
  * @return This routine does not return any value.
  *
  * @since XT 1.0
@@ -647,15 +650,22 @@ AR::ProcSup::SetIdtGate(IN PKIDTENTRY Idt,
                         IN PVOID Handler,
                         IN USHORT Selector,
                         IN USHORT Ist,
-                        IN USHORT Access)
+                        IN USHORT Dpl,
+                        IN USHORT Type)
 {
-    /* Setup the gate */
+    /* Set the handler's address */
     Idt[Vector].OffsetLow = ((ULONG_PTR)Handler & 0xFFFF);
     Idt[Vector].OffsetMiddle = (((ULONG_PTR)Handler >> 16) & 0xFFFF);
     Idt[Vector].OffsetHigh = (ULONG_PTR)Handler >> 32;
-    Idt[Vector].Dpl = Access;
+
+    /* Set the code segment selector */
+    Idt[Vector].Selector = Selector;
+
+    /* Initialize the gate's attributes and flags */
+    Idt[Vector].Access = 0;
+    Idt[Vector].Dpl = Dpl;
     Idt[Vector].IstIndex = Ist;
     Idt[Vector].Present = 1;
-    Idt[Vector].Selector = Selector;
-    Idt[Vector].Type = 0xE;
+    Idt[Vector].Reserved1 = 0;
+    Idt[Vector].Type = Type;
 }

xtoskrnl/ar/i686/procsup.cc

@@ -242,34 +242,34 @@ AR::ProcSup::InitializeIdt(IN PKPROCESSOR_BLOCK ProcessorBlock)
     for(Vector = 0; Vector < IDT_ENTRIES; Vector++)
     {
         /* Set the IDT to handle unexpected interrupts */
-        SetIdtGate(ProcessorBlock->IdtBase, Vector, (PVOID)ArTrap0xFF, KGDT_R0_CODE, 0, KIDT_INTERRUPT | KIDT_ACCESS_RING0);
+        SetIdtGate(ProcessorBlock->IdtBase, Vector, (PVOID)ArTrap0xFF, KGDT_R0_CODE, 0, KIDT_ACCESS_RING0, I686_INTERRUPT_GATE);
     }
 
     /* Setup IDT handlers for known interrupts and traps */
-    SetIdtGate(ProcessorBlock->IdtBase, 0x00, (PVOID)ArTrap0x00, KGDT_R0_CODE, 0, KIDT_INTERRUPT | KIDT_ACCESS_RING0);
-    SetIdtGate(ProcessorBlock->IdtBase, 0x01, (PVOID)ArTrap0x01, KGDT_R0_CODE, 0, KIDT_INTERRUPT | KIDT_ACCESS_RING0);
-    SetIdtGate(ProcessorBlock->IdtBase, 0x02, (PVOID)ArTrap0x02, KGDT_R0_CODE, 0, KIDT_INTERRUPT | KIDT_ACCESS_RING0);
-    SetIdtGate(ProcessorBlock->IdtBase, 0x03, (PVOID)ArTrap0x03, KGDT_R0_CODE, 0, KIDT_INTERRUPT | KIDT_ACCESS_RING3);
-    SetIdtGate(ProcessorBlock->IdtBase, 0x04, (PVOID)ArTrap0x04, KGDT_R0_CODE, 0, KIDT_INTERRUPT | KIDT_ACCESS_RING3);
-    SetIdtGate(ProcessorBlock->IdtBase, 0x05, (PVOID)ArTrap0x05, KGDT_R0_CODE, 0, KIDT_INTERRUPT | KIDT_ACCESS_RING0);
-    SetIdtGate(ProcessorBlock->IdtBase, 0x06, (PVOID)ArTrap0x06, KGDT_R0_CODE, 0, KIDT_INTERRUPT | KIDT_ACCESS_RING0);
-    SetIdtGate(ProcessorBlock->IdtBase, 0x07, (PVOID)ArTrap0x07, KGDT_R0_CODE, 0, KIDT_INTERRUPT | KIDT_ACCESS_RING0);
-    SetIdtGate(ProcessorBlock->IdtBase, 0x08, (PVOID)ArTrap0x08, KGDT_R0_CODE, 0, KIDT_INTERRUPT | KIDT_ACCESS_RING0);
-    SetIdtGate(ProcessorBlock->IdtBase, 0x09, (PVOID)ArTrap0x09, KGDT_R0_CODE, 0, KIDT_INTERRUPT | KIDT_ACCESS_RING0);
-    SetIdtGate(ProcessorBlock->IdtBase, 0x0A, (PVOID)ArTrap0x0A, KGDT_R0_CODE, 0, KIDT_INTERRUPT | KIDT_ACCESS_RING0);
-    SetIdtGate(ProcessorBlock->IdtBase, 0x0B, (PVOID)ArTrap0x0B, KGDT_R0_CODE, 0, KIDT_INTERRUPT | KIDT_ACCESS_RING0);
-    SetIdtGate(ProcessorBlock->IdtBase, 0x0C, (PVOID)ArTrap0x0C, KGDT_R0_CODE, 0, KIDT_INTERRUPT | KIDT_ACCESS_RING0);
-    SetIdtGate(ProcessorBlock->IdtBase, 0x0D, (PVOID)ArTrap0x0D, KGDT_R0_CODE, 0, KIDT_INTERRUPT | KIDT_ACCESS_RING0);
-    SetIdtGate(ProcessorBlock->IdtBase, 0x0E, (PVOID)ArTrap0x0E, KGDT_R0_CODE, 0, KIDT_INTERRUPT | KIDT_ACCESS_RING0);
-    SetIdtGate(ProcessorBlock->IdtBase, 0x10, (PVOID)ArTrap0x10, KGDT_R0_CODE, 0, KIDT_INTERRUPT | KIDT_ACCESS_RING0);
-    SetIdtGate(ProcessorBlock->IdtBase, 0x11, (PVOID)ArTrap0x11, KGDT_R0_CODE, 0, KIDT_INTERRUPT | KIDT_ACCESS_RING0);
-    SetIdtGate(ProcessorBlock->IdtBase, 0x12, (PVOID)ArTrap0x12, KGDT_R0_CODE, 0, KIDT_INTERRUPT | KIDT_ACCESS_RING0);
-    SetIdtGate(ProcessorBlock->IdtBase, 0x13, (PVOID)ArTrap0x13, KGDT_R0_CODE, 0, KIDT_INTERRUPT | KIDT_ACCESS_RING0);
-    SetIdtGate(ProcessorBlock->IdtBase, 0x2A, (PVOID)ArTrap0x2A, KGDT_R0_CODE, 0, KIDT_INTERRUPT | KIDT_ACCESS_RING3);
-    SetIdtGate(ProcessorBlock->IdtBase, 0x2B, (PVOID)ArTrap0x2B, KGDT_R0_CODE, 0, KIDT_INTERRUPT | KIDT_ACCESS_RING3);
-    SetIdtGate(ProcessorBlock->IdtBase, 0x2C, (PVOID)ArTrap0x2C, KGDT_R0_CODE, 0, KIDT_INTERRUPT | KIDT_ACCESS_RING3);
-    SetIdtGate(ProcessorBlock->IdtBase, 0x2D, (PVOID)ArTrap0x2D, KGDT_R0_CODE, 0, KIDT_INTERRUPT | KIDT_ACCESS_RING3);
-    SetIdtGate(ProcessorBlock->IdtBase, 0x2E, (PVOID)ArTrap0x2E, KGDT_R0_CODE, 0, KIDT_INTERRUPT | KIDT_ACCESS_RING3);
+    SetIdtGate(ProcessorBlock->IdtBase, 0x00, (PVOID)ArTrap0x00, KGDT_R0_CODE, 0, KIDT_ACCESS_RING0, I686_TRAP_GATE);
+    SetIdtGate(ProcessorBlock->IdtBase, 0x01, (PVOID)ArTrap0x01, KGDT_R0_CODE, 0, KIDT_ACCESS_RING0, I686_TRAP_GATE);
+    SetIdtGate(ProcessorBlock->IdtBase, 0x02, (PVOID)ArTrap0x02, KGDT_R0_CODE, 0, KIDT_ACCESS_RING0, I686_INTERRUPT_GATE);
+    SetIdtGate(ProcessorBlock->IdtBase, 0x03, (PVOID)ArTrap0x03, KGDT_R0_CODE, 0, KIDT_ACCESS_RING3, I686_TRAP_GATE);
+    SetIdtGate(ProcessorBlock->IdtBase, 0x04, (PVOID)ArTrap0x04, KGDT_R0_CODE, 0, KIDT_ACCESS_RING3, I686_TRAP_GATE);
+    SetIdtGate(ProcessorBlock->IdtBase, 0x05, (PVOID)ArTrap0x05, KGDT_R0_CODE, 0, KIDT_ACCESS_RING0, I686_TRAP_GATE);
+    SetIdtGate(ProcessorBlock->IdtBase, 0x06, (PVOID)ArTrap0x06, KGDT_R0_CODE, 0, KIDT_ACCESS_RING0, I686_TRAP_GATE);
+    SetIdtGate(ProcessorBlock->IdtBase, 0x07, (PVOID)ArTrap0x07, KGDT_R0_CODE, 0, KIDT_ACCESS_RING0, I686_TRAP_GATE);
+    SetIdtGate(ProcessorBlock->IdtBase, 0x08, (PVOID)ArTrap0x08, KGDT_R0_CODE, 0, KIDT_ACCESS_RING0, I686_TRAP_GATE);
+    SetIdtGate(ProcessorBlock->IdtBase, 0x09, (PVOID)ArTrap0x09, KGDT_R0_CODE, 0, KIDT_ACCESS_RING0, I686_TRAP_GATE);
+    SetIdtGate(ProcessorBlock->IdtBase, 0x0A, (PVOID)ArTrap0x0A, KGDT_R0_CODE, 0, KIDT_ACCESS_RING0, I686_TRAP_GATE);
+    SetIdtGate(ProcessorBlock->IdtBase, 0x0B, (PVOID)ArTrap0x0B, KGDT_R0_CODE, 0, KIDT_ACCESS_RING0, I686_TRAP_GATE);
+    SetIdtGate(ProcessorBlock->IdtBase, 0x0C, (PVOID)ArTrap0x0C, KGDT_R0_CODE, 0, KIDT_ACCESS_RING0, I686_TRAP_GATE);
+    SetIdtGate(ProcessorBlock->IdtBase, 0x0D, (PVOID)ArTrap0x0D, KGDT_R0_CODE, 0, KIDT_ACCESS_RING0, I686_TRAP_GATE);
+    SetIdtGate(ProcessorBlock->IdtBase, 0x0E, (PVOID)ArTrap0x0E, KGDT_R0_CODE, 0, KIDT_ACCESS_RING0, I686_TRAP_GATE);
+    SetIdtGate(ProcessorBlock->IdtBase, 0x10, (PVOID)ArTrap0x10, KGDT_R0_CODE, 0, KIDT_ACCESS_RING0, I686_TRAP_GATE);
+    SetIdtGate(ProcessorBlock->IdtBase, 0x11, (PVOID)ArTrap0x11, KGDT_R0_CODE, 0, KIDT_ACCESS_RING0, I686_TRAP_GATE);
+    SetIdtGate(ProcessorBlock->IdtBase, 0x12, (PVOID)ArTrap0x12, KGDT_R0_CODE, 0, KIDT_ACCESS_RING0, I686_TRAP_GATE);
+    SetIdtGate(ProcessorBlock->IdtBase, 0x13, (PVOID)ArTrap0x13, KGDT_R0_CODE, 0, KIDT_ACCESS_RING0, I686_TRAP_GATE);
+    SetIdtGate(ProcessorBlock->IdtBase, 0x2A, (PVOID)ArTrap0x2A, KGDT_R0_CODE, 0, KIDT_ACCESS_RING3, I686_TRAP_GATE);
+    SetIdtGate(ProcessorBlock->IdtBase, 0x2B, (PVOID)ArTrap0x2B, KGDT_R0_CODE, 0, KIDT_ACCESS_RING3, I686_TRAP_GATE);
+    SetIdtGate(ProcessorBlock->IdtBase, 0x2C, (PVOID)ArTrap0x2C, KGDT_R0_CODE, 0, KIDT_ACCESS_RING3, I686_TRAP_GATE);
+    SetIdtGate(ProcessorBlock->IdtBase, 0x2D, (PVOID)ArTrap0x2D, KGDT_R0_CODE, 0, KIDT_ACCESS_RING3, I686_TRAP_GATE);
+    SetIdtGate(ProcessorBlock->IdtBase, 0x2E, (PVOID)ArTrap0x2E, KGDT_R0_CODE, 0, KIDT_ACCESS_RING3, I686_TRAP_GATE);
 }
 
 /**
@@ -656,6 +656,9 @@ AR::ProcSup::SetGdtEntryBase(IN PKGDTENTRY Gdt,
  * @param Access
  *        Supplies the gate access rights.
  *
+ * @param Type
+ *        Supplies the gate type.
+ *
  * @return This routine does not return any value.
  *
  * @since XT 1.0
@@ -667,13 +670,21 @@ AR::ProcSup::SetIdtGate(IN PKIDTENTRY Idt,
                         IN PVOID Handler,
                         IN USHORT Selector,
                         IN USHORT Ist,
-                        IN USHORT Access)
+                        IN USHORT Dpl,
+                        IN USHORT Type)
 {
-    /* Setup the gate */
+    /* Set the handler's address */
     Idt[Vector].Offset = (USHORT)((ULONG)Handler & 0xFFFF);
     Idt[Vector].ExtendedOffset = (USHORT)((ULONG)Handler >> 16);
-    Idt[Vector].Access = 0x8000 | (Access << 8);
+
+    /* Set the code segment selector */
     Idt[Vector].Selector = Selector;
+
+    /* Initialize the gate's attributes and flags */
+    Idt[Vector].Access = 0;
+    Idt[Vector].Dpl = Dpl;
+    Idt[Vector].Present = 1;
+    Idt[Vector].Type = Type;
 }
 
 /**

xtoskrnl/includes/ar/amd64/procsup.hh

@@ -67,7 +67,8 @@ namespace AR
                                          IN PVOID Handler,
                                          IN USHORT Selector,
                                          IN USHORT Ist,
-                                         IN USHORT Access);
+                                         IN USHORT Dpl,
+                                         IN USHORT Type);
     };
 }
 

xtoskrnl/includes/ar/i686/procsup.hh

@@ -72,7 +72,8 @@ namespace AR
                                          IN PVOID Handler,
                                          IN USHORT Selector,
                                          IN USHORT Ist,
-                                         IN USHORT Access);
+                                         IN USHORT Dpl,
+                                         IN USHORT Type);
             STATIC XTAPI VOID SetNonMaskableInterruptTssEntry(IN PKPROCESSOR_BLOCK ProcessorBlock,
                                                               IN PVOID KernelFaultStack);
 

xtoskrnl/includes/ke/runlevel.hh

@@ -22,6 +22,48 @@ namespace KE
             STATIC XTFASTCALL VOID LowerRunLevel(IN KRUNLEVEL RunLevel);
             STATIC XTFASTCALL KRUNLEVEL RaiseRunLevel(IN KRUNLEVEL RunLevel);
     };
+
+    class LowerRunLevel
+    {
+        private:
+            KRUNLEVEL PreviousRunLevel;
+
+        public:
+            LowerRunLevel(KRUNLEVEL RunLevel)
+            {
+                PreviousRunLevel = KE::RunLevel::GetCurrentRunLevel();
+                KE::RunLevel::LowerRunLevel(RunLevel);
+            }
+
+            ~LowerRunLevel()
+            {
+                KE::RunLevel::RaiseRunLevel(PreviousRunLevel);
+            }
+
+            LowerRunLevel(const LowerRunLevel&) = delete;
+            LowerRunLevel& operator=(const LowerRunLevel&) = delete;
+    };
+
+    class RaiseRunLevel
+    {
+        private:
+            KRUNLEVEL PreviousRunLevel;
+
+        public:
+            RaiseRunLevel(KRUNLEVEL RunLevel)
+            {
+                PreviousRunLevel = KE::RunLevel::GetCurrentRunLevel();
+                KE::RunLevel::RaiseRunLevel(RunLevel);
+            }
+
+            ~RaiseRunLevel()
+            {
+                KE::RunLevel::LowerRunLevel(PreviousRunLevel);
+            }
+
+            RaiseRunLevel(const RaiseRunLevel&) = delete;
+            RaiseRunLevel& operator=(const RaiseRunLevel&) = delete;
+    };
 }
 
 #endif /* __XTOSKRNL_KE_RUNLEVEL_HH */

xtoskrnl/includes/ke/spinlock.hh

@@ -17,12 +17,73 @@ namespace KE
 {
     class SpinLock
     {
+        private:
+            STATIC KSPIN_LOCK DispatcherLockQueue;
+            STATIC KSPIN_LOCK ExpansionLockQueue;
+            STATIC KSPIN_LOCK FileSystemLockQueue;
+            STATIC KSPIN_LOCK IoCancelLockQueue;
+            STATIC KSPIN_LOCK IoCompletionLockQueue;
+            STATIC KSPIN_LOCK IoDatabaseLockQueue;
+            STATIC KSPIN_LOCK IoVpbLockQueue;
+            STATIC KSPIN_LOCK MasterLockQueue;
+            STATIC KSPIN_LOCK NonPagedAllocLockQueue;
+            STATIC KSPIN_LOCK NonPagedPoolLockQueue;
+            STATIC KSPIN_LOCK PfnLockQueue;
+            STATIC KSPIN_LOCK SystemSpaceLockQueue;
+            STATIC KSPIN_LOCK TimerTableLockQueue;
+            STATIC KSPIN_LOCK VacbLockQueue;
+            STATIC KSPIN_LOCK WorkLockQueue;
+
         public:
             STATIC XTFASTCALL VOID AcquireQueuedSpinLock(IN KSPIN_LOCK_QUEUE_LEVEL LockLevel);
             STATIC XTFASTCALL VOID AcquireSpinLock(IN OUT PKSPIN_LOCK SpinLock);
+            STATIC XTAPI VOID InitializeAllLocks();
+            STATIC XTAPI VOID InitializeLockQueues();
             STATIC XTAPI VOID InitializeSpinLock(IN PKSPIN_LOCK SpinLock);
             STATIC XTFASTCALL VOID ReleaseQueuedSpinLock(IN KSPIN_LOCK_QUEUE_LEVEL LockLevel);
             STATIC XTFASTCALL VOID ReleaseSpinLock(IN OUT PKSPIN_LOCK SpinLock);
+            STATIC XTFASTCALL BOOLEAN TestSpinLock(IN PKSPIN_LOCK SpinLock);
+    };
+
+    class QueuedSpinLockGuard
+    {
+        private:
+            KSPIN_LOCK_QUEUE_LEVEL QueuedLockLevel;
+
+        public:
+            QueuedSpinLockGuard(IN OUT KSPIN_LOCK_QUEUE_LEVEL LockLevel)
+            {
+                QueuedLockLevel = LockLevel;
+                KE::SpinLock::AcquireQueuedSpinLock(QueuedLockLevel);
+            }
+
+            ~QueuedSpinLockGuard()
+            {
+                KE::SpinLock::ReleaseQueuedSpinLock(QueuedLockLevel);
+            }
+
+            QueuedSpinLockGuard(const QueuedSpinLockGuard&) = delete;
+            QueuedSpinLockGuard& operator=(const QueuedSpinLockGuard&) = delete;
+    };
+
+    class SpinLockGuard
+    {
+        private:
+            PKSPIN_LOCK SpinLock;
+
+        public:
+            SpinLockGuard(IN OUT PKSPIN_LOCK SpinLock)
+            {
+                KE::SpinLock::AcquireSpinLock(SpinLock);
+            }
+
+            ~SpinLockGuard()
+            {
+                KE::SpinLock::ReleaseSpinLock(SpinLock);
+            }
+
+            SpinLockGuard(const SpinLockGuard&) = delete;
+            SpinLockGuard& operator=(const SpinLockGuard&) = delete;
     };
 }
 

xtoskrnl/includes/mm.hh

@@ -12,10 +12,10 @@
 #include <xtos.hh>
 
 #include XTOS_ARCH_HEADER(mm, pagemap.hh)
+#include XTOS_ARCH_HEADER(mm, paging.hh)
 
 #include <mm/hlpool.hh>
 #include <mm/init.hh>
 #include <mm/kpool.hh>
-#include <mm/paging.hh>
 
 #endif /* __XTOSKRNL_MM_HH */

xtoskrnl/includes/mm/amd64/pagemap.hh

@@ -1,13 +1,13 @@
 /**
  * PROJECT:         ExectOS
  * COPYRIGHT:       See COPYING.md in the top level directory
- * FILE:            xtoskrnl/includes/mm/pagemap.hh
+ * FILE:            xtoskrnl/includes/mm/amd64/pagemap.hh
  * DESCRIPTION:     Low-level support for page map manipulation
  * DEVELOPERS:      Aiken Harris <harraiken91@gmail.com>
  */
 
-#ifndef __XTOSKRNL_MM_PAGEMAP_HH
-#define __XTOSKRNL_MM_PAGEMAP_HH
+#ifndef __XTOSKRNL_MM_AMD64_PAGEMAP_HH
+#define __XTOSKRNL_MM_AMD64_PAGEMAP_HH
 
 #include <xtos.hh>
 
@@ -21,33 +21,64 @@ namespace MM
             MMPAGEMAP_INFO PageMapInfo;
 
         public:
-            XTAPI VOID ClearPte(PHARDWARE_PTE PtePointer);
-            XTAPI PMMP5E GetP5eAddress(PVOID Address);
-            XTAPI PMMPDE GetPdeAddress(PVOID Address);
-            XTAPI PMMPPE GetPpeAddress(PVOID Address);
-            XTAPI PMMPTE GetPteAddress(PVOID Address);
-            XTAPI PMMPXE GetPxeAddress(PVOID Address);
-            virtual XTAPI VOID InitializePageMapInfo(VOID) = 0;
-            XTAPI BOOLEAN PteValid(PHARDWARE_PTE PtePointer);
-            XTAPI VOID SetPte(PHARDWARE_PTE PtePointer,
-                              PFN_NUMBER PageFrameNumber,
-                              BOOLEAN Writable);
-            XTAPI VOID SetPteCaching(PHARDWARE_PTE PtePointer,
-                                     BOOLEAN CacheDisable,
-                                     BOOLEAN WriteThrough);
+            XTAPI PMMPTE AdvancePte(IN PMMPTE Pte,
+                                    IN LONG Count);
+            XTAPI VOID ClearPte(IN PMMPTE PtePointer);
+            XTAPI ULONGLONG GetEmptyPteList(VOID);
+            XTAPI ULONG_PTR GetNextEntry(IN PMMPTE Pte);
+            XTAPI PMMPTE GetNextPte(IN PMMPTE Pte);
+            XTAPI BOOLEAN GetOneEntry(IN PMMPTE Pte);
+            XTAPI PMMP5E GetP5eAddress(IN PVOID Address);
+            XTAPI ULONG GetP5eIndex(IN PVOID Address);
+            XTAPI PVOID GetP5eVirtualAddress(IN PMMP5E P5ePointer);
+            XTAPI PFN_NUMBER GetPageFrameNumber(IN PMMPTE Pte);
+            XTAPI PMMPDE GetPdeAddress(IN PVOID Address);
+            XTAPI ULONG GetPdeIndex(IN PVOID Address);
+            VIRTUAL XTAPI PVOID GetPdeVirtualAddress(IN PMMPDE PdePointer) = 0;
+            XTAPI PMMPPE GetPpeAddress(IN PVOID Address);
+            XTAPI ULONG GetPpeIndex(IN PVOID Address);
+            VIRTUAL XTAPI PVOID GetPpeVirtualAddress(IN PMMPPE PpePointer) = 0;
+            XTAPI PMMPTE GetPteAddress(IN PVOID Address);
+            XTAPI ULONG GetPteIndex(IN PVOID Address);
+            XTAPI ULONG GetPteSize(VOID);
+            VIRTUAL XTAPI PVOID GetPteVirtualAddress(IN PMMPTE PtePointer) = 0;
+            XTAPI PMMPXE GetPxeAddress(IN PVOID Address);
+            XTAPI ULONG GetPxeIndex(IN PVOID Address);
+            VIRTUAL XTAPI PVOID GetPxeVirtualAddress(IN PMMPXE PxePointer) = 0;
+            XTAPI BOOLEAN GetXpaStatus();
+            VIRTUAL XTAPI VOID InitializePageMapInfo(VOID) = 0;
+            XTAPI BOOLEAN PteValid(IN PMMPTE PtePointer);
+            XTAPI VOID SetNextEntry(IN PMMPTE Pte,
+                                    IN ULONG_PTR Value);
+            XTAPI VOID SetOneEntry(IN PMMPTE Pte,
+                                   IN BOOLEAN Value);
+            XTAPI VOID SetPte(IN PMMPTE PtePointer,
+                              IN PFN_NUMBER PageFrameNumber,
+                              IN ULONG_PTR AttributesMask);
+            XTAPI VOID SetPteCaching(IN PMMPTE PtePointer,
+                                     IN BOOLEAN CacheDisable,
+                                     IN BOOLEAN WriteThrough);
     } PAGEMAP, *PPAGEMAP;
 
     class PageMapBasic final : public PageMap
     {
         public:
+            XTAPI PVOID GetPdeVirtualAddress(IN PMMPDE PdePointer);
+            XTAPI PVOID GetPpeVirtualAddress(IN PMMPPE PpePointer);
+            XTAPI PVOID GetPteVirtualAddress(IN PMMPTE PtePointer);
+            XTAPI PVOID GetPxeVirtualAddress(IN PMMPXE PxePointer);
             XTAPI VOID InitializePageMapInfo(VOID);
     };
 
     class PageMapXpa final : public PageMap
     {
         public:
+            XTAPI PVOID GetPdeVirtualAddress(IN PMMPDE PdePointer);
+            XTAPI PVOID GetPpeVirtualAddress(IN PMMPPE PpePointer);
+            XTAPI PVOID GetPteVirtualAddress(IN PMMPTE PtePointer);
+            XTAPI PVOID GetPxeVirtualAddress(IN PMMPXE PxePointer);
             XTAPI VOID InitializePageMapInfo(VOID);
     };
 }
 
-#endif /* __XTOSKRNL_MM_PAGEMAP_HH */
+#endif /* __XTOSKRNL_MM_AMD64_PAGEMAP_HH */

xtoskrnl/includes/mm/amd64/paging.hh

@@ -0,0 +1,67 @@
+/**
+ * PROJECT:         ExectOS
+ * COPYRIGHT:       See COPYING.md in the top level directory
+ * FILE:            xtoskrnl/includes/mm/amd64/paging.hh
+ * DESCRIPTION:     Low level page management support for AMD64
+ * DEVELOPERS:      Aiken Harris <harraiken91@gmail.com>
+ */
+
+#ifndef __XTOSKRNL_MM_AMD64_PAGING_HH
+#define __XTOSKRNL_MM_AMD64_PAGING_HH
+
+#include <xtos.hh>
+
+
+/* Memory Manager */
+namespace MM
+{
+    class Paging
+    {
+        private:
+            STATIC PPAGEMAP PmlRoutines;
+
+        public:
+            STATIC XTAPI PMMPTE AdvancePte(IN PMMPTE Pte,
+                                           IN LONG Count);
+            STATIC XTAPI VOID ClearPte(IN PMMPTE PtePointer);
+            STATIC XTAPI VOID FlushTlb(VOID);
+            STATIC XTAPI ULONG_PTR GetEmptyPteList(VOID);
+            STATIC XTAPI ULONG_PTR GetNextEntry(IN PMMPTE Pte);
+            STATIC XTAPI PMMPTE GetNextPte(IN PMMPTE Pte);
+            STATIC XTAPI BOOLEAN GetOneEntry(IN PMMPTE Pte);
+            STATIC XTAPI PMMPDE GetP5eAddress(IN PVOID Address);
+            STATIC XTAPI PVOID GetP5eVirtualAddress(IN PMMP5E P5ePointer);
+            STATIC XTAPI PFN_NUMBER GetPageFrameNumber(IN PMMPTE Pte);
+            STATIC XTAPI PMMPDE GetPdeAddress(IN PVOID Address);
+            STATIC XTAPI PVOID GetPdeVirtualAddress(IN PMMPDE PdePointer);
+            STATIC XTAPI PMMPPE GetPpeAddress(IN PVOID Address);
+            STATIC XTAPI PVOID GetPpeVirtualAddress(IN PMMPPE PpePointer);
+            STATIC XTAPI PMMPTE GetPteAddress(IN PVOID Address);
+            STATIC XTAPI ULONG GetPteSize(VOID);
+            STATIC XTAPI PVOID GetPteVirtualAddress(IN PMMPTE PtePointer);
+            STATIC XTAPI PMMPXE GetPxeAddress(IN PVOID Address);
+            STATIC XTAPI PVOID GetPxeVirtualAddress(IN PMMPXE PxePointer);
+            STATIC XTAPI BOOLEAN GetXpaStatus(VOID);
+            STATIC XTAPI VOID InitializePageMapSupport(VOID);
+            STATIC XTAPI BOOLEAN PteValid(IN PMMPTE PtePointer);
+            STATIC XTAPI VOID SetNextEntry(IN PMMPTE Pte,
+                                           IN ULONG_PTR Value);
+            STATIC XTAPI VOID SetOneEntry(IN PMMPTE Pte,
+                                          IN BOOLEAN Value);
+            STATIC XTAPI VOID SetPte(IN PMMPTE PtePointer,
+                                     IN PFN_NUMBER PageFrameNumber,
+                                     IN ULONG_PTR AttributesMask);
+            STATIC XTAPI VOID SetPteCaching(IN PMMPTE PtePointer,
+                                            IN BOOLEAN CacheDisable,
+                                            IN BOOLEAN WriteThrough);
+            STATIC XTFASTCALL VOID ZeroPages(IN PVOID Address,
+                                             IN ULONG Size);
+
+        private:
+            STATIC XTAPI BOOLEAN GetExtendedPhysicalAddressingStatus(VOID);
+            STATIC XTAPI PPAGEMAP GetPageMapBasicRoutines(VOID);
+            STATIC XTAPI PPAGEMAP GetPageMapXpaRoutines(VOID);
+    };
+}
+
+#endif /* __XTOSKRNL_MM_AMD64_PAGING_HH */

xtoskrnl/includes/mm/i686/pagemap.hh

@@ -21,44 +21,85 @@ namespace MM
             MMPAGEMAP_INFO PageMapInfo;
 
         public:
-            XTAPI VOID ClearPte(PHARDWARE_PTE PtePointer);
-            XTAPI PMMPDE GetPdeAddress(PVOID Address);
-            XTAPI PMMPPE GetPpeAddress(PVOID Address);
-            XTAPI PMMPTE GetPteAddress(PVOID Address);
-            virtual XTAPI VOID InitializePageMapInfo(VOID) = 0;
-            virtual XTAPI BOOLEAN PteValid(PHARDWARE_PTE PtePointer) = 0;
-            virtual XTAPI VOID SetPte(PHARDWARE_PTE PtePointer,
-                                      PFN_NUMBER PageFrameNumber,
-                                      BOOLEAN Writable) = 0;
-            virtual XTAPI VOID SetPteCaching(PHARDWARE_PTE PtePointer,
-                                             BOOLEAN CacheDisable,
-                                             BOOLEAN WriteThrough) = 0;
+            VIRTUAL XTAPI PMMPTE AdvancePte(IN PMMPTE Pte,
+                                            IN ULONG Count) = 0;
+            XTAPI VOID ClearPte(IN PMMPTE PtePointer);
+            XTAPI ULONG GetEmptyPteList(VOID);
+            VIRTUAL XTAPI ULONG_PTR GetNextEntry(IN PMMPTE Pte) = 0;
+            VIRTUAL XTAPI PMMPTE GetNextPte(IN PMMPTE Pte) = 0;
+            VIRTUAL XTAPI BOOLEAN GetOneEntry(IN PMMPTE Pte) = 0;
+            VIRTUAL XTAPI PFN_NUMBER GetPageFrameNumber(IN PMMPTE Pte) = 0;
+            XTAPI PMMPDE GetPdeAddress(IN PVOID Address);
+            XTAPI ULONG GetPdeIndex(IN PVOID Address);
+            XTAPI PVOID GetPdeVirtualAddress(IN PMMPDE PdePointer);
+            XTAPI PMMPPE GetPpeAddress(IN PVOID Address);
+            XTAPI ULONG GetPpeIndex(IN PVOID Address);
+            XTAPI PVOID GetPpeVirtualAddress(IN PMMPPE PpePointer);
+            XTAPI PMMPTE GetPteAddress(IN PVOID Address);
+            XTAPI ULONG GetPteIndex(IN PVOID Address);
+            VIRTUAL XTAPI ULONG GetPteSize(VOID) = 0;
+            XTAPI PVOID GetPteVirtualAddress(IN PMMPTE PtePointer);
+            XTAPI BOOLEAN GetXpaStatus();
+            VIRTUAL XTAPI VOID InitializePageMapInfo(VOID) = 0;
+            VIRTUAL XTAPI BOOLEAN PteValid(IN PMMPTE PtePointer) = 0;
+            VIRTUAL XTAPI VOID SetNextEntry(IN PMMPTE Pte,
+                                            IN ULONG_PTR Value) = 0;
+            VIRTUAL XTAPI VOID SetOneEntry(IN PMMPTE Pte,
+                                           IN BOOLEAN Value) = 0;
+            VIRTUAL XTAPI VOID SetPte(IN PMMPTE PtePointer,
+                                      IN PFN_NUMBER PageFrameNumber,
+                                      IN ULONG_PTR AttributesMask) = 0;
+            VIRTUAL XTAPI VOID SetPteCaching(IN PMMPTE PtePointer,
+                                             IN BOOLEAN CacheDisable,
+                                             IN BOOLEAN WriteThrough) = 0;
     } PAGEMAP, *PPAGEMAP;
 
     class PageMapBasic final : public PageMap
     {
         public:
+            XTAPI PMMPTE AdvancePte(IN PMMPTE Pte,
+                                    IN ULONG Count);
+            XTAPI ULONG_PTR GetNextEntry(IN PMMPTE Pte);
+            XTAPI PMMPTE GetNextPte(IN PMMPTE Pte);
+            XTAPI BOOLEAN GetOneEntry(IN PMMPTE Pte);
+            XTAPI PFN_NUMBER GetPageFrameNumber(IN PMMPTE Pte);
+            XTAPI ULONG GetPteSize(VOID);
             XTAPI VOID InitializePageMapInfo(VOID);
-            XTAPI BOOLEAN PteValid(PHARDWARE_PTE PtePointer);
-            XTAPI VOID SetPte(PHARDWARE_PTE PtePointer,
-                              PFN_NUMBER PageFrameNumber,
-                              BOOLEAN Writable);
-            XTAPI VOID SetPteCaching(PHARDWARE_PTE PtePointer,
-                                     BOOLEAN CacheDisable,
-                                     BOOLEAN WriteThrough);
+            XTAPI BOOLEAN PteValid(IN PMMPTE PtePointer);
+            XTAPI VOID SetNextEntry(IN PMMPTE Pte,
+                                    IN ULONG_PTR Value);
+            XTAPI VOID SetOneEntry(IN PMMPTE Pte,
+                                   IN BOOLEAN Value);
+            XTAPI VOID SetPte(IN PMMPTE PtePointer,
+                              IN PFN_NUMBER PageFrameNumber,
+                              IN ULONG_PTR AttributesMask);
+            XTAPI VOID SetPteCaching(IN PMMPTE PtePointer,
+                                     IN BOOLEAN CacheDisable,
+                                     IN BOOLEAN WriteThrough);
     };
 
     class PageMapXpa final : public PageMap
     {
         public:
+            XTAPI PMMPTE AdvancePte(IN PMMPTE Pte,
+                                    IN ULONG Count);
+            XTAPI ULONG_PTR GetNextEntry(IN PMMPTE Pte);
+            XTAPI PMMPTE GetNextPte(IN PMMPTE Pte);
+            XTAPI BOOLEAN GetOneEntry(IN PMMPTE Pte);
+            XTAPI PFN_NUMBER GetPageFrameNumber(IN PMMPTE Pte);
+            XTAPI ULONG GetPteSize(VOID);
             XTAPI VOID InitializePageMapInfo(VOID);
-            XTAPI BOOLEAN PteValid(PHARDWARE_PTE PtePointer);
-            XTAPI VOID SetPte(PHARDWARE_PTE PtePointer,
-                              PFN_NUMBER PageFrameNumber,
-                              BOOLEAN Writable);
-            XTAPI VOID SetPteCaching(PHARDWARE_PTE PtePointer,
-                                     BOOLEAN CacheDisable,
-                                     BOOLEAN WriteThrough);
+            XTAPI BOOLEAN PteValid(IN PMMPTE PtePointer);
+            XTAPI VOID SetNextEntry(IN PMMPTE Pte,
+                                    IN ULONG_PTR Value);
+            XTAPI VOID SetOneEntry(IN PMMPTE Pte,
+                                   IN BOOLEAN Value);
+            XTAPI VOID SetPte(IN PMMPTE PtePointer,
+                              IN PFN_NUMBER PageFrameNumber,
+                              IN ULONG_PTR AttributesMask);
+            XTAPI VOID SetPteCaching(IN PMMPTE PtePointer,
+                                     IN BOOLEAN CacheDisable,
+                                     IN BOOLEAN WriteThrough);
     };
 }
 

xtoskrnl/includes/mm/i686/paging.hh

@@ -0,0 +1,63 @@
+/**
+ * PROJECT:         ExectOS
+ * COPYRIGHT:       See COPYING.md in the top level directory
+ * FILE:            xtoskrnl/includes/mm/i686/paging.hh
+ * DESCRIPTION:     Low level page management support for i686
+ * DEVELOPERS:      Aiken Harris <harraiken91@gmail.com>
+ */
+
+#ifndef __XTOSKRNL_MM_I686_PAGING_HH
+#define __XTOSKRNL_MM_I686_PAGING_HH
+
+#include <xtos.hh>
+
+
+/* Memory Manager */
+namespace MM
+{
+    class Paging
+    {
+        private:
+            STATIC PPAGEMAP PmlRoutines;
+
+        public:
+            STATIC XTAPI PMMPTE AdvancePte(IN PMMPTE Pte,
+                                           IN LONG Count);
+            STATIC XTAPI VOID ClearPte(IN PMMPTE PtePointer);
+            STATIC XTAPI VOID FlushTlb(VOID);
+            STATIC XTAPI ULONG_PTR GetEmptyPteList(VOID);
+            STATIC XTAPI ULONG_PTR GetNextEntry(IN PMMPTE Pte);
+            STATIC XTAPI PMMPTE GetNextPte(IN PMMPTE Pte);
+            STATIC XTAPI BOOLEAN GetOneEntry(IN PMMPTE Pte);
+            STATIC XTAPI PFN_NUMBER GetPageFrameNumber(IN PMMPTE Pte);
+            STATIC XTAPI PMMPDE GetPdeAddress(IN PVOID Address);
+            STATIC XTAPI PVOID GetPdeVirtualAddress(IN PMMPDE PdePointer);
+            STATIC XTAPI PMMPPE GetPpeAddress(IN PVOID Address);
+            STATIC XTAPI PVOID GetPpeVirtualAddress(IN PMMPPE PpePointer);
+            STATIC XTAPI PMMPTE GetPteAddress(IN PVOID Address);
+            STATIC XTAPI ULONG GetPteSize(VOID);
+            STATIC XTAPI PVOID GetPteVirtualAddress(IN PMMPTE PtePointer);
+            STATIC XTAPI BOOLEAN GetXpaStatus(VOID);
+            STATIC XTAPI VOID InitializePageMapSupport(VOID);
+            STATIC XTAPI BOOLEAN PteValid(IN PMMPTE PtePointer);
+            STATIC XTAPI VOID SetNextEntry(IN PMMPTE Pte,
+                                           IN ULONG_PTR Value);
+            STATIC XTAPI VOID SetOneEntry(IN PMMPTE Pte,
+                                          IN BOOLEAN Value);
+            STATIC XTAPI VOID SetPte(IN PMMPTE PtePointer,
+                                     IN PFN_NUMBER PageFrameNumber,
+                                     IN ULONG_PTR AttributesMask);
+            STATIC XTAPI VOID SetPteCaching(IN PMMPTE PtePointer,
+                                            IN BOOLEAN CacheDisable,
+                                            IN BOOLEAN WriteThrough);
+            STATIC XTFASTCALL VOID ZeroPages(IN PVOID Address,
+                                             IN ULONG Size);
+
+        private:
+            STATIC XTAPI BOOLEAN GetExtendedPhysicalAddressingStatus(VOID);
+            STATIC XTAPI PPAGEMAP GetPageMapBasicRoutines(VOID);
+            STATIC XTAPI PPAGEMAP GetPageMapXpaRoutines(VOID);
+    };
+}
+
+#endif /* __XTOSKRNL_MM_I686_PAGING_HH */

xtoskrnl/includes/mm/paging.hh

@@ -1,47 +0,0 @@
-/**
- * PROJECT:         ExectOS
- * COPYRIGHT:       See COPYING.md in the top level directory
- * FILE:            xtoskrnl/includes/mm/paging.hh
- * DESCRIPTION:     Low level page management support
- * DEVELOPERS:      Aiken Harris <harraiken91@gmail.com>
- */
-
-#ifndef __XTOSKRNL_MM_PAGING_HH
-#define __XTOSKRNL_MM_PAGING_HH
-
-#include <xtos.hh>
-
-
-/* Memory Manager */
-namespace MM
-{
-    class Paging
-    {
-        private:
-            STATIC PPAGEMAP PmlRoutines;
-
-        public:
-            STATIC XTAPI VOID ClearPte(PHARDWARE_PTE PtePointer);
-            STATIC XTAPI VOID FlushTlb(VOID);
-            STATIC XTAPI PMMPDE GetPdeAddress(PVOID Address);
-            STATIC XTAPI PMMPPE GetPpeAddress(PVOID Address);
-            STATIC XTAPI PMMPTE GetPteAddress(PVOID Address);
-            STATIC XTAPI VOID InitializePageMapSupport(VOID);
-            STATIC XTAPI BOOLEAN PteValid(PHARDWARE_PTE PtePointer);
-            STATIC XTAPI VOID SetPte(PHARDWARE_PTE PtePointer,
-                                     PFN_NUMBER PageFrameNumber,
-                                     BOOLEAN Writable);
-            STATIC XTAPI VOID SetPteCaching(PHARDWARE_PTE PtePointer,
-                                            BOOLEAN CacheDisable,
-                                            BOOLEAN WriteThrough);
-            STATIC XTFASTCALL VOID ZeroPages(IN PVOID Address,
-                                             IN ULONG Size);
-
-        private:
-            STATIC XTAPI BOOLEAN GetExtendedPhysicalAddressingStatus(VOID);
-            STATIC XTAPI PPAGEMAP GetPageMapBasicRoutines(VOID);
-            STATIC XTAPI PPAGEMAP GetPageMapXpaRoutines(VOID);
-    };
-}
-
-#endif /* __XTOSKRNL_MM_PAGING_HH */

xtoskrnl/ke/data.cc

@@ -12,12 +12,6 @@
 /* Kernel initialization block passed by boot loader */
 PKERNEL_INITIALIZATION_BLOCK KE::BootInformation::InitializationBlock = {};
 
-/* Kernel boot resources list */
-LIST_ENTRY KE::SystemResources::ResourcesListHead;
-
-/* Kernel boot resources lock */
-KSPIN_LOCK KE::SystemResources::ResourcesLock;
-
 /* Kernel initial process */
 EPROCESS KE::KProcess::InitialProcess;
 
@@ -26,3 +20,54 @@ ETHREAD KE::KThread::InitialThread = {};
 
 /* Kernel UBSAN active frame flag */
 BOOLEAN KE::KUbsan::ActiveFrame = FALSE;
+
+/* Kernel dispatcher lock queue */
+KSPIN_LOCK KE::SpinLock::DispatcherLockQueue;
+
+/* Kernel expansion lock queue */
+KSPIN_LOCK KE::SpinLock::ExpansionLockQueue;
+
+/* Kernel file system structures lock queue */
+KSPIN_LOCK KE::SpinLock::FileSystemLockQueue;
+
+/* Kernel IO cancel lock queue */
+KSPIN_LOCK KE::SpinLock::IoCancelLockQueue;
+
+/* Kernel IO completion lock queue */
+KSPIN_LOCK KE::SpinLock::IoCompletionLockQueue;
+
+/* Kernel IO database lock queue */
+KSPIN_LOCK KE::SpinLock::IoDatabaseLockQueue;
+
+/* Kernel IO VPB lock queue */
+KSPIN_LOCK KE::SpinLock::IoVpbLockQueue;
+
+/* Kernel cache master lock queue */
+KSPIN_LOCK KE::SpinLock::MasterLockQueue;
+
+/* Kernel non-paged allocator lock queue */
+KSPIN_LOCK KE::SpinLock::NonPagedAllocLockQueue;
+
+/* Kernel non-paged pool lock queue */
+KSPIN_LOCK KE::SpinLock::NonPagedPoolLockQueue;
+
+/* Kernel PFN lock queue */
+KSPIN_LOCK KE::SpinLock::PfnLockQueue;
+
+/* Kernel system space lock queue */
+KSPIN_LOCK KE::SpinLock::SystemSpaceLockQueue;
+
+/* Kernel Timer table lock queue */
+KSPIN_LOCK KE::SpinLock::TimerTableLockQueue;
+
+/* Kernel VACB lock queue */
+KSPIN_LOCK KE::SpinLock::VacbLockQueue;
+
+/* Kernel work queue lock queue */
+KSPIN_LOCK KE::SpinLock::WorkLockQueue;
+
+/* Kernel boot resources list */
+LIST_ENTRY KE::SystemResources::ResourcesListHead;
+
+/* Kernel boot resources lock */
+KSPIN_LOCK KE::SystemResources::ResourcesLock;

xtoskrnl/ke/spinlock.cc

@@ -4,6 +4,7 @@
  * FILE:            xtoskrnl/ke/spinlock.cc
  * DESCRIPTION:     Spinlocks support
  * DEVELOPERS:      Rafal Kupiec <belliash@codingworkshop.eu.org>
+ *                  Aiken Harris <harraiken91@gmail.com>
  */
 
 #include <xtos.hh>
@@ -56,6 +57,78 @@ KE::SpinLock::AcquireSpinLock(IN OUT PKSPIN_LOCK SpinLock)
     AR::CpuFunc::ReadWriteBarrier();
 }
 
+/**
+ * Initializes all kernel spinlocks.
+ *
+ * @return This routine does not return any value.
+ *
+ * @since XT 1.0
+ */
+XTAPI
+VOID
+KE::SpinLock::InitializeAllLocks()
+{
+    /* Initialize all spin locks */
+    InitializeSpinLock(&DispatcherLockQueue);
+    InitializeSpinLock(&PfnLockQueue);
+    InitializeSpinLock(&SystemSpaceLockQueue);
+}
+
+/**
+ * Initializes spinlock queues for current processor.
+ *
+ * @return This routine does not return any value.
+ *
+ * @since XT 1.0
+ */
+XTAPI
+VOID
+KE::SpinLock::InitializeLockQueues()
+{
+    PKPROCESSOR_CONTROL_BLOCK ControlBlock;
+
+    /* Get current processor control block */
+    ControlBlock = KE::Processor::GetCurrentProcessorControlBlock();
+
+    /* Initialize PCB lock queues */
+    ControlBlock->LockQueue[DispatcherLock].Lock = &DispatcherLockQueue;
+    ControlBlock->LockQueue[DispatcherLock].Next = NULLPTR;
+    ControlBlock->LockQueue[ExpansionLock].Lock = &ExpansionLockQueue;
+    ControlBlock->LockQueue[ExpansionLock].Next = NULLPTR;
+    ControlBlock->LockQueue[PfnLock].Lock = &PfnLockQueue;
+    ControlBlock->LockQueue[PfnLock].Next = NULLPTR;
+    ControlBlock->LockQueue[SystemSpaceLock].Lock = &SystemSpaceLockQueue;
+    ControlBlock->LockQueue[SystemSpaceLock].Next = NULLPTR;
+    ControlBlock->LockQueue[VacbLock].Lock = &VacbLockQueue;
+    ControlBlock->LockQueue[VacbLock].Next = NULLPTR;
+    ControlBlock->LockQueue[MasterLock].Lock = &MasterLockQueue;
+    ControlBlock->LockQueue[MasterLock].Next = NULLPTR;
+    ControlBlock->LockQueue[NonPagedAllocPoolLock].Lock = &NonPagedAllocLockQueue;
+    ControlBlock->LockQueue[NonPagedAllocPoolLock].Next = NULLPTR;
+    ControlBlock->LockQueue[IoCancelLock].Lock = &IoCancelLockQueue;
+    ControlBlock->LockQueue[IoCancelLock].Next = NULLPTR;
+    ControlBlock->LockQueue[WorkQueueLock].Lock = &WorkLockQueue;
+    ControlBlock->LockQueue[WorkQueueLock].Next = NULLPTR;
+    ControlBlock->LockQueue[IoVpbLock].Lock = &IoVpbLockQueue;
+    ControlBlock->LockQueue[IoVpbLock].Next = NULLPTR;
+    ControlBlock->LockQueue[IoDatabaseLock].Lock = &IoDatabaseLockQueue;
+    ControlBlock->LockQueue[IoDatabaseLock].Next = NULLPTR;
+    ControlBlock->LockQueue[IoCompletionLock].Lock = &IoCompletionLockQueue;
+    ControlBlock->LockQueue[IoCompletionLock].Next = NULLPTR;
+    ControlBlock->LockQueue[FileSystemLock].Lock = &FileSystemLockQueue;
+    ControlBlock->LockQueue[FileSystemLock].Next = NULLPTR;
+    ControlBlock->LockQueue[AfdWorkQueueLock].Lock = NULLPTR;
+    ControlBlock->LockQueue[AfdWorkQueueLock].Next = NULLPTR;
+    ControlBlock->LockQueue[BcbLock].Lock = NULLPTR;
+    ControlBlock->LockQueue[BcbLock].Next = NULLPTR;
+    ControlBlock->LockQueue[NonPagedPoolLock].Lock = &NonPagedPoolLockQueue;
+    ControlBlock->LockQueue[NonPagedPoolLock].Next = NULLPTR;
+    ControlBlock->LockQueue[ReservedSystemLock].Lock = NULLPTR;
+    ControlBlock->LockQueue[ReservedSystemLock].Next = NULLPTR;
+    ControlBlock->LockQueue[TimerTableLock].Lock = &TimerTableLockQueue;
+    ControlBlock->LockQueue[TimerTableLock].Next = NULLPTR;
+}
+
 /**
  * Initializes a kernel spinlock object.
  *
@@ -112,3 +185,29 @@ KE::SpinLock::ReleaseSpinLock(IN OUT PKSPIN_LOCK SpinLock)
     /* Add an explicit memory barrier */
     AR::CpuFunc::ReadWriteBarrier();
 }
+
+/**
+ * Tests a kernel spin lock.
+ *
+ * @param SpinLock
+ *        Supplies a pointer to the kernel spin lock.
+ *
+ * @return This routine returns TRUE if the lock is free, FALSE otherwise.
+ *
+ * @since XT 1.0
+ */
+XTFASTCALL
+BOOLEAN
+TestSpinLock(IN PKSPIN_LOCK SpinLock)
+{
+    /* Check if the lock is free */
+    if(*SpinLock)
+    {
+        /* Spinlock is busy, yield processor and return FALSE */
+        AR::CpuFunc::YieldProcessor();
+        return FALSE;
+    }
+
+    /* Spinlock is free, return TRUE */
+    return TRUE;
+}

xtoskrnl/mm/amd64/pagemap.cc

@@ -9,6 +9,28 @@
 #include <xtos.hh>
 
 
+/**
+ * Advances a PTE pointer by a given number of entries, considering the actual PTE size.
+ *
+ * @param Pte
+ *        The PTE pointer to advance.
+ *
+ * @param Count
+ *        The number of PTE entries to advance by.
+ *
+ * @return The advanced PTE pointer.
+ *
+ * @since XT 1.0
+ */
+XTAPI
+PMMPTE
+MM::PageMap::AdvancePte(IN PMMPTE Pte,
+                        IN LONG Count)
+{
+    /* Return advanced PTE pointer */
+    return (PMMPTE)((ULONG_PTR)Pte + (Count * sizeof(MMPTE)));
+}
+
 /**
  * Clears the contents of a page table entry (PTE).
  *
@@ -21,13 +43,79 @@
  */
 XTAPI
 VOID
-MM::PageMap::ClearPte(PHARDWARE_PTE PtePointer)
+MM::PageMap::ClearPte(IN PMMPTE PtePointer)
 {
-    PtePointer->CacheDisable = 0;
-    PtePointer->PageFrameNumber = 0;
-    PtePointer->Valid = 0;
-    PtePointer->Writable = 0;
-    PtePointer->WriteThrough = 0;
+    /* Clear PTE */
+    PtePointer->Long = 0;
+}
+
+/**
+ * Gets the value representing an empty PTE list.
+ *
+ * @return This routine returns the value representing an empty PTE list.
+ *
+ * @since XT 1.0
+ */
+XTAPI
+ULONGLONG
+MM::PageMap::GetEmptyPteList(VOID)
+{
+    /* Return empty PTE list mask */
+    return PageMapInfo.EmptyPteList;
+}
+
+/**
+ * Gets the next entry in a PTE list.
+ *
+ * @param Pte
+ *        The PTE pointer to get the next entry from.
+ *
+ * @return This routine returns the next entry in the PTE list.
+ *
+ * @since XT 1.0
+ */
+XTAPI
+ULONG_PTR
+MM::PageMap::GetNextEntry(IN PMMPTE Pte)
+{
+    /* Return next entry in PTE list */
+    return Pte->List.NextEntry;
+}
+
+/**
+ * Advances a PTE pointer, considering the actual PTE size.
+ *
+ * @param Pte
+ *        The PTE pointer to advance.
+ *
+ * @return The advanced PTE pointer.
+ *
+ * @since XT 1.0
+ */
+XTAPI
+PMMPTE
+MM::PageMap::GetNextPte(IN PMMPTE Pte)
+{
+    /* Return advanced PTE pointer */
+    return AdvancePte(Pte, 1);
+}
+
+/**
+ * Checks if a PTE list contains only one entry.
+ *
+ * @param Pte
+ *        The PTE pointer to check.
+ *
+ * @return This routine returns TRUE if the PTE list has only one entry, FALSE otherwise.
+ *
+ * @since XT 1.0
+ */
+XTAPI
+BOOLEAN
+MM::PageMap::GetOneEntry(IN PMMPTE Pte)
+{
+    /* Return one entry status */
+    return Pte->List.OneEntry;
 }
 
 /**
@@ -42,7 +130,7 @@ MM::PageMap::ClearPte(PHARDWARE_PTE PtePointer)
  */
 XTAPI
 PMMP5E
-MM::PageMap::GetP5eAddress(PVOID Address)
+MM::PageMap::GetP5eAddress(IN PVOID Address)
 {
     ULONGLONG Offset;
 
@@ -51,6 +139,57 @@ MM::PageMap::GetP5eAddress(PVOID Address)
     return (PMMP5E)((PageMapInfo.P5eBase + Offset) * PageMapInfo.Xpa);
 }
 
+/**
+ * Gets the index of the P5E (Page Map Level 5 Entry), that maps given address.
+ *
+ * @param Address
+ *        Specifies the virtual address for which to retrieve the corresponding P5E.
+ *
+ * @return This routine returns the index of the P5E, or NULLPTR if LA57 is not enabled.
+ *
+ * @since XT 1.0
+ */
+XTAPI
+ULONG
+MM::PageMap::GetP5eIndex(IN PVOID Address)
+{
+    return (((((ULONGLONG)Address) >> MM_P5I_SHIFT) & 0x1FF) * PageMapInfo.Xpa);
+}
+
+/**
+ * Gets the virtual address that is mapped by a given Page Map Level 5 Entry.
+ *
+ * @param P5ePointer
+ *        Specifies the address of the P5E.
+ *
+ * @return This routine returns the virtual address mapped by the P5E, or NULLPTR if LA57 is not enabled.
+ *
+ * @since XT 1.0
+ */
+XTAPI
+PVOID
+MM::PageMap::GetP5eVirtualAddress(IN PMMP5E P5ePointer)
+{
+    return (PVOID)((((LONGLONG)P5ePointer << 52) >> 7) * PageMapInfo.Xpa);
+}
+
+/**
+ * Gets the page frame number from a corresponding PTE.
+ *
+ * @param Pte
+ *        The PTE pointer to get the page frame number from.
+ *
+ * @return This routine returns the page frame number.
+ *
+ * @since XT 1.0
+ */
+XTAPI
+PFN_NUMBER
+MM::PageMap::GetPageFrameNumber(IN PMMPTE Pte)
+{
+    return Pte->Hardware.PageFrameNumber;
+}
+
 /**
  * Gets the address of the PDE (Page Directory Entry), that maps given address.
  *
@@ -63,7 +202,7 @@ MM::PageMap::GetP5eAddress(PVOID Address)
  */
 XTAPI
 PMMPDE
-MM::PageMap::GetPdeAddress(PVOID Address)
+MM::PageMap::GetPdeAddress(IN PVOID Address)
 {
     ULONGLONG Offset;
 
@@ -73,18 +212,36 @@ MM::PageMap::GetPdeAddress(PVOID Address)
 }
 
 /**
- * Gets the address of the PPE (Page Directory Pointer Table Entry), that maps given address.
+ * Gets the index of the PDE (Page Directory Entry), that maps given address.
  *
  * @param Address
  *        Specifies the virtual address for which to retrieve the corresponding PDE.
  *
+ * @return This routine returns the index of the PDE.
+ *
+ * @since XT 1.0
+ */
+XTAPI
+ULONG
+MM::PageMap::GetPdeIndex(IN PVOID Address)
+{
+    /* Return PDE index */
+    return ((((ULONGLONG)Address) >> MM_PDI_SHIFT) & 0x1FF);
+}
+
+/**
+ * Gets the address of the PPE (Page Directory Pointer Table Entry), that maps given address.
+ *
+ * @param Address
+ *        Specifies the virtual address for which to retrieve the corresponding PPE.
+ *
  * @return This routine returns the address of the PPE.
  *
  * @since XT 1.0
  */
 XTAPI
 PMMPPE
-MM::PageMap::GetPpeAddress(PVOID Address)
+MM::PageMap::GetPpeAddress(IN PVOID Address)
 {
     ULONGLONG Offset;
 
@@ -93,6 +250,24 @@ MM::PageMap::GetPpeAddress(PVOID Address)
     return (PMMPPE)(PageMapInfo.PpeBase + Offset);
 }
 
+/**
+ * Gets the index of the PPE (Page Directory Pointer Table Entry), that maps given address.
+ *
+ * @param Address
+ *        Specifies the virtual address for which to retrieve the corresponding PPE.
+ *
+ * @return This routine returns the index of the PPE.
+ *
+ * @since XT 1.0
+ */
+XTAPI
+ULONG
+MM::PageMap::GetPpeIndex(IN PVOID Address)
+{
+    /* Return PPE index */
+    return ((((ULONGLONG)Address) >> MM_PPI_SHIFT) & 0x1FF);
+}
+
 /**
  * Gets the address of the PTE (Page Table Entry), that maps given address.
  *
@@ -105,7 +280,7 @@ MM::PageMap::GetPpeAddress(PVOID Address)
  */
 XTAPI
 PMMPTE
-MM::PageMap::GetPteAddress(PVOID Address)
+MM::PageMap::GetPteAddress(IN PVOID Address)
 {
     ULONGLONG Offset;
 
@@ -114,6 +289,39 @@ MM::PageMap::GetPteAddress(PVOID Address)
     return (PMMPTE)(PageMapInfo.PteBase + Offset);
 }
 
+/**
+ * Gets the index of the PTE (Page Table Entry), that maps given address.
+ *
+ * @param Address
+ *        Specifies the virtual address for which to retrieve the corresponding PTE.
+ *
+ * @return This routine returns the index of the PTE.
+ *
+ * @since XT 1.0
+ */
+XTAPI
+ULONG
+MM::PageMap::GetPteIndex(IN PVOID Address)
+{
+    /* Return PTE index */
+    return ((((ULONGLONG)Address) >> MM_PTI_SHIFT) & 0x1FF);
+}
+
+/**
+ * Gets the size of a PTE.
+ *
+ * @return This routine returns the size of a PTE.
+ *
+ * @since XT 1.0
+ */
+XTAPI
+ULONG
+MM::PageMap::GetPteSize(VOID)
+{
+    /* Return the size of MMPTE */
+    return sizeof(MMPTE);
+}
+
 /**
  * Gets the address of the PXE (Extended Page Entry), that maps given address.
  *
@@ -126,14 +334,47 @@ MM::PageMap::GetPteAddress(PVOID Address)
  */
 XTAPI
 PMMPXE
-MM::PageMap::GetPxeAddress(PVOID Address)
+MM::PageMap::GetPxeAddress(IN PVOID Address)
 {
     ULONGLONG Offset;
 
+    /* Calculate offset and return PXE address */
     Offset = ((((ULONGLONG)Address & (((ULONGLONG)1 << PageMapInfo.VaBits) - 1)) >> MM_PXI_SHIFT) << MM_PTE_SHIFT);
     return (PMMPXE)(PageMapInfo.PxeBase + Offset);
 }
 
+/**
+ * Gets the index of the PXE (Extended Page Entry), that maps given address.
+ *
+ * @param Address
+ *        Specifies the virtual address for which to retrieve the corresponding PXE.
+ *
+ * @return This routine returns the index of the PXE.
+ *
+ * @since XT 1.0
+ */
+XTAPI
+ULONG
+MM::PageMap::GetPxeIndex(IN PVOID Address)
+{
+    /* Return PXE index */
+    return ((((ULONGLONG)Address) >> MM_PXI_SHIFT) & 0x1FF);
+}
+
+/**
+ * Gets the status of Extended Paging Address (XPA) mode.
+ *
+ * @return This routine returns TRUE if XPA is enabled, FALSE otherwise.
+ *
+ * @since XT 1.0
+ */
+XTAPI
+BOOLEAN
+MM::PageMap::GetXpaStatus()
+{
+    return PageMapInfo.Xpa;
+}
+
 /**
  * Checks whether the given PML2 page table entry (PTE) is valid.
  *
@@ -146,9 +387,54 @@ MM::PageMap::GetPxeAddress(PVOID Address)
  */
 XTAPI
 BOOLEAN
-MM::PageMap::PteValid(PHARDWARE_PTE PtePointer)
+MM::PageMap::PteValid(IN PMMPTE PtePointer)
 {
-    return (BOOLEAN)PtePointer->Valid;
+    /* Check if PTE is valid */
+    return (BOOLEAN)PtePointer->Hardware.Valid;
+}
+
+/**
+ * Sets the next entry in a PTE list.
+ *
+ * @param Pte
+ *        The PTE pointer to modify.
+ *
+ * @param Value
+ *        The value to set as the next entry.
+ *
+ * @return This routine does not return any value.
+ *
+ * @since XT 1.0
+ */
+XTAPI
+VOID
+MM::PageMap::SetNextEntry(IN PMMPTE Pte,
+                          IN ULONG_PTR Value)
+{
+    /* Set next entry in PTE list */
+    Pte->List.NextEntry = Value;
+}
+
+/**
+ * Sets the flag indicating whether a PTE list contains only one entry.
+ *
+ * @param Pte
+ *        The PTE pointer to modify.
+ *
+ * @param Value
+ *        The value to set. TRUE if the list has only one entry, FALSE otherwise.
+ *
+ * @return This routine does not return any value.
+ *
+ * @since XT 1.0
+ */
+XTAPI
+VOID
+MM::PageMap::SetOneEntry(IN PMMPTE Pte,
+                         IN BOOLEAN Value)
+{
+    /* Set one entry status */
+    Pte->List.OneEntry = Value;
 }
 
 /**
@@ -160,8 +446,8 @@ MM::PageMap::PteValid(PHARDWARE_PTE PtePointer)
  * @param PageFrameNumber
  *        Physical frame number to map.
  *
- * @param Writable
- *        Indicates whether the page should be writable.
+ * @param AttributesMask
+ *        Specifies the attributes mask to apply to the PTE.
  *
  * @return This routine does not return any value.
  *
@@ -169,13 +455,14 @@ MM::PageMap::PteValid(PHARDWARE_PTE PtePointer)
  */
 XTAPI
 VOID
-MM::PageMap::SetPte(PHARDWARE_PTE PtePointer,
-                    PFN_NUMBER PageFrameNumber,
-                    BOOLEAN Writable)
+MM::PageMap::SetPte(IN PMMPTE PtePointer,
+                    IN PFN_NUMBER PageFrameNumber,
+                    IN ULONG_PTR AttributesMask)
 {
-    PtePointer->PageFrameNumber = PageFrameNumber;
-    PtePointer->Valid = 1;
-    PtePointer->Writable = Writable;
+    /* Set PTE */
+    PtePointer->Hardware.PageFrameNumber = PageFrameNumber;
+    PtePointer->Hardware.Valid = 1;
+    PtePointer->Long |= AttributesMask;
 }
 
 /**
@@ -196,12 +483,85 @@ MM::PageMap::SetPte(PHARDWARE_PTE PtePointer,
  */
 XTAPI
 VOID
-MM::PageMap::SetPteCaching(PHARDWARE_PTE PtePointer,
-                           BOOLEAN CacheDisable,
-                           BOOLEAN WriteThrough)
+MM::PageMap::SetPteCaching(IN PMMPTE PtePointer,
+                           IN BOOLEAN CacheDisable,
+                           IN BOOLEAN WriteThrough)
 {
-    PtePointer->CacheDisable = CacheDisable;
-    PtePointer->WriteThrough = WriteThrough;
+    /* Set caching attributes */
+    PtePointer->Hardware.CacheDisable = CacheDisable;
+    PtePointer->Hardware.WriteThrough = WriteThrough;
+}
+
+/**
+ * Gets the virtual address that is mapped by a given Page Directory Entry (PML4).
+ *
+ * @param PdePointer
+ *        Specifies the address of the PDE.
+ *
+ * @return This routine returns the virtual address mapped by the PDE.
+ *
+ * @since XT 1.0
+ */
+XTAPI
+PVOID
+MM::PageMapBasic::GetPdeVirtualAddress(IN PMMPDE PdePointer)
+{
+    /* Return PDE virtual address */
+    return (PVOID)(((LONGLONG)PdePointer << 34) >> 16);
+}
+
+/**
+ * Gets the virtual address that is mapped by a given Page Directory Pointer Table Entry (PML4).
+ *
+ * @param PpePointer
+ *        Specifies the address of the PPE.
+ *
+ * @return This routine returns the virtual address mapped by the PPE.
+ *
+ * @since XT 1.0
+ */
+XTAPI
+PVOID
+MM::PageMapBasic::GetPpeVirtualAddress(IN PMMPPE PpePointer)
+{
+    /* Return PPE virtual address */
+    return (PVOID)(((LONGLONG)PpePointer << 43) >> 16);
+}
+
+/**
+ * Gets the virtual address that is mapped by a given Page Table Entry (PML4).
+ *
+ * @param PtePointer
+ *        Specifies the address of the PTE.
+ *
+ * @return This routine returns the virtual address mapped by the PTE.
+ *
+ * @since XT 1.0
+ */
+XTAPI
+PVOID
+MM::PageMapBasic::GetPteVirtualAddress(IN PMMPTE PtePointer)
+{
+    /* Return PTE virtual address */
+    return (PVOID)(((LONGLONG)PtePointer << 25) >> 16);
+}
+
+/**
+ * Gets the virtual address that is mapped by a given Extended Page Entry (PML4).
+ *
+ * @param PxePointer
+ *        Specifies the address of the PXE.
+ *
+ * @return This routine returns the virtual address mapped by the PXE.
+ *
+ * @since XT 1.0
+ */
+XTAPI
+PVOID
+MM::PageMapBasic::GetPxeVirtualAddress(IN PMMPXE PxePointer)
+{
+    /* Return PXE virtual address */
+    return (PVOID)(((LONGLONG)PxePointer << 52) >> 16);
 }
 
 /**
@@ -218,6 +578,9 @@ MM::PageMapBasic::InitializePageMapInfo(VOID)
     /* Set PML4 page map information */
     PageMapInfo.Xpa = FALSE;
 
+    /* Set PML4 empty PTE list mask */
+    PageMapInfo.EmptyPteList = 0xFFFFFFFFUI64;
+
     /* Set PML4 base addresses */
     PageMapInfo.PteBase = MM_PTE_BASE;
     PageMapInfo.PdeBase = MM_PDE_BASE;
@@ -229,6 +592,78 @@ MM::PageMapBasic::InitializePageMapInfo(VOID)
     PageMapInfo.VaBits = 48;
 }
 
+/**
+ * Gets the virtual address that is mapped by a given Page Directory Entry (PML5).
+ *
+ * @param PdePointer
+ *        Specifies the address of the PDE.
+ *
+ * @return This routine returns the virtual address mapped by the PDE.
+ *
+ * @since XT 1.0
+ */
+XTAPI
+PVOID
+MM::PageMapXpa::GetPdeVirtualAddress(IN PMMPDE PdePointer)
+{
+    /* Return PDE virtual address */
+    return (PVOID)(((LONGLONG)PdePointer << 25) >> 7);
+}
+
+/**
+ * Gets the virtual address that is mapped by a given Page Directory Pointer Table Entry (PML5).
+ *
+ * @param PpePointer
+ *        Specifies the address of the PPE.
+ *
+ * @return This routine returns the virtual address mapped by the PPE.
+ *
+ * @since XT 1.0
+ */
+XTAPI
+PVOID
+MM::PageMapXpa::GetPpeVirtualAddress(IN PMMPPE PpePointer)
+{
+    /* Return PPE virtual address */
+    return (PVOID)(((LONGLONG)PpePointer << 34) >> 7);
+}
+
+/**
+ * Gets the virtual address that is mapped by a given Page Table Entry (PML5).
+ *
+ * @param PtePointer
+ *        Specifies the address of the PTE.
+ *
+ * @return This routine returns the virtual address mapped by the PTE.
+ *
+ * @since XT 1.0
+ */
+XTAPI
+PVOID
+MM::PageMapXpa::GetPteVirtualAddress(IN PMMPTE PtePointer)
+{
+    /* Return PTE virtual address */
+    return (PVOID)(((LONGLONG)PtePointer << 16) >> 7);
+}
+
+/**
+ * Gets the virtual address that is mapped by a given Extended Page Entry (PML5).
+ *
+ * @param PxePointer
+ *        Specifies the address of the PXE.
+ *
+ * @return This routine returns the virtual address mapped by the PXE.
+ *
+ * @since XT 1.0
+ */
+XTAPI
+PVOID
+MM::PageMapXpa::GetPxeVirtualAddress(IN PMMPXE PxePointer)
+{
+    /* Return PXE virtual address */
+    return (PVOID)(((LONGLONG)PxePointer << 43) >> 7);
+}
+
 /**
  * Initializes page map information for XPA paging (PML5).
  *
@@ -243,6 +678,9 @@ MM::PageMapXpa::InitializePageMapInfo(VOID)
     /* Set PML5 page map information */
     PageMapInfo.Xpa = TRUE;
 
+    /* Set PML5 empty PTE list mask */
+    PageMapInfo.EmptyPteList = 0xFFFFFFFFUI64;
+
     /* Set PML5 base addresses */
     PageMapInfo.PteBase = MM_PTE_LA57_BASE;
     PageMapInfo.PdeBase = MM_PDE_LA57_BASE;

xtoskrnl/mm/amd64/paging.cc

@@ -25,6 +25,78 @@ MM::Paging::GetExtendedPhysicalAddressingStatus(VOID)
     return ((AR::CpuFunc::ReadControlRegister(4) & CR4_LA57) != 0) ? TRUE : FALSE;
 }
 
+/**
+ * Gets the address of the P5E (Page Map Level 5 Entry), that maps given address.
+ *
+ * @param Address
+ *        Specifies the virtual address for which to retrieve the corresponding P5E.
+ *
+ * @return This routine returns the address of the P5E, or NULLPTR if LA57 is not enabled.
+ *
+ * @since XT 1.0
+ */
+XTAPI
+PMMPDE
+MM::Paging::GetP5eAddress(IN PVOID Address)
+{
+    /* Return PDE address */
+    return PmlRoutines->GetP5eAddress(Address);
+}
+
+/**
+ * Gets the virtual address that is mapped by a given Page Map Level 5 Entry.
+ *
+ * @param P5ePointer
+ *        Specifies the address of the P5E.
+ *
+ * @return This routine returns the virtual address mapped by the P5E, or NULLPTR if LA57 is not enabled.
+ *
+ * @since XT 1.0
+ */
+XTAPI
+PVOID
+MM::Paging::GetP5eVirtualAddress(IN PMMP5E P5ePointer)
+{
+    /* Return PTE virtual address */
+    return PmlRoutines->GetP5eVirtualAddress(P5ePointer);
+}
+
+/**
+ * Gets the address of the PXE (Extended Page Entry), that maps given address.
+ *
+ * @param Address
+ *        Specifies the virtual address for which to retrieve the corresponding PXE.
+ *
+ * @return This routine returns the address of the PXE.
+ *
+ * @since XT 1.0
+ */
+XTAPI
+PMMPXE
+MM::Paging::GetPxeAddress(IN PVOID Address)
+{
+    /* Return PXE address */
+    return PmlRoutines->GetPxeAddress(Address);
+}
+
+/**
+ * Gets the virtual address that is mapped by a given Extended Page Entry.
+ *
+ * @param PxePointer
+ *        Specifies the address of the PXE.
+ *
+ * @return This routine returns the virtual address mapped by the PXE.
+ *
+ * @since XT 1.0
+ */
+XTAPI
+PVOID
+MM::Paging::GetPxeVirtualAddress(IN PMMPXE PxePointer)
+{
+    /* Return PXE virtual address */
+    return PmlRoutines->GetPxeVirtualAddress(PxePointer);
+}
+
 /**
  * Fills a section of memory with zeroes like RtlZeroMemory(), but in more efficient way.
  *

xtoskrnl/mm/hlpool.cc

@@ -170,7 +170,7 @@ MM::HardwarePool::MapHardwareMemory(IN PHYSICAL_ADDRESS PhysicalAddress,
 {
     PVOID BaseAddress, ReturnAddress;
     PFN_NUMBER MappedPages;
-    PHARDWARE_PTE PtePointer;
+    PMMPTE PtePointer;
 
     /* Initialize variables */
     BaseAddress = HardwareHeapStart;
@@ -189,7 +189,7 @@ MM::HardwarePool::MapHardwareMemory(IN PHYSICAL_ADDRESS PhysicalAddress,
         }
 
         /* Get PTE pointer and advance to next page */
-        PtePointer = (PHARDWARE_PTE)MM::Paging::GetPteAddress(ReturnAddress);
+        PtePointer = MM::Paging::GetPteAddress(ReturnAddress);
         ReturnAddress = (PVOID)((ULONG_PTR)ReturnAddress + MM_PAGE_SIZE);
 
         /* Check if PTE is valid */
@@ -219,10 +219,10 @@ MM::HardwarePool::MapHardwareMemory(IN PHYSICAL_ADDRESS PhysicalAddress,
     while(MappedPages--)
     {
         /* Get PTE pointer */
-        PtePointer = (PHARDWARE_PTE)MM::Paging::GetPteAddress(BaseAddress);
+        PtePointer = MM::Paging::GetPteAddress(BaseAddress);
 
         /* Fill the PTE */
-        MM::Paging::SetPte(PtePointer, (PFN_NUMBER)(PhysicalAddress.QuadPart >> MM_PAGE_SHIFT), TRUE);
+        MM::Paging::SetPte(PtePointer, (PFN_NUMBER)(PhysicalAddress.QuadPart >> MM_PAGE_SHIFT), MM_PTE_READWRITE);
 
         /* Advance to the next address */
         PhysicalAddress.QuadPart += MM_PAGE_SIZE;
@@ -259,18 +259,18 @@ VOID
 MM::HardwarePool::MarkHardwareMemoryWriteThrough(IN PVOID VirtualAddress,
                                                  IN PFN_NUMBER PageCount)
 {
-    PHARDWARE_PTE PtePointer;
+    PMMPTE PtePointer;
     PFN_NUMBER Page;
 
     /* Get PTE address from virtual address */
-    PtePointer = (PHARDWARE_PTE)MM::Paging::GetPteAddress(VirtualAddress);
+    PtePointer = MM::Paging::GetPteAddress(VirtualAddress);
 
     /* Iterate through mapped pages */
     for(Page = 0; Page < PageCount; Page++)
     {
         /* Mark pages as CD/WT */
         MM::Paging::SetPteCaching(PtePointer, TRUE, TRUE);
-        PtePointer++;
+        MM::Paging::GetNextEntry(PtePointer);
     }
 }
 
@@ -296,13 +296,13 @@ MM::HardwarePool::RemapHardwareMemory(IN PVOID VirtualAddress,
                                       IN PHYSICAL_ADDRESS PhysicalAddress,
                                       IN BOOLEAN FlushTlb)
 {
-    PHARDWARE_PTE PtePointer;
+    PMMPTE PtePointer;
 
     /* Get PTE address from virtual address */
-    PtePointer = (PHARDWARE_PTE)MM::Paging::GetPteAddress(VirtualAddress);
+    PtePointer = MM::Paging::GetPteAddress(VirtualAddress);
 
     /* Remap the PTE */
-    MM::Paging::SetPte(PtePointer, (PFN_NUMBER)(PhysicalAddress.QuadPart >> MM_PAGE_SHIFT), TRUE);
+    MM::Paging::SetPte(PtePointer, (PFN_NUMBER)(PhysicalAddress.QuadPart >> MM_PAGE_SHIFT), MM_PTE_READWRITE);
 
     /* Check if TLB needs to be flushed */
     if(FlushTlb)
@@ -334,7 +334,7 @@ MM::HardwarePool::UnmapHardwareMemory(IN PVOID VirtualAddress,
                                       IN PFN_NUMBER PageCount,
                                       IN BOOLEAN FlushTlb)
 {
-    PHARDWARE_PTE PtePointer;
+    PMMPTE PtePointer;
     PFN_NUMBER Page;
 
     /* Check if address is valid hardware memory */
@@ -348,7 +348,7 @@ MM::HardwarePool::UnmapHardwareMemory(IN PVOID VirtualAddress,
     VirtualAddress = (PVOID)((ULONG_PTR)VirtualAddress & ~(MM_PAGE_SIZE - 1));
 
     /* Get PTE address from virtual address */
-    PtePointer = (PHARDWARE_PTE)MM::Paging::GetPteAddress(VirtualAddress);
+    PtePointer = MM::Paging::GetPteAddress(VirtualAddress);
 
     /* Iterate through mapped pages */
     for(Page = 0; Page < PageCount; Page++)

xtoskrnl/mm/i686/pagemap.cc

@@ -21,11 +21,27 @@
  */
 XTAPI
 VOID
-MM::PageMap::ClearPte(PHARDWARE_PTE PtePointer)
+MM::PageMap::ClearPte(IN PMMPTE PtePointer)
 {
+    /* Clear PTE */
     PtePointer->Long = 0;
 }
 
+/**
+ * Gets the value representing an empty PTE list.
+ *
+ * @return This routine returns the value representing an empty PTE list.
+ *
+ * @since XT 1.0
+ */
+XTAPI
+ULONG
+MM::PageMap::GetEmptyPteList(VOID)
+{
+    /* Return empty PTE list mask */
+    return PageMapInfo.EmptyPteList;
+}
+
 /**
  * Gets the address of the PDE (Page Directory Entry), that maps given address.
  *
@@ -38,7 +54,7 @@ MM::PageMap::ClearPte(PHARDWARE_PTE PtePointer)
  */
 XTAPI
 PMMPDE
-MM::PageMap::GetPdeAddress(PVOID Address)
+MM::PageMap::GetPdeAddress(IN PVOID Address)
 {
     ULONG Offset;
 
@@ -47,6 +63,42 @@ MM::PageMap::GetPdeAddress(PVOID Address)
     return (PMMPDE)(PageMapInfo.PdeBase + Offset);
 }
 
+/**
+ * Gets the index of the PDE (Page Directory Entry), that maps given address.
+ *
+ * @param Address
+ *        Specifies the virtual address for which to retrieve the corresponding PDE.
+ *
+ * @return This routine returns the index of the PDE.
+ *
+ * @since XT 1.0
+ */
+XTAPI
+ULONG
+MM::PageMap::GetPdeIndex(IN PVOID Address)
+{
+    /* Return PDE index */
+    return ((((ULONG_PTR)(Address)) >> PageMapInfo.PdiShift) & (PageMapInfo.Xpa ? 0x1FF : 0x3FF));
+}
+
+/**
+ * Gets the virtual address that is mapped by a given Page Directory Entry.
+ *
+ * @param PdePointer
+ *        Specifies the address of the PDE.
+ *
+ * @return This routine returns the virtual address mapped by the PDE.
+ *
+ * @since XT 1.0
+ */
+XTAPI
+PVOID
+MM::PageMap::GetPdeVirtualAddress(IN PMMPDE PdePointer)
+{
+    /* Return PDE virtual address */
+    return ((PVOID)((ULONG)(PdePointer) << 20));
+}
+
 /**
  * Gets the address of the PPE (Page Directory Pointer Table Entry), that maps given address.
  *
@@ -59,12 +111,48 @@ MM::PageMap::GetPdeAddress(PVOID Address)
  */
 XTAPI
 PMMPPE
-MM::PageMap::GetPpeAddress(PVOID Address)
+MM::PageMap::GetPpeAddress(IN PVOID Address)
 {
     /* Return zero */
     return (PMMPPE)0;
 }
 
+/**
+ * Gets the index of the PPE (Page Directory Pointer Table Entry), that maps given address.
+ *
+ * @param Address
+ *        Specifies the virtual address for which to retrieve the corresponding PPE.
+ *
+ * @return This routine returns the index of the PPE.
+ *
+ * @since XT 1.0
+ */
+XTAPI
+ULONG
+MM::PageMap::GetPpeIndex(IN PVOID Address)
+{
+    /* Return PPE index */
+    return ((((ULONG_PTR)(Address)) >> MM_PPI_SHIFT) & 0x3) * PageMapInfo.Xpa;
+}
+
+/**
+ * Gets the virtual address that is mapped by a given Page Directory Pointer Table Entry.
+ *
+ * @param PpePointer
+ *        Specifies the virtual address of the PPE.
+ *
+ * @return This routine returns the virtual address mapped by the PPE.
+ *
+ * @since XT 1.0
+ */
+XTAPI
+PVOID
+MM::PageMap::GetPpeVirtualAddress(IN PMMPPE PpePointer)
+{
+    /* Return PPE virtual address */
+    return (PVOID)((ULONG)(PpePointer) << 30);
+}
+
 /**
  * Gets the address of the PTE (Page Table Entry), that maps given address.
  *
@@ -77,13 +165,171 @@ MM::PageMap::GetPpeAddress(PVOID Address)
  */
 XTAPI
 PMMPTE
-MM::PageMap::GetPteAddress(PVOID Address)
+MM::PageMap::GetPteAddress(IN PVOID Address)
 {
     ULONG Offset;
 
     /* Calculate offset and return PTE address */
     Offset = ((((ULONG_PTR)(Address)) >> MM_PTI_SHIFT) << PageMapInfo.PteShift);
-    return (PMMPTE)(MM_PTE_BASE + Offset);
+    return (PMMPTE)(PageMapInfo.PteBase + Offset);
+}
+
+/**
+ * Gets the index of the PTE (Page Table Entry), that maps given address.
+ *
+ * @param Address
+ *        Specifies the virtual address for which to retrieve the corresponding PTE.
+ *
+ * @return This routine returns the index of the PTE.
+ *
+ * @since XT 1.0
+ */
+XTAPI
+ULONG
+MM::PageMap::GetPteIndex(IN PVOID Address)
+{
+    /* Return PTE index */
+    return ((((ULONG_PTR)(Address)) >> MM_PTI_SHIFT) & (PageMapInfo.Xpa ? 0x1FF : 0x3FF));
+}
+
+/**
+ * Gets the virtual address that is mapped by a given Page Table Entry.
+ *
+ * @param PtePointer
+ *        Specifies the virtual address of the PTE.
+ *
+ * @return This routine returns the virtual address mapped by the PTE.
+ *
+ * @since XT 1.0
+ */
+XTAPI
+PVOID
+MM::PageMap::GetPteVirtualAddress(IN PMMPTE PtePointer)
+{
+    /* Return PTE virtual address */
+    return ((PVOID)((ULONG)(PtePointer) << 10));
+}
+
+/**
+ * Gets the status of Extended Paging Address (XPA) mode.
+ *
+ * @return This routine returns TRUE if XPA is enabled, FALSE otherwise.
+ *
+ * @since XT 1.0
+ */
+XTAPI
+BOOLEAN
+MM::PageMap::GetXpaStatus()
+{
+    return PageMapInfo.Xpa;
+}
+
+/**
+ * Advances a PTE pointer by a given number of entries, considering the actual PTE size for PML2.
+ *
+ * @param Pte
+ *        The PTE pointer to advance.
+ *
+ * @param Count
+ *        The number of PTE entries to advance by.
+ *
+ * @return This routine returns the advanced PTE pointer.
+ *
+ * @since XT 1.0
+ */
+XTAPI
+PMMPTE
+MM::PageMapBasic::AdvancePte(IN PMMPTE Pte,
+                             IN ULONG Count)
+{
+    /* Return advanced PTE pointer */
+    return (PMMPTE)((ULONG_PTR)Pte + (Count * sizeof(MMPML2_PTE)));
+}
+
+/**
+ * Gets the next entry in a PTE list.
+ *
+ * @param Pte
+ *        The PTE pointer to get the next entry from.
+ *
+ * @return This routine returns the next entry in the PTE list.
+ *
+ * @since XT 1.0
+ */
+XTAPI
+ULONG_PTR
+MM::PageMapBasic::GetNextEntry(IN PMMPTE Pte)
+{
+    /* Return next entry in PTE list */
+    return Pte->Pml2.List.NextEntry;
+}
+
+/**
+ * Advances a PTE pointer, considering the actual PTE size for PML2.
+ *
+ * @param Pte
+ *        The PTE pointer to advance.
+ *
+ * @return The advanced PTE pointer.
+ *
+ * @since XT 1.0
+ */
+XTAPI
+PMMPTE
+MM::PageMapBasic::GetNextPte(IN PMMPTE Pte)
+{
+    /* Return advanced PTE pointer */
+    return AdvancePte(Pte, 1);
+}
+
+/**
+ * Checks if a PTE list contains only one entry.
+ *
+ * @param Pte
+ *        The PTE pointer to check.
+ *
+ * @return This routine returns TRUE if the PTE list has only one entry, FALSE otherwise.
+ *
+ * @since XT 1.0
+ */
+XTAPI
+BOOLEAN
+MM::PageMapBasic::GetOneEntry(IN PMMPTE Pte)
+{
+    /* Return one entry status */
+    return Pte->Pml2.List.OneEntry;
+}
+
+/**
+ * Gets the page frame number from a corresponding PTE.
+ *
+ * @param Pte
+ *        The PTE pointer to get the page frame number from.
+ *
+ * @return This routine returns the page frame number.
+ *
+ * @since XT 1.0
+ */
+XTAPI
+PFN_NUMBER
+MM::PageMapBasic::GetPageFrameNumber(IN PMMPTE Pte)
+{
+    return Pte->Pml2.Hardware.PageFrameNumber;
+}
+
+/**
+ * Gets the size of a PTE for basic paging (PML2).
+ *
+ * @return This routine returns the size of a PTE.
+ *
+ * @since XT 1.0
+ */
+XTAPI
+ULONG
+MM::PageMapBasic::GetPteSize(VOID)
+{
+    /* Return the size of MMPTE */
+    return sizeof(MMPML2_PTE);
 }
 
 /**
@@ -100,6 +346,9 @@ MM::PageMapBasic::InitializePageMapInfo(VOID)
     /* Set PML2 page map information */
     PageMapInfo.Xpa = FALSE;
 
+    /* Set PML2 empty PTE list mask */
+    PageMapInfo.EmptyPteList = (ULONG)0xFFFFF;
+
     /* Set PML2 base addresses */
     PageMapInfo.PteBase = MM_PTE_BASE;
     PageMapInfo.PdeBase = MM_PDE_LEGACY_BASE;
@@ -121,9 +370,54 @@ MM::PageMapBasic::InitializePageMapInfo(VOID)
  */
 XTAPI
 BOOLEAN
-MM::PageMapBasic::PteValid(PHARDWARE_PTE PtePointer)
+MM::PageMapBasic::PteValid(IN PMMPTE PtePointer)
 {
-    return (BOOLEAN)PtePointer->Pml2.Valid;
+    /* Check if PTE is valid */
+    return (BOOLEAN)PtePointer->Pml2.Hardware.Valid;
+}
+
+/**
+ * Sets the next entry in a PTE list.
+ *
+ * @param Pte
+ *        The PTE pointer to modify.
+ *
+ * @param Value
+ *        The value to set as the next entry.
+ *
+ * @return This routine does not return any value.
+ *
+ * @since XT 1.0
+ */
+XTAPI
+VOID
+MM::PageMapBasic::SetNextEntry(IN PMMPTE Pte,
+                               IN ULONG_PTR Value)
+{
+    /* Set next entry in PTE list */
+    Pte->Pml2.List.NextEntry = Value;
+}
+
+/**
+ * Sets the flag indicating whether a PTE list contains only one entry.
+ *
+ * @param Pte
+ *        The PTE pointer to modify.
+ *
+ * @param Value
+ *        The value to set. TRUE if the list has only one entry, FALSE otherwise.
+ *
+ * @return This routine does not return any value.
+ *
+ * @since XT 1.0
+ */
+XTAPI
+VOID
+MM::PageMapBasic::SetOneEntry(IN PMMPTE Pte,
+                              IN BOOLEAN Value)
+{
+    /* Set one entry status */
+    Pte->Pml2.List.OneEntry = Value;
 }
 
 /**
@@ -135,8 +429,8 @@ MM::PageMapBasic::PteValid(PHARDWARE_PTE PtePointer)
  * @param PageFrameNumber
  *        Physical frame number to map.
  *
- * @param Writable
- *        Indicates whether the page should be writable.
+ * @param AttributesMask
+ *        Specifies the attributes mask to apply to the PTE.
  *
  * @return This routine does not return any value.
  *
@@ -144,13 +438,14 @@ MM::PageMapBasic::PteValid(PHARDWARE_PTE PtePointer)
  */
 XTAPI
 VOID
-MM::PageMapBasic::SetPte(PHARDWARE_PTE PtePointer,
-                         PFN_NUMBER PageFrameNumber,
-                         BOOLEAN Writable)
+MM::PageMapBasic::SetPte(IN PMMPTE PtePointer,
+                         IN PFN_NUMBER PageFrameNumber,
+                         IN ULONG_PTR AttributesMask)
 {
-    PtePointer->Pml2.PageFrameNumber = PageFrameNumber;
-    PtePointer->Pml2.Valid = 1;
-    PtePointer->Pml2.Writable = Writable;
+    /* Set PTE */
+    PtePointer->Pml2.Hardware.PageFrameNumber = PageFrameNumber;
+    PtePointer->Pml2.Hardware.Valid = 1;
+    PtePointer->Long |= AttributesMask;
 }
 
 /**
@@ -171,12 +466,121 @@ MM::PageMapBasic::SetPte(PHARDWARE_PTE PtePointer,
  */
 XTAPI
 VOID
-MM::PageMapBasic::SetPteCaching(PHARDWARE_PTE PtePointer,
-                                BOOLEAN CacheDisable,
-                                BOOLEAN WriteThrough)
+MM::PageMapBasic::SetPteCaching(IN PMMPTE PtePointer,
+                                IN BOOLEAN CacheDisable,
+                                IN BOOLEAN WriteThrough)
 {
-    PtePointer->Pml2.CacheDisable = CacheDisable;
-    PtePointer->Pml2.WriteThrough = WriteThrough;
+    /* Set caching attributes */
+    PtePointer->Pml2.Hardware.CacheDisable = CacheDisable;
+    PtePointer->Pml2.Hardware.WriteThrough = WriteThrough;
+}
+
+/**
+ * Advances a PTE pointer by a given number of entries, considering the actual PTE size for PML3.
+ *
+ * @param Pte
+ *        The PTE pointer to advance.
+ *
+ * @param Count
+ *        The number of PTE entries to advance by.
+ *
+ * @return The advanced PTE pointer.
+ *
+ * @since XT 1.0
+ */
+XTAPI
+PMMPTE
+MM::PageMapXpa::AdvancePte(IN PMMPTE Pte,
+                           IN ULONG Count)
+{
+    /* Return advanced PTE pointer */
+    return (PMMPTE)((ULONG_PTR)Pte + (Count * sizeof(MMPML3_PTE)));
+}
+
+/**
+ * Gets the next entry in a PTE list.
+ *
+ * @param Pte
+ *        The PTE pointer to get the next entry from.
+ *
+ * @return This routine returns the next entry in the PTE list.
+ *
+ * @since XT 1.0
+ */
+XTAPI
+ULONG_PTR
+MM::PageMapXpa::GetNextEntry(IN PMMPTE Pte)
+{
+    /* Return next entry in PTE list */
+    return Pte->Pml3.List.NextEntry;
+}
+
+/**
+ * Advances a PTE pointer, considering the actual PTE size for PML3.
+ *
+ * @param Pte
+ *        The PTE pointer to advance.
+ *
+ * @return The advanced PTE pointer.
+ *
+ * @since XT 1.0
+ */
+XTAPI
+PMMPTE
+MM::PageMapXpa::GetNextPte(IN PMMPTE Pte)
+{
+    /* Return advanced PTE pointer */
+    return AdvancePte(Pte, 1);
+}
+
+/**
+ * Checks if a PTE list contains only one entry.
+ *
+ * @param Pte
+ *        The PTE pointer to check.
+ *
+ * @return This routine returns TRUE if the PTE list has only one entry, FALSE otherwise.
+ *
+ * @since XT 1.0
+ */
+XTAPI
+BOOLEAN
+MM::PageMapXpa::GetOneEntry(IN PMMPTE Pte)
+{
+    /* Return one entry status */
+    return Pte->Pml3.List.OneEntry;
+}
+
+/**
+ * Gets the page frame number from a corresponding PTE.
+ *
+ * @param Pte
+ *        The PTE pointer to get the page frame number from.
+ *
+ * @return This routine returns the page frame number.
+ *
+ * @since XT 1.0
+ */
+XTAPI
+PFN_NUMBER
+MM::PageMapXpa::GetPageFrameNumber(IN PMMPTE Pte)
+{
+    return Pte->Pml3.Hardware.PageFrameNumber;
+}
+
+/**
+ * Gets the size of a PTE for XPA paging (PML3).
+ *
+ * @return This routine returns the size of a PTE.
+ *
+ * @since XT 1.0
+ */
+XTAPI
+ULONG
+MM::PageMapXpa::GetPteSize(VOID)
+{
+    /* Return the size of MMPTE */
+    return sizeof(MMPML3_PTE);
 }
 
 /**
@@ -190,14 +594,17 @@ XTAPI
 VOID
 MM::PageMapXpa::InitializePageMapInfo(VOID)
 {
-    /* Set PML2 page map information */
+    /* Set PML3 page map information */
     PageMapInfo.Xpa = TRUE;
 
-    /* Set PML2 base addresses */
+    /* Set PML3 empty PTE list mask */
+    PageMapInfo.EmptyPteList = (ULONG)0xFFFFFFFF;
+
+    /* Set PML3 base addresses */
     PageMapInfo.PteBase = MM_PTE_BASE;
     PageMapInfo.PdeBase = MM_PDE_BASE;
 
-    /* Set PML2 shift values */
+    /* Set PML3 shift values */
     PageMapInfo.PdiShift = MM_PDI_SHIFT;
     PageMapInfo.PteShift = MM_PTE_SHIFT;
 }
@@ -214,9 +621,53 @@ MM::PageMapXpa::InitializePageMapInfo(VOID)
  */
 XTAPI
 BOOLEAN
-MM::PageMapXpa::PteValid(PHARDWARE_PTE PtePointer)
+MM::PageMapXpa::PteValid(IN PMMPTE PtePointer)
 {
-    return (BOOLEAN)PtePointer->Pml3.Valid;
+    return (BOOLEAN)PtePointer->Pml3.Hardware.Valid;
+}
+
+/**
+ * Sets the next entry in a PTE list.
+ *
+ * @param Pte
+ *        The PTE pointer to modify.
+ *
+ * @param Value
+ *        The value to set as the next entry.
+ *
+ * @return This routine does not return any value.
+ *
+ * @since XT 1.0
+ */
+XTAPI
+VOID
+MM::PageMapXpa::SetNextEntry(IN PMMPTE Pte,
+                             IN ULONG_PTR Value)
+{
+    /* Set next entry in PTE list */
+    Pte->Pml3.List.NextEntry = Value;
+}
+
+/**
+ * Sets the flag indicating whether a PTE list contains only one entry.
+ *
+ * @param Pte
+ *        The PTE pointer to modify.
+ *
+ * @param Value
+ *        The value to set. TRUE if the list has only one entry, FALSE otherwise.
+ *
+ * @return This routine does not return any value.
+ *
+ * @since XT 1.0
+ */
+XTAPI
+VOID
+MM::PageMapXpa::SetOneEntry(IN PMMPTE Pte,
+                            IN BOOLEAN Value)
+{
+    /* Set one entry status */
+    Pte->Pml3.List.OneEntry = Value;
 }
 
 /**
@@ -228,8 +679,8 @@ MM::PageMapXpa::PteValid(PHARDWARE_PTE PtePointer)
  * @param PageFrameNumber
  *        Physical frame number to map.
  *
- * @param Writable
- *        Indicates whether the page should be writable.
+ * @param AttributesMask
+ *        Specifies the attributes mask to apply to the PTE.
  *
  * @return This routine does not return any value.
  *
@@ -237,13 +688,14 @@ MM::PageMapXpa::PteValid(PHARDWARE_PTE PtePointer)
  */
 XTAPI
 VOID
-MM::PageMapXpa::SetPte(PHARDWARE_PTE PtePointer,
-                       PFN_NUMBER PageFrameNumber,
-                       BOOLEAN Writable)
+MM::PageMapXpa::SetPte(IN PMMPTE PtePointer,
+                       IN PFN_NUMBER PageFrameNumber,
+                       IN ULONG_PTR AttributesMask)
 {
-    PtePointer->Pml3.PageFrameNumber = PageFrameNumber;
-    PtePointer->Pml3.Valid = 1;
-    PtePointer->Pml3.Writable = Writable;
+    /* Set PTE */
+    PtePointer->Pml3.Hardware.PageFrameNumber = PageFrameNumber;
+    PtePointer->Pml3.Hardware.Valid = 1;
+    PtePointer->Long |= AttributesMask;
 }
 
 /**
@@ -264,10 +716,11 @@ MM::PageMapXpa::SetPte(PHARDWARE_PTE PtePointer,
  */
 XTAPI
 VOID
-MM::PageMapXpa::SetPteCaching(PHARDWARE_PTE PtePointer,
-                              BOOLEAN CacheDisable,
-                              BOOLEAN WriteThrough)
+MM::PageMapXpa::SetPteCaching(IN PMMPTE PtePointer,
+                              IN BOOLEAN CacheDisable,
+                              IN BOOLEAN WriteThrough)
 {
-    PtePointer->Pml3.CacheDisable = CacheDisable;
-    PtePointer->Pml3.WriteThrough = WriteThrough;
+    /* Set caching attributes */
+    PtePointer->Pml3.Hardware.CacheDisable = CacheDisable;
+    PtePointer->Pml3.Hardware.WriteThrough = WriteThrough;
 }

xtoskrnl/mm/paging.cc

@@ -9,6 +9,28 @@
 #include <xtos.hh>
 
 
+/**
+ * Advances a PTE pointer by a given number of entries, considering the actual PTE size.
+ *
+ * @param Pte
+ *        The PTE pointer to advance.
+ *
+ * @param Count
+ *        The number of PTE entries to advance by.
+ *
+ * @return The advanced PTE pointer.
+ *
+ * @since XT 1.0
+ */
+XTAPI
+PMMPTE
+MM::Paging::AdvancePte(IN PMMPTE Pte,
+                       IN LONG Count)
+{
+    /* Return advanced PTE pointer */
+    return PmlRoutines->AdvancePte(Pte, Count);
+}
+
 /**
  * Clears the contents of a page table entry (PTE).
  *
@@ -21,8 +43,9 @@
  */
 XTAPI
 VOID
-MM::Paging::ClearPte(PHARDWARE_PTE PtePointer)
+MM::Paging::ClearPte(IN PMMPTE PtePointer)
 {
+    /* Clear PTE */
     PmlRoutines->ClearPte(PtePointer);
 }
 
@@ -78,6 +101,92 @@ MM::Paging::FlushTlb(VOID)
     }
 }
 
+/**
+ * Gets the value representing an empty PTE list.
+ *
+ * @return This routine returns the value representing an empty PTE list.
+ *
+ * @since XT 1.0
+ */
+XTAPI
+ULONG_PTR
+MM::Paging::GetEmptyPteList(VOID)
+{
+    /* Return empty PTE list mask */
+    return (ULONG_PTR)PmlRoutines->GetEmptyPteList();
+}
+
+/**
+ * Gets the next entry in a PTE list.
+ *
+ * @param Pte
+ *        The PTE pointer to get the next entry from.
+ *
+ * @return This routine returns the next entry in the PTE list.
+ *
+ * @since XT 1.0
+ */
+XTAPI
+ULONG_PTR
+MM::Paging::GetNextEntry(IN PMMPTE Pte)
+{
+    /* Return next entry in PTE list */
+    return PmlRoutines->GetNextEntry(Pte);
+}
+
+/**
+ * Advances a PTE pointer, considering the actual PTE size.
+ *
+ * @param Pte
+ *        The PTE pointer to advance.
+ *
+ * @return The advanced PTE pointer.
+ *
+ * @since XT 1.0
+ */
+XTAPI
+PMMPTE
+MM::Paging::GetNextPte(IN PMMPTE Pte)
+{
+    /* Return advanced PTE pointer */
+    return PmlRoutines->GetNextPte(Pte);
+}
+
+/**
+ * Checks if a PTE list contains only one entry.
+ *
+ * @param Pte
+ *        The PTE pointer to check.
+ *
+ * @return This routine returns TRUE if the PTE list has only one entry, FALSE otherwise.
+ *
+ * @since XT 1.0
+ */
+XTAPI
+BOOLEAN
+MM::Paging::GetOneEntry(IN PMMPTE Pte)
+{
+    /* Return one entry status */
+    return PmlRoutines->GetOneEntry(Pte);
+}
+
+/**
+ * Gets the page frame number from a corresponding PTE.
+ *
+ * @param Pte
+ *        The PTE pointer to get the page frame number from.
+ *
+ * @return This routine returns the page frame number.
+ *
+ * @since XT 1.0
+ */
+XTAPI
+PFN_NUMBER
+MM::Paging::GetPageFrameNumber(IN PMMPTE Pte)
+{
+    return PmlRoutines->GetPageFrameNumber(Pte);
+}
+
 /**
  * Gets the page map routines for basic paging mode (non-XPA).
  *
@@ -90,6 +199,8 @@ MM::PPAGEMAP
 MM::Paging::GetPageMapBasicRoutines(VOID)
 {
     static MM::PageMapBasic PageMapBasicRoutines;
+
+    /* Return non-XPA page map routines */
     return &PageMapBasicRoutines;
 }
 
@@ -105,6 +216,8 @@ MM::PPAGEMAP
 MM::Paging::GetPageMapXpaRoutines(VOID)
 {
     static MM::PageMapXpa PageMapXpaRoutines;
+
+    /* Return XPA page map routines */
     return &PageMapXpaRoutines;
 }
 
@@ -120,11 +233,30 @@ MM::Paging::GetPageMapXpaRoutines(VOID)
  */
 XTAPI
 PMMPDE
-MM::Paging::GetPdeAddress(PVOID Address)
+MM::Paging::GetPdeAddress(IN PVOID Address)
 {
+    /* Return PDE address */
     return PmlRoutines->GetPdeAddress(Address);
 }
 
+/**
+ * Gets the virtual address that is mapped by a given Page Directory Entry.
+ *
+ * @param PdePointer
+ *        Specifies the address of the PDE.
+ *
+ * @return This routine returns the virtual address mapped by the PDE.
+ *
+ * @since XT 1.0
+ */
+XTAPI
+PVOID
+MM::Paging::GetPdeVirtualAddress(IN PMMPDE PdePointer)
+{
+    /* Return PTE virtual address */
+    return PmlRoutines->GetPdeVirtualAddress(PdePointer);
+}
+
 /**
  * Gets the address of the PPE (Page Directory Pointer Table Entry), that maps given address.
  *
@@ -137,11 +269,30 @@ MM::Paging::GetPdeAddress(PVOID Address)
  */
 XTAPI
 PMMPPE
-MM::Paging::GetPpeAddress(PVOID Address)
+MM::Paging::GetPpeAddress(IN PVOID Address)
 {
+    /* Return PPE address */
     return PmlRoutines->GetPpeAddress(Address);
 }
 
+/**
+ * Gets the virtual address that is mapped by a given Page Directory Pointer Table Entry.
+ *
+ * @param PpePointer
+ *        Specifies the address of the PPE.
+ *
+ * @return This routine returns the virtual address mapped by the PPE.
+ *
+ * @since XT 1.0
+ */
+XTAPI
+PVOID
+MM::Paging::GetPpeVirtualAddress(IN PMMPPE PpePointer)
+{
+    /* Return PTE virtual address */
+    return PmlRoutines->GetPpeVirtualAddress(PpePointer);
+}
+
 /**
  * Gets the address of the PTE (Page Table Entry), that maps given address.
  *
@@ -154,11 +305,59 @@ MM::Paging::GetPpeAddress(PVOID Address)
  */
 XTAPI
 PMMPTE
-MM::Paging::GetPteAddress(PVOID Address)
+MM::Paging::GetPteAddress(IN PVOID Address)
 {
+    /* Return PTE address */
     return PmlRoutines->GetPteAddress(Address);
 }
 
+/**
+ * Gets the size of a PTE.
+ *
+ * @return This routine returns the size of a PTE.
+ *
+ * @since XT 1.0
+ */
+XTAPI
+ULONG
+MM::Paging::GetPteSize(VOID)
+{
+    /* Return the size of MMPTE */
+    return PmlRoutines->GetPteSize();
+}
+
+/**
+ * Gets the virtual address that is mapped by a given Page Table Entry.
+ *
+ * @param PtePointer
+ *        Specifies the address of the PTE.
+ *
+ * @return This routine returns the virtual address mapped by the PTE.
+ *
+ * @since XT 1.0
+ */
+XTAPI
+PVOID
+MM::Paging::GetPteVirtualAddress(IN PMMPTE PtePointer)
+{
+    /* Return PTE virtual address */
+    return PmlRoutines->GetPteVirtualAddress(PtePointer);
+}
+
+/**
+ * Gets current status of eXtended Physical Addressing (XPA).
+ *
+ * @return This routine returns TRUE if PAE or LA57 (XPA) is enabled, or FALSE otherwise.
+ *
+ * @since XT 1.0
+ */
+XTAPI
+BOOLEAN
+MM::Paging::GetXpaStatus()
+{
+    return PmlRoutines->GetXpaStatus();
+}
+
 /**
  * Detects if eXtended Physical Addressing (XPA) is enabled and initializes page map support.
  *
@@ -198,22 +397,20 @@ MM::Paging::InitializePageMapSupport(VOID)
  */
 XTAPI
 BOOLEAN
-MM::Paging::PteValid(PHARDWARE_PTE PtePointer)
+MM::Paging::PteValid(IN PMMPTE PtePointer)
 {
+    /* Check if PTE is valid */
     return PmlRoutines->PteValid(PtePointer);
 }
 
 /**
- * Sets a PML2 page table entry (PTE) with the specified physical page and access flags.
+ * Sets the next entry in a PTE list.
  *
- * @param PtePointer
- *        Pointer to the page table entry (PTE) to set.
+ * @param Pte
+ *        The PTE pointer to modify.
  *
- * @param PageFrameNumber
- *        Physical frame number to map.
- *
- * @param Writable
- *        Indicates whether the page should be writable.
+ * @param Value
+ *        The value to set as the next entry.
  *
  * @return This routine does not return any value.
  *
@@ -221,11 +418,59 @@ MM::Paging::PteValid(PHARDWARE_PTE PtePointer)
  */
 XTAPI
 VOID
-MM::Paging::SetPte(PHARDWARE_PTE PtePointer,
-                   PFN_NUMBER PageFrameNumber,
-                   BOOLEAN Writable)
+MM::Paging::SetNextEntry(IN PMMPTE Pte,
+                         IN ULONG_PTR Value)
 {
-    PmlRoutines->SetPte(PtePointer, PageFrameNumber, Writable);
+    /* Set next entry in PTE list */
+    PmlRoutines->SetNextEntry(Pte, Value);
+}
+
+/**
+ * Sets the flag indicating whether a PTE list contains only one entry.
+ *
+ * @param Pte
+ *        The PTE pointer to modify.
+ *
+ * @param Value
+ *        The value to set. TRUE if the list has only one entry, FALSE otherwise.
+ *
+ * @return This routine does not return any value.
+ *
+ * @since XT 1.0
+ */
+XTAPI
+VOID
+MM::Paging::SetOneEntry(IN PMMPTE Pte,
+                        IN BOOLEAN Value)
+{
+    /* Set one entry status */
+    PmlRoutines->SetOneEntry(Pte, Value);
+}
+
+/**
+ * Sets a Page Table Entry (PTE) with the specified physical page and access flags.
+ *
+ * @param PtePointer
+ *        Pointer to the page table entry (PTE) to set.
+ *
+ * @param PageFrameNumber
+ *        Physical frame number to map.
+ *
+ * @param AttributesMask
+ *        Specifies the attributes mask to apply to the PTE.
+ *
+ * @return This routine does not return any value.
+ *
+ * @since XT 1.0
+ */
+XTAPI
+VOID
+MM::Paging::SetPte(IN PMMPTE PtePointer,
+                   IN PFN_NUMBER PageFrameNumber,
+                   IN ULONG_PTR AttributesMask)
+{
+    /* Set PTE */
+    PmlRoutines->SetPte(PtePointer, PageFrameNumber, AttributesMask);
 }
 
 /**
@@ -246,9 +491,10 @@ MM::Paging::SetPte(PHARDWARE_PTE PtePointer,
  */
 XTAPI
 VOID
-MM::Paging::SetPteCaching(PHARDWARE_PTE PtePointer,
-                          BOOLEAN CacheDisable,
-                          BOOLEAN WriteThrough)
+MM::Paging::SetPteCaching(IN PMMPTE PtePointer,
+                          IN BOOLEAN CacheDisable,
+                          IN BOOLEAN WriteThrough)
 {
+    /* Set caching attributes */
     PmlRoutines->SetPteCaching(PtePointer, CacheDisable, WriteThrough);
 }