141 Commits

Autor	SHA1	Mensagem	Data
belliash	73fc7607cd	There is no need to specify alignment of the structure in the forward reference	2023-02-02 15:37:57 +01:00
belliash	21fbe6febe	Add IDT related definitions	2023-02-01 20:14:10 +01:00
belliash	a761d3125a	Architecture specific initialization prior to processor structures initialization	2023-01-30 20:34:05 +01:00
belliash	6f068513cd	Initial processor block initialization	2023-01-30 19:07:05 +01:00
belliash	ebe6792f2b	Add MSR (Model Specific Registers) values	2023-01-30 17:59:00 +01:00
belliash	7bf4a9ab8d	Initialize boot CPU structures inside kernel on AMD64	2023-01-29 00:45:17 +01:00
belliash	27e2fdf4f2	Introduce architecture library as new kernel subsystem and move selected routines into new subsystem	2023-01-28 10:34:55 +01:00
belliash	e94e50b5d9	Implement HlLoadInterruptDescriptorTable() intrinsics for loading IDT	2023-01-26 20:08:57 +01:00
belliash	3ad3149f80	Add descriptor structure definition	2023-01-25 17:42:35 +01:00
belliash	bfc9db8b6d	Unify KGDTENTRY and KIDTENTRY between architectures as much as possible	2023-01-25 17:35:03 +01:00
belliash	a366de618f	AMD64 Interrupt request levels definitions	2023-01-25 17:08:42 +01:00
belliash	8f348c3954	Add GDT and Segments related definitions for AMD64	2023-01-25 17:05:15 +01:00
belliash	707dc37868	Fix type of Source parameter in HlLoadSegment() routine	2023-01-24 23:08:48 +01:00
belliash	35aa514f95	Implement HlLoadSegment() intrinsics routine	2023-01-24 19:27:18 +01:00
belliash	d3d8d144a0	Implement HlLoadGlobalDescriptorTable() intrinsic	2023-01-23 20:13:51 +01:00
belliash	c81b858757	Implement HlReadGSQuadWord() intrinsic	2023-01-23 19:59:54 +01:00
belliash	f20ab3e52e	Implement HlLoadTaskRegister() for loading TSS segment selector into task register	2023-01-23 15:26:35 +01:00
belliash	fb60625abc	Add more intrinsic routines	2023-01-13 22:32:45 +01:00
belliash	025e05013d	Partially revert last changes	2023-01-10 22:51:38 +01:00
belliash	bac7af8a33	Cleanup data types	2023-01-09 23:07:21 +01:00
belliash	ca1d7ddfe8	Basic context, frames and exceptions definitions	2023-01-07 23:36:50 +01:00
belliash	f74ba62f24	Add GDT, IDT and TSS related structures	2023-01-07 13:33:16 +01:00
belliash	674e69da0e	Cleanup useless externals	2023-01-05 23:38:58 +01:00
belliash	712de4e4e4	XTDK contains headers uniquely identified	2023-01-05 23:28:43 +01:00
belliash	3250ad67aa	Rename header file	2023-01-05 23:09:54 +01:00
belliash	3131aac7a9	Move serial ports I/O address to architecture specific header	2023-01-05 15:58:36 +01:00
belliash	b7e5f1b5c1	Use CR constants instead of hardcoded values	2023-01-04 16:33:28 +01:00
belliash	fcfa575bff	Implement HlReadTimeStampCounter() routine	2022-12-27 23:28:27 +01:00
belliash	f46615f92c	Implement HlInvalidateTlbEntry(), HlReadModelSpecificRegister() and HlWriteModelSpecificRegister() routines	2022-12-27 23:19:33 +01:00
belliash	602d89ef27	Fixes in HlIoPortInShort() and HlIoPortInLong() routines	2022-12-27 22:43:19 +01:00
belliash	9828b23400	Implement HlIoPortInShort(), HlIoPortInLong(), HlIoPortOutShort() and HlIoPortOutLong() routines	2022-12-27 22:26:45 +01:00
belliash	5b75d005a7	Implement HlClearInterruptFlag() and HlSetInterruptFlag() intrinsic routines	2022-12-27 18:54:01 +01:00
belliash	93ad0b4ea0	Set valid calling convention for HAL routines	2022-12-23 14:41:11 +01:00
belliash	3ab1695968	Common routines for reading from and writing to CPU control registers	2022-12-23 14:30:52 +01:00
belliash	6c4496f839	KERNEL_STACK_SIZE should be expressed in bytes as the name suggests, calculate number of pages where needed	2022-12-21 22:24:16 +01:00
belliash	7c38efc802	Update boot sequence and check PE/COFF image machine type compatibility	2022-12-20 19:11:15 +01:00
belliash	9f4db475bb	Implement HlHalt() intrinsic routine and add basic definitions for kernel services	2022-12-11 23:09:35 +01:00
belliash	324a88cc01	Implement HlCpuId() routine and corresponding structures for issueing CPUID instruction	2022-12-11 17:40:56 +01:00
belliash	93fa2aed67	Implement BlMapVirtualMemory() routine for recursive mapping	2022-12-06 23:32:31 +01:00
belliash	b89121fded	Implement routines for accessing and manipulating CPU control registers	2022-12-02 23:03:42 +01:00
belliash	35f2c67138	Basic XT structures	2022-07-29 16:31:59 +02:00