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memmgr ... 356c221e23

Author SHA1 Message Date
PerikiyoXD
356c221e23 Add support for WHPX accelerator on Windows and introduce OVMF Pure EFI firmware 2025-10-09 16:25:52 +02:00
89 changed files with 1017 additions and 7996 deletions
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5
README.md
View File

@@ -53,9 +53,8 @@ implement any environment subsystem to support applications that are strictly wr
* NT drivers compatibility layer
# Requirements
ExectOS is currently in a very early stage of development, so its specific requirements are not fully defined yet.
However, based on the current design, it requires modern EFI hardware. You cannot boot ExectOS on a legacy BIOS
right now, but there are plans to add BIOS support in the future.
ExectOS is in very early development stage, thus its requirements have been not specified yet. However according to its
design, it requires a modern EFI enabled hardware. It is not possible currently to boot ExectOS on a legacy BIOS.
# Source structure
| Directory | Description |

2
boot/bootsect/CMakeLists.txt
View File

@@ -1,8 +1,6 @@
# XT Boot Sector
PROJECT(BOOTSECT)
add_definitions("-DARCH_ESP_SOURCE=\\\"${ARCH}/cpu.S\\\"")
# Compile boot sectors
compile_bootsector(mbrboot ${BOOTSECT_SOURCE_DIR}/mbrboot.S 0x7C00 Start)
compile_bootsector(espboot ${BOOTSECT_SOURCE_DIR}/espboot.S 0x7C00 Start)

144
boot/bootsect/amd64/cpu.S
View File

@@ -1,144 +0,0 @@
/**
* PROJECT: ExectOS
* COPYRIGHT: See COPYING.md in the top level directory
* FILE: boot/bootsect/amd64/cpu.S
* DESCRIPTION: Low-level support for CPU initialization
* DEVELOPERS: Aiken Harris <harraiken91@gmail.com>
*/
BuildPageMap:
/* Generate page map for first 1GB of memory */
pushaw
pushw %es
cld
movw $(0x1000 / 16), %ax
movw %ax, %es
xorw %di, %di
movl $(0x2000 | 0x07), %eax
stosl
xorl %eax, %eax
movw $1021, %cx
rep stosl
movw $(0x2000 / 16), %ax
movw %ax, %es
xorw %di, %di
movl $(0x3000 | 0x07), %eax
stosl
xorl %eax, %eax
movw $1021, %cx
rep stosl
movw $(0x3000 / 16), %ax
movw %ax, %es
xorw %di, %di
movw $512, %cx
movl $0x00000083, %eax
.BuildPageMapLoop:
/* Identity map 512 pages of 2MB */
movl %eax, %es:(%di)
addl $2097152, %eax
addw $0x08, %di
loop .BuildPageMapLoop
popw %es
popaw
ret
InitializeCpu:
/* Check if CPU supports CPUID, long mode and PAE */
pushal
pushfl
popl %eax
movl %eax, %ebx
xorl $0x00200000, %eax
pushl %eax
popfl
pushfl
popl %eax
cmpl %ebx, %eax
je CpuUnsupported
movl $0x01, %eax
cpuid
testl $0x40, %edx
jz CpuUnsupported
movl $0x80000000, %eax
cpuid
cmpl $0x80000000, %eax
jbe CpuUnsupported
movl $0x80000001, %eax
cpuid
testl $0x20000000, %edx
jz CpuUnsupported
popal
call LoadGdt
ret
LoadGdt:
/* Load Global Descriptor Table */
lgdt .GdtPointer
ret
RunStage2:
/* Switch to long mode and pass control to Stage 2 */
call BuildPageMap
call ParseExecutableHeader
xorl %edx, %edx
pushl %edx
pushl %eax
cli
xorw %ax, %ax
movw %ax, %ds
movw %ax, %es
movw %ax, %fs
movw %ax, %gs
movw %ax, %ss
movl %cr4, %eax
orl $0x00A0, %eax
movl %eax, %cr4
movl $0x00001000, %eax
movl %eax, %cr3
movl $0xC0000080, %ecx
rdmsr
orl $0x00000100, %eax
wrmsr
movl %cr0, %eax
orl $0x80000001, %eax
movl %eax, %cr0
ljmp $0x10, $.Stage2LongMode
.code64
.Stage2LongMode:
/* Set segments and stack, then jump to Stage 2 */
movw $0x18, %ax
movw %ax, %ds
movw %ax, %es
movw %ax, %ss
xorw %ax, %ax
movw %ax, %fs
movw %ax, %gs
popq %rax
xorq %rbx, %rbx
xorq %rcx, %rcx
xorq %rdx, %rdx
xorq %rsi, %rsi
xorq %rdi, %rdi
xorq %rbp, %rbp
jmp *%rax
.code16
.GdtDescriptor:
/* Global Descriptor Table */
.quad 0x0000000000000000
.quad 0x0000000000000000
.quad 0x00AF9A000000FFFF
.quad 0x00CF92000000FFFF
.quad 0x00009E000000FFFF
.quad 0x000092000000FFFF
.quad 0x00CF9B000000FFFF
.GdtPointer:
/* Pointer to Global Descriptor Table */
.word .GdtPointer - .GdtDescriptor - 1
.long .GdtDescriptor
.Stage2FileName:
/* Name of Stage 2 executable file */
.ascii "BOOTX64 EFI"

322
boot/bootsect/espboot.S
View File

@@ -121,15 +121,15 @@ VerifyBiosParameterBlock:
ja FsError
ReadExtraCode:
/* Read second VBR sector with extra boot code (3 sectors starting from sector 2) */
/* Read second VBR sector with extra boot code */
movl HiddenSectors - Start(%bp), %eax
addl $0x02, %eax
movw $0x03, %cx
movw $0x01, %cx
xorw %bx, %bx
movw %bx, %es
movw $0x7E00, %bx
call ReadSectors
jmp StartExtraCode
jmp StartSectors
ReadSectors:
/* Check for extended BIOS functions and use it only if available */
@@ -139,23 +139,19 @@ ReadSectors:
movw $0x55AA, %bx
movb DriveNumber - Start(%bp), %dl
int $0x13
jc .ReadCHS
jc ReadCHS
cmpw $0xAA55, %bx
jne .ReadCHS
jne ReadCHS
testb $0x01, %cl
jz .ReadCHS
jz ReadCHS
/* Verify drive size and determine whether to use CHS or LBA */
cmpl %edi, %eax
jnb .ReadLBA
jnb ReadLBA
.ReadCHS:
ReadCHS:
/* Read sectors using CHS */
popal
.CHSLoop:
/* Read sector by sector using CHS */
pushw %cx
pushal
xorl %edx, %edx
movzwl SectorsPerTrack - Start(%bp), %ecx
@@ -173,18 +169,17 @@ ReadSectors:
orb %ah, %cl
movw $0x0201, %ax
int $0x13
popal
popw %cx
jc DiskError
popal
incl %eax
movw %es, %dx
addw $0x20, %dx
movw %dx, %es
loop .CHSLoop
loop ReadCHS
popw %es
ret
.ReadLBA:
ReadLBA:
/* Prepare DAP packet and read sectors using LBA */
popal
pushw %cx
@@ -213,19 +208,19 @@ ReadSectors:
movw %dx, %es
popw %bx
subw %si, %cx
jnz .ReadLBA
jnz ReadLBA
popw %es
ret
DiskError:
/* Display disk error message and reboot */
movw $.MsgDiskError, %si
movw $msgDiskError, %si
call Print
jmp Reboot
FsError:
/* Display FS error message and reboot */
movw $.MsgFsError, %si
movw $msgFsError, %si
call Print
jmp Reboot
@@ -233,297 +228,48 @@ Print:
/* Simple routine to print messages */
lodsb
orb %al, %al
jz .DonePrint
jz DonePrint
movb $0x0E, %ah
movw $0x07, %bx
int $0x10
jmp Print
.DonePrint:
DonePrint:
retw
Reboot:
/* Display a message, wait for a key press and reboot */
movw $.MsgAnyKey, %si
movw $msgAnyKey, %si
call Print
xorw %ax, %ax
int $0x16
int $0x19
.MsgAnyKey:
.ascii "Press any key to restart...\r\n\0"
msgAnyKey:
.ascii "Press any key to restart\r\n"
.MsgDiskError:
.ascii "Disk error!\r\n\0"
msgDiskError:
.ascii "Disk error\r\n"
.MsgFsError:
.ascii "File system error!\r\n\0"
msgFsError:
.ascii "File system error\r\n"
/* Fill the rest of the VBR with zeros and add VBR signature at the end */
.fill (510 - (. - Start)), 1, 0
.word 0xAA55
StartExtraCode:
/* Load XTLDR file from disk */
call LoadStage2
/* Enable A20 gate */
call EnableA20
/* Call architecture specific initialization code */
call InitializeCpu
/* Jump to Stage2 */
call RunStage2
Clear8042:
/* Clear 8042 PS/2 buffer */
nop
nop
nop
nop
inb $0x64, %al
cmpb $0xff, %al
je .Clear8042_Done
testb $0x02, %al
jnz Clear8042
.Clear8042_Done:
ret
EnableA20:
/* Enable A20 gate */
pushaw
call Clear8042
movb $0xD1, %al
outb %al, $0x64
call Clear8042
movb $0xDF, %al
outb %al, $0x60
call Clear8042
movb $0xFF, %al
outb %al, $0x64
call Clear8042
popaw
ret
FindFatEntry:
/* Find a file or directory in the FAT table */
pushw %bx
pushw %cx
pushw %dx
pushw %si
pushw %di
.FindFatCluster:
/* Find FAT32 cluster holding the entry */
cmp $0x0FFFFFF8, %eax
jae .FindEntryFail
pushl %eax
movw $0x0200, %bx
movw %bx, %es
call ReadCluster
popl %eax
movb SectorsPerCluster - Start(%bp), %cl
shlw $0x04, %cx
xorw %di, %di
.FindEntryLoop:
/* Find the entry */
movb %es:(%di), %al
cmpb $0x00, %al
je .FindEntryFail
cmpb $0xE5, %al
je .FindSkipEntry
movb %es:0x0B(%di), %ah
cmpb $0x0F, %ah
je .FindSkipEntry
pushw %di
pushw %si
pushw %cx
movw $0x0B, %cx
repe cmpsb
popw %cx
popw %si
popw %di
jnz .FindSkipEntry
movw %es:0x1A(%di), %ax
movw %es:0x14(%di), %dx
shll $0x10, %edx
orl %edx, %eax
clc
jmp .FindEntryDone
.FindSkipEntry:
/* Skip to the next entry */
addw $0x20, %di
decw %cx
jnz .FindEntryLoop
call GetFatEntry
jmp .FindFatCluster
.FindEntryFail:
/* Error, file/directory not found */
stc
.FindEntryDone:
/* Clean up the stack */
popw %di
popw %si
popw %dx
popw %cx
popw %bx
ret
GetFatEntry:
/* Get FAT32 sector and offset from FAT table */
shll $0x02, %eax
movl %eax, %ecx
xorl %edx, %edx
movzwl BytesPerSector - Start(%bp), %ebx
pushl %ebx
divl %ebx
movzwl ReservedSectors - Start(%bp), %ebx
addl %ebx, %eax
movl HiddenSectors - Start(%bp), %ebx
addl %ebx, %eax
popl %ebx
decl %ebx
andl %ebx, %ecx
movzwl ExtendedFlags - Start(%bp), %ebx
andw $0x0F, %bx
jz LoadFatSector
cmpb FatCopies - Start(%bp), %bl
jae FsError
pushl %eax
movl BigSectorsPerFat - Start(%bp), %eax
mull %ebx
popl %edx
addl %edx, %eax
LoadFatSector:
/* Load FAT32 sector from disk */
pushl %ecx
movw $0x9000, %bx
movw %bx, %es
cmpl %esi, %eax
je .LoadFatSectorDone
movl %eax, %esi
xorw %bx, %bx
movw $0x01, %cx
call ReadSectors
.LoadFatSectorDone:
/* Clean up the stack */
popl %ecx
movl %es:(%ecx), %eax
andl $0x0FFFFFFF, %eax
ret
LoadStage2:
/* Load Stage2 executable, first find file in the path */
movl $0xFFFFFFFF, %esi
pushl %esi
movl 0x7C2C, %eax
movw $.EfiDirName, %si
call FindFatEntry
jc Stage2NotLoaded
movw $.BootDirName, %si
call FindFatEntry
jc Stage2NotLoaded
movw $.Stage2FileName, %si
call FindFatEntry
jc Stage2NotLoaded
popl %esi
/* Load XTLDR file from disk */
cmpl $0x02, %eax
jb FileNotFound
cmpl $0x0FFFFFF8, %eax
jae FileNotFound
movw $(0xF800 / 16), %bx
movw %bx, %es
.LoadStage2Loop:
/* Load file data from disk */
pushl %eax
xorw %bx, %bx
pushw %es
call ReadCluster
popw %es
xorw %bx, %bx
movb SectorsPerCluster - Start(%bp), %bl
shlw $0x05, %bx
movw %es, %ax
addw %bx, %ax
movw %ax, %es
popl %eax
pushw %es
call GetFatEntry
popw %es
cmpl $0x0FFFFFF8, %eax
jb .LoadStage2Loop
ret
ParseExecutableHeader:
/* Parse Stage2 PE/COFF executable header */
pushw %es
movw $(0xF800 / 16), %ax
movw %ax, %es
movl %es:60, %eax
addl $(4 + 20), %eax
movl %es:16(%eax), %eax
addl $0xF800, %eax
popw %es
ret
ReadCluster:
/* Read FAT32 cluster from disk */
decl %eax
decl %eax
xorl %edx, %edx
movzbl SectorsPerCluster - Start(%bp), %ebx
mull %ebx
pushl %eax
xorl %edx, %edx
movzbl FatCopies - Start(%bp), %eax
mull BigSectorsPerFat - Start(%bp)
movzwl ReservedSectors - Start(%bp), %ebx
addl %ebx, %eax
addl HiddenSectors - Start(%bp), %eax
popl %ebx
addl %ebx, %eax
xorw %bx, %bx
movzbw SectorsPerCluster - Start(%bp), %cx
call ReadSectors
ret
/* Include architecture specific code */
.include ARCH_ESP_SOURCE
CpuUnsupported:
/* Display CPU unsupported message and reboot */
popal
movw $.MsgCpuUnsupported, %si
StartSectors:
/* Print message */
movw $msgUnavailable, %si
call Print
jmp Reboot
FileNotFound:
/* Display XTLDR not found message and reboot */
movw $.MsgXtLdrNotFound, %si
call Print
jmp Reboot
/* Wait for key press and reboot */
xorw %ax, %ax
int $0x16
int $0x19
Stage2NotLoaded:
/* Clean up the stack and display XTLDR not found message and reboot */
popl %esi
jmp FileNotFound
msgUnavailable:
.ascii "XTLDR requires EFI-based system!\r\nPress any key to restart\r\n"
.BootDirName:
/* Boot directory name */
.ascii "BOOT "
.EfiDirName:
/* EFI directory name */
.ascii "EFI "
.MsgCpuUnsupported:
.ascii "CPU not supported!\r\n\0"
.MsgXtLdrNotFound:
.ascii "XTLDR Stage2 not found!\r\n\0"
/* Fill the rest of the extra VBR with zeros and add signature */
.fill (2043 - (. - Start)), 1, 0
.ascii "XTLDR"
/* Fill the rest of the extra VBR with zeros */
.fill (1024 - (. - Start)), 1, 0

124
boot/bootsect/i686/cpu.S
View File

@@ -1,124 +0,0 @@
/**
* PROJECT: ExectOS
* COPYRIGHT: See COPYING.md in the top level directory
* FILE: boot/bootsect/i686/cpu.S
* DESCRIPTION: Low-level support for CPU initialization
* DEVELOPERS: Aiken Harris <harraiken91@gmail.com>
*/
BuildPageMap:
/* Generate page map for first 16MB of memory */
pushaw
pushw %es
cld
movw $(0x1000 >> 0x04), %ax
movw %ax, %es
xorw %di, %di
movl $(0x2000 | 0x03), %eax
stosl
movl $(0x3000 | 0x03), %eax
stosl
movl $(0x4000 | 0x03), %eax
stosl
movl $(0x5000 | 0x03), %eax
stosl
xorl %eax, %eax
movw $(1024 - 4), %cx
rep stosl
movl $0x00000003, %eax
movl $4, %edx
movw $(0x2000 >> 0x04), %bx
.BuildPageMapLoop:
/* Identity map 1024 pages of 4KB */
movw %bx, %es
xorw %di, %di
pushl %edx
movw $1024, %cx
.FillPageMapTable:
/* Fill the page table */
movl %eax, %es:(%di)
addl $4096, %eax
addw $0x04, %di
loop .FillPageMapTable
popl %edx
addw $(0x1000 >> 0x04), %bx
decl %edx
jnz .BuildPageMapLoop
popw %es
popaw
ret
InitializeCpu:
/* Check if CPU supports CPUID */
pushal
pushfl
popl %eax
movl %eax, %ebx
xorl $0x00200000, %eax
pushl %eax
popfl
pushfl
popl %eax
cmpl %ebx, %eax
je CpuUnsupported
popal
call LoadGdt
ret
LoadGdt:
/* Load Global Descriptor Table */
lgdt .GdtPointer
ret
RunStage2:
/* Switch to protected mode and pass control to Stage 2 */
call BuildPageMap
call ParseExecutableHeader
pushl %eax
cli
movl %cr0, %eax
orl $0x01, %eax
movl %eax, %cr0
ljmp $0x08, $.Stage2ProtectedMode
.code32
.Stage2ProtectedMode:
/* Set segments and stack, then jump to Stage 2 */
movw $0x10, %ax
movw %ax, %ds
movw %ax, %es
movw %ax, %ss
xorw %ax, %ax
movw %ax, %fs
movw %ax, %gs
popl %eax
xorl %ebx, %ebx
xorl %ecx, %ecx
xorl %edx, %edx
xorl %esi, %esi
xorl %edi, %edi
xorl %ebp, %ebp
movl $0x1000, %ebx
movl %ebx, %cr3
movl %cr0, %ebx
orl $0x80000000, %ebx
movl %ebx, %cr0
jmp *%eax
.code16
.GdtDescriptor:
/* Global Descriptor Table */
.quad 0x0000000000000000
.quad 0x00CF9A000000FFFF
.quad 0x00CF92000000FFFF
.quad 0x00009E000000FFFF
.quad 0x000092000000FFFF
.GdtPointer:
/* Pointer to Global Descriptor Table */
.word .GdtPointer - .GdtDescriptor - 1
.long .GdtDescriptor
.Stage2FileName:
/* Name of Stage 2 executable file */
.ascii "BOOTIA32EFI"

17
boot/bootsect/mbrboot.S
View File

@@ -4,7 +4,6 @@
* FILE: boot/bootsect/amd64/mbrboot.S
* DESCRIPTION: XT Boot Loader MBR boot code
* DEVELOPERS: Rafal Kupiec <belliash@codingworkshop.eu.org>
* Aiken Harris <aiken@codingworkshop.eu.org>
*/
.text
@@ -42,7 +41,7 @@ RealStart:
movw %ax, %ss
/* Print welcome message */
leaw .MsgXtosBoot, %si
leaw msgXtosBoot, %si
call Print
/* Get BIOS boot drive and partition table offset */
@@ -91,19 +90,19 @@ PartitionFound:
InvalidSignature:
/* Invalid signature error */
leaw .MsgInvalidSignature, %si
leaw msgInvalidSignature, %si
call Print
jmp HaltSystem
PartitionNotFound:
/* Active partition not found error */
leaw .MsgPartitionNotFound, %si
leaw msgPartitionNotFound, %si
call Print
jmp HaltSystem
VbrReadFail:
/* VBR read failed error */
leaw .MsgVbrReadFail, %si
leaw msgVbrReadFail, %si
call Print
jmp HaltSystem
@@ -137,16 +136,16 @@ DonePrint:
/* Storage for the LBA start */
.long 0
.MsgInvalidSignature:
msgInvalidSignature:
.asciz "Invalid partition signature!"
.MsgPartitionNotFound:
msgPartitionNotFound:
.asciz "Bootable partition not found!"
.MsgVbrReadFail:
msgVbrReadFail:
.asciz "VBR read failed!"
.MsgXtosBoot:
msgXtosBoot:
.asciz "Starting XTOS boot loader...\r\n"
/* Fill the rest of the MBR with zeros and add MBR signature at the end */

5
boot/xtldr/CMakeLists.txt
View File

@@ -16,7 +16,6 @@ list(APPEND LIBXTLDR_SOURCE
# Specify list of source code files
list(APPEND XTLDR_SOURCE
${XTLDR_SOURCE_DIR}/arch/${ARCH}/memory.cc
${XTLDR_SOURCE_DIR}/biosutil.cc
${XTLDR_SOURCE_DIR}/bootutil.cc
${XTLDR_SOURCE_DIR}/config.cc
${XTLDR_SOURCE_DIR}/console.cc
@@ -39,9 +38,6 @@ add_executable(xtldr ${XTLDR_SOURCE})
# Add linker libraries
target_link_libraries(xtldr libxtos)
# Add linker options
target_link_options(xtldr PRIVATE /ALIGN:512)
# Set proper binary name and install target
if(ARCH STREQUAL "i686")
set(BINARY_NAME "bootia32")
@@ -53,6 +49,5 @@ set_install_target(xtldr efi/boot)
# Set loader entrypoint and subsystem
set_entrypoint(xtldr "BlStartXtLoader")
set_imagebase(xtldr ${BASEADDRESS_XTLDR})
set_linker_map(xtldr TRUE)
set_subsystem(xtldr efi_application)

22
boot/xtldr/arch/amd64/memory.cc
View File

@@ -44,14 +44,6 @@ Memory::BuildPageMap(IN PXTBL_PAGE_MAPPING PageMap,
return Status;
}
/* Add new memory mapping for the page map itself */
Status = MapVirtualMemory(PageMap, Address, Address, 1, LoaderMemoryData);
if(Status != STATUS_EFI_SUCCESS)
{
/* Memory mapping failure */
return Status;
}
/* Assign and zero-fill memory used by page mappings */
PageMap->PtePointer = (PVOID)(UINT_PTR)Address;
RTL::Memory::ZeroMemory(PageMap->PtePointer, EFI_PAGE_SIZE);
@@ -65,7 +57,7 @@ Memory::BuildPageMap(IN PXTBL_PAGE_MAPPING PageMap,
}
/* Map the trampoline code area */
Status = MapVirtualMemory(PageMap, MM_TRAMPOLINE_ADDRESS,MM_TRAMPOLINE_ADDRESS,
Status = MapVirtualMemory(PageMap, (PVOID)MM_TRAMPOLINE_ADDRESS,(PVOID)MM_TRAMPOLINE_ADDRESS,
1, LoaderFirmwareTemporary);
if(Status != STATUS_EFI_SUCCESS)
{
@@ -82,7 +74,7 @@ Memory::BuildPageMap(IN PXTBL_PAGE_MAPPING PageMap,
ModuleInfo = CONTAIN_RECORD(ModulesListEntry, XTBL_MODULE_INFO, Flink);
/* Map module code */
Status = MapVirtualMemory(PageMap, (ULONGLONG)ModuleInfo->ModuleBase, (ULONGLONG)ModuleInfo->ModuleBase,
Status = MapVirtualMemory(PageMap, ModuleInfo->ModuleBase, ModuleInfo->ModuleBase,
EFI_SIZE_TO_PAGES(ModuleInfo->ModuleSize), LoaderFirmwareTemporary);
/* Check if mapping succeeded */
@@ -103,7 +95,7 @@ Memory::BuildPageMap(IN PXTBL_PAGE_MAPPING PageMap,
if(LoaderBase && LoaderSize)
{
/* Map boot loader code as well */
Status = MapVirtualMemory(PageMap, (ULONGLONG)LoaderBase, (ULONGLONG)LoaderBase,
Status = MapVirtualMemory(PageMap, LoaderBase, LoaderBase,
EFI_SIZE_TO_PAGES(LoaderSize), LoaderFirmwareTemporary);
if(Status != STATUS_EFI_SUCCESS)
{
@@ -201,7 +193,7 @@ Memory::GetNextPageTable(IN PXTBL_PAGE_MAPPING PageMap,
}
/* Add new memory mapping */
Status = MapVirtualMemory(PageMap, Address, Address, 1, LoaderMemoryData);
Status = MapVirtualMemory(PageMap, NULLPTR, (PVOID)(UINT_PTR)Address, 1, LoaderMemoryData);
if(Status != STATUS_EFI_SUCCESS)
{
/* Memory mapping failure */
@@ -247,9 +239,9 @@ Memory::GetNextPageTable(IN PXTBL_PAGE_MAPPING PageMap,
XTCDECL
EFI_STATUS
Memory::MapPage(IN PXTBL_PAGE_MAPPING PageMap,
IN ULONGLONG VirtualAddress,
IN ULONGLONG PhysicalAddress,
IN ULONGLONG NumberOfPages)
IN ULONG_PTR VirtualAddress,
IN ULONG_PTR PhysicalAddress,
IN ULONG NumberOfPages)
{
PVOID Pml1, Pml2, Pml3, Pml4, Pml5;
SIZE_T Pml1Entry, Pml2Entry, Pml3Entry, Pml4Entry, Pml5Entry;

14
boot/xtldr/arch/i686/memory.cc
View File

@@ -93,7 +93,7 @@ Memory::BuildPageMap(IN PXTBL_PAGE_MAPPING PageMap,
}
/* Map the trampoline code area */
Status = MapVirtualMemory(PageMap, MM_TRAMPOLINE_ADDRESS,MM_TRAMPOLINE_ADDRESS,
Status = MapVirtualMemory(PageMap, (PVOID)MM_TRAMPOLINE_ADDRESS,(PVOID)MM_TRAMPOLINE_ADDRESS,
1, LoaderFirmwareTemporary);
if(Status != STATUS_EFI_SUCCESS)
{
@@ -110,7 +110,7 @@ Memory::BuildPageMap(IN PXTBL_PAGE_MAPPING PageMap,
ModuleInfo = CONTAIN_RECORD(ModulesListEntry, XTBL_MODULE_INFO, Flink);
/* Map module code */
Status = MapVirtualMemory(PageMap, (ULONGLONG)ModuleInfo->ModuleBase, (ULONGLONG)ModuleInfo->ModuleBase,
Status = MapVirtualMemory(PageMap, ModuleInfo->ModuleBase, ModuleInfo->ModuleBase,
EFI_SIZE_TO_PAGES(ModuleInfo->ModuleSize), LoaderFirmwareTemporary);
/* Check if mapping succeeded */
@@ -131,7 +131,7 @@ Memory::BuildPageMap(IN PXTBL_PAGE_MAPPING PageMap,
if(LoaderBase && LoaderSize)
{
/* Map boot loader code as well */
Status = MapVirtualMemory(PageMap, (ULONGLONG)LoaderBase, (ULONGLONG)LoaderBase,
Status = MapVirtualMemory(PageMap, LoaderBase, LoaderBase,
EFI_SIZE_TO_PAGES(LoaderSize), LoaderFirmwareTemporary);
if(Status != STATUS_EFI_SUCCESS)
{
@@ -252,7 +252,7 @@ Memory::GetNextPageTable(IN PXTBL_PAGE_MAPPING PageMap,
}
/* Add new memory mapping */
Status = MapVirtualMemory(PageMap, (ULONGLONG)NULLPTR, Address, 1, LoaderMemoryData);
Status = MapVirtualMemory(PageMap, NULLPTR, (PVOID)(UINT_PTR)Address, 1, LoaderMemoryData);
if(Status != STATUS_EFI_SUCCESS)
{
/* Memory mapping failure */
@@ -313,9 +313,9 @@ Memory::GetNextPageTable(IN PXTBL_PAGE_MAPPING PageMap,
XTCDECL
EFI_STATUS
Memory::MapPage(IN PXTBL_PAGE_MAPPING PageMap,
IN ULONGLONG VirtualAddress,
IN ULONGLONG PhysicalAddress,
IN ULONGLONG NumberOfPages)
IN ULONG_PTR VirtualAddress,
IN ULONG_PTR PhysicalAddress,
IN ULONG NumberOfPages)
{
SIZE_T PageFrameNumber;
PVOID Pml1, Pml2, Pml3;

190
boot/xtldr/biosutil.cc
View File

@@ -1,190 +0,0 @@
/**
* PROJECT: ExectOS
* COPYRIGHT: See COPYING.md in the top level directory
* FILE: xtldr/biosutil.cc
* DESCRIPTION: Legacy BIOS support
* DEVELOPERS: Aiken Harris <harraiken91@gmail.com>
*/
#include <xtldr.hh>
/**
* Clears the entire screen and moves the cursor to the top-left corner.
*
* @return This routine does not return any value.
*
* @since XT 1.0
*/
XTCDECL
VOID
BiosUtils::ClearScreen()
{
VOLATILE PUSHORT VgaBuffer = (PUSHORT)0xB8000;
USHORT Blank;
UINT Index;
/* Set blank character */
Blank = (0x0F << 8) | L' ';
/* Fill the entire screen with blank characters */
for(Index = 0; Index < VgaWidth * VgaHeight; Index++)
{
VgaBuffer[Index] = Blank;
}
/* Reset cursor position to the top-left corner */
CursorX = 0;
CursorY = 0;
/* Update the hardware cursor position */
UpdateCursor();
}
/**
* Formats the input string and prints it out to the screen.
*
* @param Format
* The formatted string that is to be written to the output.
*
* @param ...
* Depending on the format string, this routine might expect a sequence of additional arguments.
*
* @return This routine does not return any value.
*
* @since XT 1.0
*/
XTCDECL
VOID
BiosUtils::Print(IN PCWSTR Format,
IN ...)
{
RTL_PRINT_CONTEXT PrintContext;
VA_LIST Arguments;
/* Initialise the print contexts */
PrintContext.WriteWideCharacter = PutChar;
/* Initialise the va_list */
VA_START(Arguments, Format);
/* Format and print the string to the stdout */
RTL::WideString::FormatWideString(&PrintContext, (PWCHAR)Format, Arguments);
/* Clean up the va_list */
VA_END(Arguments);
}
/**
* Writes a single wide character to the screen using legacy BIOS VGA text mode.
*
* @param Character
* The wide character to be printed.
*
* @return This routine returns a status code.
*
* @since XT 1.0
*/
XTCDECL
XTSTATUS
BiosUtils::PutChar(IN WCHAR Character)
{
VOLATILE PUSHORT VgaBuffer = (PUSHORT)0xB8000;
USHORT VgaCharacter;
/* Handle special characters */
if(Character == L'\n')
{
/* Move to the next line */
CursorX = 0;
CursorY++;
}
else if(Character == L'\r')
{
/* Move to the beginning of the current line */
CursorX = 0;
}
else
{
/* Print character and move cursor to the right */
VgaCharacter = (0x0F << 8) | (Character & 0xFF);
VgaBuffer[CursorY * VgaWidth + CursorX] = VgaCharacter;
CursorX++;
}
/* Handle moving to the next line if cursor is at the end of the line */
if(CursorX >= VgaWidth)
{
CursorX = 0;
CursorY++;
}
/* Handle scrolling if cursor is at the end of the screen */
if(CursorY >= VgaHeight)
{
ScrollScreen();
CursorY = VgaHeight - 1;
}
/* Update the hardware cursor position */
UpdateCursor();
/* Return success */
return STATUS_EFI_SUCCESS;
}
/**
* Scrolls the entire screen content up by one line and clears the last line.
*
* @return This routine does not return any value.
*
* @since XT 1.0
*/
XTCDECL
VOID
BiosUtils::ScrollScreen()
{
VOLATILE PUSHORT VgaBuffer = (PUSHORT)0xB8000;
USHORT Blank;
UINT Index;
/* Set blank character */
Blank = (0x0F << 8) | L' ';
/* Move every line up by one */
for(Index = 0; Index < (VgaHeight - 1) * VgaWidth; Index++)
{
VgaBuffer[Index] = VgaBuffer[Index + VgaWidth];
}
/* Clear the last line */
for(Index = (VgaHeight - 1) * VgaWidth; Index < VgaHeight * VgaWidth; Index++)
{
VgaBuffer[Index] = Blank;
}
}
/**
* Updates the hardware cursor position on the screen.
*
* @return This routine does not return any value.
*
* @since XT 1.0
*/
XTCDECL
VOID
BiosUtils::UpdateCursor()
{
USHORT Position;
/* Calculate cursor position */
Position = CursorY * VgaWidth + CursorX;
/* Send command to set the high byte of the cursor position */
HL::IoPort::WritePort8(0x3D4, 0x0E);
HL::IoPort::WritePort8(0x3D5, (UCHAR)((Position >> 8) & 0xFF));
/* Send command to set the low byte of the cursor position */
HL::IoPort::WritePort8(0x3D4, 0x0F);
HL::IoPort::WritePort8(0x3D5, (UCHAR)(Position & 0xFF));
}

12
boot/xtldr/data.cc
View File

@@ -10,18 +10,6 @@
#include <xtldr.hh>
/* Legacy BIOS cursor X position */
USHORT BiosUtils::CursorX = 0;
/* Legacy BIOS cursor Y position */
USHORT BiosUtils::CursorY = 0;
/* Legacy BIOS screen height */
CONST USHORT BiosUtils::VgaHeight = 25;
/* Legacy BIOS screen width */
CONST USHORT BiosUtils::VgaWidth = 80;
/* XT Boot Loader menu list */
PLIST_ENTRY Configuration::BootMenuList = NULLPTR;

44
boot/xtldr/includes/xtldr.hh
View File

@@ -15,25 +15,6 @@
#include <libxtos.hh>
class BiosUtils
{
private:
STATIC USHORT CursorX;
STATIC USHORT CursorY;
STATIC CONST USHORT VgaHeight;
STATIC CONST USHORT VgaWidth;
public:
STATIC XTCDECL VOID ClearScreen();
STATIC XTCDECL VOID Print(IN PCWSTR Format,
IN ...);
STATIC XTCDECL XTSTATUS PutChar(IN WCHAR Character);
private:
STATIC XTCDECL VOID ScrollScreen();
STATIC XTCDECL VOID UpdateCursor();
};
class BootUtils
{
public:
@@ -168,7 +149,6 @@ class Memory
STATIC XTCDECL EFI_STATUS FreePages(IN ULONGLONG NumberOfPages,
IN EFI_PHYSICAL_ADDRESS Memory);
STATIC XTCDECL EFI_STATUS FreePool(IN PVOID Memory);
STATIC XTCDECL LOADER_MEMORY_TYPE GetLoaderMemoryType(IN EFI_MEMORY_TYPE EfiMemoryType);
STATIC XTCDECL VOID GetMappingsCount(IN PXTBL_PAGE_MAPPING PageMap,
OUT PULONG NumberOfMappings);
STATIC XTCDECL EFI_STATUS GetMemoryMap(OUT PEFI_MEMORY_MAP MemoryMap);
@@ -178,25 +158,31 @@ class Memory
IN SHORT PageMapLevel,
IN PAGE_SIZE PageSize);
STATIC XTCDECL EFI_STATUS MapEfiMemory(IN OUT PXTBL_PAGE_MAPPING PageMap,
IN ULONG_PTR BaseAddress);
IN OUT PVOID *MemoryMapAddress,
IN PBL_GET_MEMTYPE_ROUTINE GetMemoryTypeRoutine);
STATIC XTCDECL EFI_STATUS MapPage(IN PXTBL_PAGE_MAPPING PageMap,
IN ULONGLONG VirtualAddress,
IN ULONGLONG PhysicalAddress,
IN ULONGLONG NumberOfPages);
IN ULONG_PTR VirtualAddress,
IN ULONG_PTR PhysicalAddress,
IN ULONG NumberOfPages);
STATIC XTCDECL EFI_STATUS MapVirtualMemory(IN OUT PXTBL_PAGE_MAPPING PageMap,
IN ULONGLONG VirtualAddress,
IN ULONGLONG PhysicalAddress,
IN PVOID VirtualAddress,
IN PVOID PhysicalAddress,
IN ULONGLONG NumberOfPages,
IN LOADER_MEMORY_TYPE MemoryType);
STATIC XTCDECL PVOID PhysicalAddressToVirtual(IN PVOID PhysicalAddress,
IN PVOID PhysicalBase,
IN PVOID VirtualBase);
STATIC XTCDECL EFI_STATUS PhysicalListToVirtual(IN PXTBL_PAGE_MAPPING PageMap,
IN OUT PLIST_ENTRY ListHead,
IN PVOID PhysicalBase,
IN PVOID VirtualBase);
private:
STATIC XTCDECL LOADER_MEMORY_TYPE GetLoaderMemoryType(IN EFI_MEMORY_TYPE EfiMemoryType);
STATIC XTCDECL EFI_STATUS GetNextPageTable(IN PXTBL_PAGE_MAPPING PageMap,
IN PVOID PageTable,
IN SIZE_T Entry,
OUT PVOID *NextPageTable);
STATIC XTCDECL EFI_STATUS MapDescriptor(IN OUT PXTBL_PAGE_MAPPING PageMap,
IN PEFI_MEMORY_DESCRIPTOR Descriptor,
IN ULONG_PTR BaseAddress);
STATIC XTCDECL EFI_STATUS SelfMapPml(IN PXTBL_PAGE_MAPPING PageMap,
IN ULONG_PTR SelfMapAddress);
};

289
boot/xtldr/memory.cc
View File

@@ -4,7 +4,6 @@
* FILE: xtldr/memory.cc
* DESCRIPTION: XT Boot Loader memory management
* DEVELOPERS: Rafal Kupiec <belliash@codingworkshop.eu.org>
* Aiken Harris <harraiken91@gmail.com>
*/
#include <xtldr.hh>
@@ -309,69 +308,17 @@ Memory::InitializePageMap(OUT PXTBL_PAGE_MAPPING PageMap,
PageMap->PageSize = PageSize;
}
/**
* Maps memory descriptor to the page mapping structure.
*
* @param PageMap
* Supplies a pointer to the page mapping structure.
*
* @param Descriptor
* Supplies a pointer to EFI memory descriptor, which will be mapped.
*
* @param BaseAddress
* Supplies a base address, where EFI memory will be mapped.
*
* @return This routine returns a status code.
*
* @since XT 1.0
*/
XTCDECL
EFI_STATUS
Memory::MapDescriptor(IN OUT PXTBL_PAGE_MAPPING PageMap,
IN PEFI_MEMORY_DESCRIPTOR Descriptor,
IN ULONG_PTR BaseAddress)
{
LOADER_MEMORY_TYPE MemoryType;
/* Skip EFI reserved memory */
if(Descriptor->Type == EfiReservedMemoryType)
{
/* Skip EFI reserved memory */
return STATUS_EFI_SUCCESS;
}
/* Convert EFI memory type into XTLDR memory type */
MemoryType = Memory::GetLoaderMemoryType((EFI_MEMORY_TYPE)Descriptor->Type);
/* Do memory mappings depending on memory type */
if(MemoryType == LoaderFirmwareTemporary)
{
/* Map EFI firmware code */
return Memory::MapVirtualMemory(PageMap, Descriptor->PhysicalStart,
Descriptor->PhysicalStart, Descriptor->NumberOfPages, MemoryType);
}
else if(MemoryType != LoaderFree)
{
/* Add any non-free memory mappings based on provided base address */
return Memory::MapVirtualMemory(PageMap, (BaseAddress | Descriptor->PhysicalStart), Descriptor->PhysicalStart,
Descriptor->NumberOfPages, MemoryType);
}
else
{
/* Map all other memory as loader free */
return Memory::MapVirtualMemory(PageMap, (ULONGLONG)NULLPTR, Descriptor->PhysicalStart,
Descriptor->NumberOfPages, LoaderFree);
}
}
/**
* Adds EFI memory mapping to the page mapping structure.
*
* @param PageMap
* Supplies a pointer to the page mapping structure.
*
* @param BaseAddress
* Supplies a base address, where EFI memory will be mapped.
* @param MemoryMapAddress
* Supplies a virtual address, where EFI memory will be mapped.
*
* @param GetMemoryTypeRoutine
* Supplies a pointer to the routine which will be used to match EFI memory type to the OS memory type.
*
* @return This routine returns a status code.
*
@@ -380,15 +327,27 @@ Memory::MapDescriptor(IN OUT PXTBL_PAGE_MAPPING PageMap,
XTCDECL
EFI_STATUS
Memory::MapEfiMemory(IN OUT PXTBL_PAGE_MAPPING PageMap,
IN ULONG_PTR BaseAddress)
IN OUT PVOID *MemoryMapAddress,
IN PBL_GET_MEMTYPE_ROUTINE GetMemoryTypeRoutine)
{
PEFI_MEMORY_DESCRIPTOR Descriptor;
LOADER_MEMORY_TYPE MemoryType;
PEFI_MEMORY_MAP MemoryMap;
SIZE_T DescriptorCount;
ULONGLONG MaxAddress;
PUCHAR VirtualAddress;
EFI_STATUS Status;
SIZE_T Index;
/* Set virtual address as specified in argument */
VirtualAddress = (PUCHAR)*MemoryMapAddress;
/* Check if custom memory type routine is specified */
if(GetMemoryTypeRoutine == NULLPTR)
{
/* Use default memory type routine */
GetMemoryTypeRoutine = GetLoaderMemoryType;
}
/* Allocate and zero-fill buffer for EFI memory map */
AllocatePool(sizeof(EFI_MEMORY_MAP), (PVOID*)&MemoryMap);
RTL::Memory::ZeroMemory(MemoryMap, sizeof(EFI_MEMORY_MAP));
@@ -408,43 +367,68 @@ Memory::MapEfiMemory(IN OUT PXTBL_PAGE_MAPPING PageMap,
/* Iterate through all descriptors from the memory map */
for(Index = 0; Index < DescriptorCount; Index++)
{
/* Check page map level */
if(PageMap->PageMapLevel == 2)
/* Make sure descriptor does not start beyond lowest physical page */
if(Descriptor->PhysicalStart <= MAXUINT_PTR)
{
/* Limit physical address to 4GB in legacy mode */
MaxAddress = 0xFFFFFFFF;
}
else if(PageMap->PageMapLevel == 3)
{
/* Limit physical address to 64GB in PAE mode */
MaxAddress = 0xFFFFFFFFF;
}
/* Check page map level */
if(PageMap->PageMapLevel == 2 || PageMap->PageMapLevel == 3)
{
/* Check if physical address starts beyond limit */
if(Descriptor->PhysicalStart > MaxAddress)
/* Skip EFI reserved memory */
if(Descriptor->Type == EfiReservedMemoryType)
{
/* Go to the next descriptor */
Descriptor = (PEFI_MEMORY_DESCRIPTOR)((PUCHAR)Descriptor + MemoryMap->DescriptorSize);
continue;
}
/* Check if memory descriptor exceeds the lowest physical page */
if(Descriptor->PhysicalStart + (Descriptor->NumberOfPages << EFI_PAGE_SHIFT) > MaxAddress)
/* Check if preparing page map level 2 (non-PAE i686) */
if(PageMap->PageMapLevel == 2)
{
/* Truncate memory descriptor to maximum supported address */
Descriptor->NumberOfPages = (((ULONGLONG)MaxAddress) - Descriptor->PhysicalStart) >> EFI_PAGE_SHIFT;
}
}
/* Check if physical address starts beyond 4GB */
if(Descriptor->PhysicalStart > 0xFFFFFFFF)
{
/* Go to the next descriptor */
Descriptor = (PEFI_MEMORY_DESCRIPTOR)((PUCHAR)Descriptor + MemoryMap->DescriptorSize);
continue;
}
/* Map this descriptor and make sure it succeeded */
Status = MapDescriptor(PageMap, Descriptor, BaseAddress);
if(Status != STATUS_EFI_SUCCESS)
{
/* Mapping failed */
return Status;
/* Check if memory descriptor exceeds the lowest physical page */
if(Descriptor->PhysicalStart + (Descriptor->NumberOfPages << EFI_PAGE_SHIFT) > MAXULONG)
{
/* Truncate memory descriptor to the 4GB */
Descriptor->NumberOfPages = (((ULONGLONG)MAXULONG + 1) - Descriptor->PhysicalStart) >> EFI_PAGE_SHIFT;
}
}
/* Convert EFI memory type into XTLDR memory type */
MemoryType = GetMemoryTypeRoutine((EFI_MEMORY_TYPE)Descriptor->Type);
/* Do memory mappings depending on memory type */
if(MemoryType == LoaderFirmwareTemporary)
{
/* Map EFI firmware code */
Status = MapVirtualMemory(PageMap, (PVOID)Descriptor->PhysicalStart,
(PVOID)Descriptor->PhysicalStart, Descriptor->NumberOfPages, MemoryType);
}
else if(MemoryType != LoaderFree)
{
/* Add any non-free memory mapping */
Status = MapVirtualMemory(PageMap, VirtualAddress, (PVOID)Descriptor->PhysicalStart,
Descriptor->NumberOfPages, MemoryType);
/* Calculate next valid virtual address */
VirtualAddress += Descriptor->NumberOfPages * EFI_PAGE_SIZE;
}
else
{
/* Map all other memory as loader free */
Status = MapVirtualMemory(PageMap, NULLPTR, (PVOID)Descriptor->PhysicalStart,
Descriptor->NumberOfPages, LoaderFree);
}
/* Make sure memory mapping succeeded */
if(Status != STATUS_EFI_SUCCESS)
{
/* Mapping failed */
return Status;
}
}
/* Grab next descriptor */
@@ -452,7 +436,7 @@ Memory::MapEfiMemory(IN OUT PXTBL_PAGE_MAPPING PageMap,
}
/* Always map first page */
Status = MapVirtualMemory(PageMap, (ULONGLONG)NULLPTR, 0, 1, LoaderFirmwarePermanent);
Status = MapVirtualMemory(PageMap, NULLPTR, (PVOID)0, 1, LoaderFirmwarePermanent);
if(Status != STATUS_EFI_SUCCESS)
{
/* Mapping failed */
@@ -460,7 +444,7 @@ Memory::MapEfiMemory(IN OUT PXTBL_PAGE_MAPPING PageMap,
}
/* Map BIOS ROM and VRAM */
Status = MapVirtualMemory(PageMap, (ULONGLONG)NULLPTR, 0xA0000, 0x60, LoaderFirmwarePermanent);
Status = MapVirtualMemory(PageMap, NULLPTR, (PVOID)0xA0000, 0x60, LoaderFirmwarePermanent);
if(Status != STATUS_EFI_SUCCESS)
{
/* Mapping failed */
@@ -468,6 +452,7 @@ Memory::MapEfiMemory(IN OUT PXTBL_PAGE_MAPPING PageMap,
}
/* Store next valid virtual address and return success */
*MemoryMapAddress = VirtualAddress;
return STATUS_EFI_SUCCESS;
}
@@ -496,13 +481,13 @@ Memory::MapEfiMemory(IN OUT PXTBL_PAGE_MAPPING PageMap,
XTCDECL
EFI_STATUS
Memory::MapVirtualMemory(IN OUT PXTBL_PAGE_MAPPING PageMap,
IN ULONGLONG VirtualAddress,
IN ULONGLONG PhysicalAddress,
IN PVOID VirtualAddress,
IN PVOID PhysicalAddress,
IN ULONGLONG NumberOfPages,
IN LOADER_MEMORY_TYPE MemoryType)
{
PXTBL_MEMORY_MAPPING Mapping1, Mapping2, Mapping3;
ULONGLONG PhysicalAddressEnd, PhysicalAddress2End;
PVOID PhysicalAddressEnd, PhysicalAddress2End;
PLIST_ENTRY ListEntry, MappingListEntry;
SIZE_T NumberOfMappedPages;
EFI_STATUS Status;
@@ -522,7 +507,7 @@ Memory::MapVirtualMemory(IN OUT PXTBL_PAGE_MAPPING PageMap,
Mapping1->MemoryType = MemoryType;
/* Calculate the end of the physical address */
PhysicalAddressEnd = PhysicalAddress + (NumberOfPages * EFI_PAGE_SIZE) - 1;
PhysicalAddressEnd = (PVOID)((ULONG_PTR)PhysicalAddress + (NumberOfPages * EFI_PAGE_SIZE) - 1);
/* Iterate through all the mappings already set to insert new mapping at the correct place */
ListEntry = PageMap->MemoryMap.Flink;
@@ -530,7 +515,7 @@ Memory::MapVirtualMemory(IN OUT PXTBL_PAGE_MAPPING PageMap,
{
/* Take a mapping from the list and calculate its end of physical address */
Mapping2 = CONTAIN_RECORD(ListEntry, XTBL_MEMORY_MAPPING, ListEntry);
PhysicalAddress2End = Mapping2->PhysicalAddress + (Mapping2->NumberOfPages * EFI_PAGE_SIZE) - 1;
PhysicalAddress2End = (PVOID)((ULONG_PTR)Mapping2->PhysicalAddress + (Mapping2->NumberOfPages * EFI_PAGE_SIZE) - 1);
/* Check if new mapping is a subset of an existing mapping */
if(Mapping1->PhysicalAddress >= Mapping2->PhysicalAddress && PhysicalAddressEnd <= PhysicalAddress2End)
@@ -554,7 +539,7 @@ Memory::MapVirtualMemory(IN OUT PXTBL_PAGE_MAPPING PageMap,
}
/* Calculate number of pages for this mapping */
NumberOfMappedPages = (PhysicalAddress2End - PhysicalAddressEnd) / EFI_PAGE_SIZE;
NumberOfMappedPages = ((PUCHAR)PhysicalAddress2End - (PUCHAR)PhysicalAddressEnd) / EFI_PAGE_SIZE;
if(NumberOfMappedPages > 0)
{
/* Pages associated to the mapping, allocate memory for it */
@@ -566,8 +551,8 @@ Memory::MapVirtualMemory(IN OUT PXTBL_PAGE_MAPPING PageMap,
}
/* Set mapping fields and insert it on the top */
Mapping3->PhysicalAddress = PhysicalAddressEnd + 1;
Mapping3->VirtualAddress = (ULONGLONG)NULLPTR;
Mapping3->PhysicalAddress = (PUCHAR)PhysicalAddressEnd + 1;
Mapping3->VirtualAddress = NULLPTR;
Mapping3->NumberOfPages = NumberOfMappedPages;
Mapping3->MemoryType = Mapping2->MemoryType;
RTL::LinkedList::InsertHeadList(&Mapping2->ListEntry, &Mapping3->ListEntry);
@@ -576,7 +561,7 @@ Memory::MapVirtualMemory(IN OUT PXTBL_PAGE_MAPPING PageMap,
/* Calculate number of pages and the end of the physical address */
Mapping2->NumberOfPages = ((PUCHAR)PhysicalAddressEnd + 1 -
(PUCHAR)Mapping2->PhysicalAddress) / EFI_PAGE_SIZE;
PhysicalAddress2End = Mapping2->PhysicalAddress + (Mapping2->NumberOfPages * EFI_PAGE_SIZE) - 1;
PhysicalAddress2End = (PVOID)((ULONG_PTR)Mapping2->PhysicalAddress + (Mapping2->NumberOfPages * EFI_PAGE_SIZE) - 1);
}
/* Check if they overlap */
@@ -603,7 +588,7 @@ Memory::MapVirtualMemory(IN OUT PXTBL_PAGE_MAPPING PageMap,
/* Set mapping fields and insert it on the top */
Mapping3->PhysicalAddress = Mapping1->PhysicalAddress;
Mapping3->VirtualAddress = (ULONGLONG)NULLPTR;
Mapping3->VirtualAddress = NULLPTR;
Mapping3->NumberOfPages = NumberOfMappedPages;
Mapping3->MemoryType = Mapping2->MemoryType;
RTL::LinkedList::InsertHeadList(&Mapping2->ListEntry, &Mapping3->ListEntry);
@@ -612,7 +597,7 @@ Memory::MapVirtualMemory(IN OUT PXTBL_PAGE_MAPPING PageMap,
/* Calculate number of pages and the end of the physical address */
Mapping2->NumberOfPages = ((PUCHAR)Mapping1->PhysicalAddress -
(PUCHAR)Mapping2->PhysicalAddress) / EFI_PAGE_SIZE;
PhysicalAddress2End = Mapping2->PhysicalAddress + (Mapping2->NumberOfPages * EFI_PAGE_SIZE) - 1;
PhysicalAddress2End = (PVOID)((ULONG_PTR)Mapping2->PhysicalAddress + (Mapping2->NumberOfPages * EFI_PAGE_SIZE) - 1);
}
/* Check if mapping is really needed */
@@ -657,3 +642,105 @@ Memory::MapVirtualMemory(IN OUT PXTBL_PAGE_MAPPING PageMap,
/* Return success */
return STATUS_EFI_SUCCESS;
}
/**
* Converts physical address to virtual address based on physical base and virtual base.
*
* @param PhysicalAddress
* Specifies physical address that will be converted to virtual address.
*
* @param PhysicalBase
* Supplies a physical base address.
*
* @param VirtualBase
* Supplies a virtual base address.
*
* @return This routine returns a mapped virtual address.
*
* @since XT 1.0
*/
XTCDECL
PVOID
Memory::PhysicalAddressToVirtual(IN PVOID PhysicalAddress,
IN PVOID PhysicalBase,
IN PVOID VirtualBase)
{
/* Convert physical address to virtual address */
return (PUCHAR)VirtualBase + ((PUCHAR)PhysicalAddress - (PUCHAR)PhysicalBase);
}
/**
* Converts whole linked list addressing from physical to virtual for future use after enabling paging.
*
* @param PageMap
* Supplies a pointer to the page mapping structure.
*
* @param ListHead
* Supplies a pointer to a structure that serves as the list header.
*
* @param PhysicalBase
* Supplies a physical base address.
*
* @param VirtualBase
* Supplies a virtual base address.
*
* @return This routine returns a status code.
*
* @since XT 1.0
*/
XTCDECL
EFI_STATUS
Memory::PhysicalListToVirtual(IN PXTBL_PAGE_MAPPING PageMap,
IN OUT PLIST_ENTRY ListHead,
IN PVOID PhysicalBase,
IN PVOID VirtualBase)
{
PLIST_ENTRY ListEntry, NextEntry;
/* Make sure list is properly initialized */
if(ListHead->Flink == 0 || ListHead->Blink == 0)
{
/* List not initialized, return error code */
return STATUS_EFI_INVALID_PARAMETER;
}
/* Iterate through all elements */
ListEntry = ListHead->Flink;
while(ListEntry != ListHead)
{
/* Save physical address of the next element */
NextEntry = ListEntry->Flink;
/* Convert the address of this element to VirtualAddress */
if(ListEntry->Blink == ListHead)
{
/* Find virtual address of list head */
ListEntry->Blink = (PLIST_ENTRY)GetVirtualAddress(PageMap, ListEntry->Blink);
}
else
{
/* Convert list entry */
ListEntry->Blink = (PLIST_ENTRY)PhysicalAddressToVirtual(ListEntry->Blink, (PVOID)PhysicalBase, VirtualBase);
}
if(ListEntry->Flink == ListHead)
{
/* Convert list head */
ListEntry->Flink = ListHead->Flink->Blink;
}
else
{
/* Convert list entry */
ListEntry->Flink = (PLIST_ENTRY)PhysicalAddressToVirtual(ListEntry->Flink, (PVOID)PhysicalBase, VirtualBase);
}
/* Get to the next element*/
ListEntry = NextEntry;
}
/* Convert list head */
ListHead->Blink = (PLIST_ENTRY)PhysicalAddressToVirtual(ListHead->Blink, (PVOID)PhysicalBase, VirtualBase);
ListHead->Flink = (PLIST_ENTRY)PhysicalAddressToVirtual(ListHead->Flink, (PVOID)PhysicalBase, VirtualBase);
/* Return success */
return STATUS_EFI_SUCCESS;
}

2
boot/xtldr/modules/pecoff/pecoff.cc
View File

@@ -729,11 +729,11 @@ PeCoff::RelocateLoadedImage(IN PPECOFF_IMAGE_CONTEXT Image)
}
else
{
/* Check if loaded 32-bit PE32 image should be relocated */
/* Set relocation data directory and image base address */
DataDirectory = &Image->PeHeader->OptionalHeader32.DataDirectory[PECOFF_IMAGE_DIRECTORY_ENTRY_BASERELOC];
ImageBase = Image->PeHeader->OptionalHeader32.ImageBase;
/* Check if loaded 32-bit PE32 image should be relocated */
if(Image->PeHeader->OptionalHeader32.NumberOfRvaAndSizes <= PECOFF_IMAGE_DIRECTORY_ENTRY_BASERELOC ||
DataDirectory->VirtualAddress == 0 || DataDirectory->Size < sizeof(PECOFF_IMAGE_BASE_RELOCATION))
{

14
boot/xtldr/modules/xtos_o/amd64/memory.cc
View File

@@ -156,20 +156,6 @@ Xtos::EnablePaging(IN PXTBL_PAGE_MAPPING PageMap)
return STATUS_EFI_SUCCESS;
}
/**
* Returns the base address of the memory mapping.
*
* @return This routine returns the base address of the memory mapping.
*
* @since XT 1.0
*/
XTCDECL
ULONG_PTR
Xtos::GetBaseMappingAddress(VOID)
{
return KSEG0_BASE;
}
/**
* Maps the page table for hardware layer addess space.
*

29
boot/xtldr/modules/xtos_o/i686/memory.cc
View File

@@ -44,20 +44,6 @@ Xtos::DeterminePagingLevel(IN CONST PWCHAR Parameters)
return 2;
}
/**
* Returns the base address of the memory mapping.
*
* @return This routine returns the base address of the memory mapping.
*
* @since XT 1.0
*/
XTCDECL
ULONG_PTR
Xtos::GetBaseMappingAddress(VOID)
{
return KSEG0_BASE;
}
/**
* Builds the actual memory mapping page table and enables paging. This routine exits EFI boot services as well.
*
@@ -73,22 +59,9 @@ EFI_STATUS
Xtos::EnablePaging(IN PXTBL_PAGE_MAPPING PageMap)
{
EFI_STATUS Status;
ULONG_PTR SelfMapAddress;
/* Initialize self map address */
if(PageMap->PageMapLevel == 3)
{
/* For PML3 (PAE) use PTE base address */
SelfMapAddress = MM_PTE_BASE;
}
else
{
/* For PML2 (PAE disabled) use legacy PDE base address */
SelfMapAddress = MM_PDE_LEGACY_BASE;
}
/* Build page map */
Status = XtLdrProtocol->Memory.BuildPageMap(PageMap, SelfMapAddress);
Status = XtLdrProtocol->Memory.BuildPageMap(PageMap, MM_PTE_BASE);
if(Status != STATUS_EFI_SUCCESS)
{
/* Failed to build page map */

30
boot/xtldr/modules/xtos_o/includes/xtos.hh
View File

@@ -33,34 +33,44 @@ class Xtos
IN PEFI_SYSTEM_TABLE SystemTable);
private:
STATIC XTCDECL EFI_STATUS AddVirtualMemoryMapping(IN PLIST_ENTRY MemoryMappings,
IN PVOID VirtualAddress,
IN PVOID PhysicalAddress,
IN UINT NumberOfPages,
IN LOADER_MEMORY_TYPE MemoryType);
STATIC XTCDECL LOADER_MEMORY_TYPE ConvertEfiMemoryType(IN EFI_MEMORY_TYPE EfiMemoryType);
STATIC XTCDECL ULONG DeterminePagingLevel(IN CONST PWCHAR Parameters);
STATIC XTCDECL EFI_STATUS EnablePaging(IN PXTBL_PAGE_MAPPING PageMap);
STATIC XTCDECL ULONG_PTR GetBaseMappingAddress(VOID);
STATIC XTCDECL VOID GetDisplayInformation(OUT PSYSTEM_RESOURCE_FRAMEBUFFER FrameBufferResource,
IN PEFI_PHYSICAL_ADDRESS FrameBufferBase,
IN PULONG_PTR FrameBufferSize,
IN PXTBL_FRAMEBUFFER_MODE_INFORMATION FrameBufferModeInfo);
STATIC XTCDECL EFI_STATUS GetMemoryDescriptorList(IN PXTBL_PAGE_MAPPING PageMap,
IN PVOID *VirtualAddress,
OUT PLIST_ENTRY MemoryDescriptorList);
STATIC XTCDECL EFI_STATUS GetSystemResourcesList(IN PXTBL_PAGE_MAPPING PageMap,
IN PVOID *VirtualAddress,
OUT PLIST_ENTRY SystemResourcesList);
STATIC XTCDECL EFI_STATUS GetVirtualAddress(IN PLIST_ENTRY MemoryMappings,
IN PVOID PhysicalAddress,
OUT PVOID *VirtualAddress);
STATIC XTCDECL EFI_STATUS InitializeApicBase(IN PXTBL_PAGE_MAPPING PageMap);
STATIC XTCDECL EFI_STATUS InitializeLoaderBlock(IN PXTBL_PAGE_MAPPING PageMap,
OUT PKERNEL_INITIALIZATION_BLOCK *KernelParameters,
IN PVOID *VirtualAddress,
IN PXTBL_BOOT_PARAMETERS Parameters);
STATIC XTCDECL EFI_STATUS InitializeVirtualMemory(IN OUT PLIST_ENTRY MemoryMappings,
IN OUT PVOID *MemoryMapAddress);
STATIC XTCDECL EFI_STATUS LoadModule(IN PEFI_FILE_HANDLE BootDir,
IN PWCHAR FileName,
IN PVOID VirtualAddress,
IN LOADER_MEMORY_TYPE MemoryType,
IN OUT PXTBL_PAGE_MAPPING PageMap,
OUT PPECOFF_IMAGE_CONTEXT *ImageContext);
STATIC XTCDECL EFI_STATUS MapHardwareMemoryPool(IN PXTBL_PAGE_MAPPING PageMap);
STATIC XTCDECL EFI_STATUS MapMemory(IN OUT PXTBL_PAGE_MAPPING PageMap,
IN ULONGLONG Address,
IN ULONG NumberOfPages,
IN LOADER_MEMORY_TYPE MemoryType,
IN BOOLEAN KernelMapping);
STATIC XTCDECL PVOID PhysicalAddressToVirtual(PVOID PhysicalAddress);
STATIC XTCDECL EFI_STATUS PhysicalListToVirtual(IN OUT PLIST_ENTRY ListHead);
STATIC XTCDECL EFI_STATUS MapVirtualMemory(IN PLIST_ENTRY MemoryMappings,
IN UINT_PTR VirtualAddress,
IN UINT_PTR PhysicalAddress,
IN UINT NumberOfPages,
IN OUT PVOID *PtePointer);
STATIC XTCDECL EFI_STATUS RunBootSequence(IN PEFI_FILE_HANDLE BootDir,
IN PXTBL_BOOT_PARAMETERS Parameters);
};

250
boot/xtldr/modules/xtos_o/xtos.cc
View File

@@ -191,6 +191,7 @@ Xtos::GetDisplayInformation(OUT PSYSTEM_RESOURCE_FRAMEBUFFER FrameBufferResource
XTCDECL
EFI_STATUS
Xtos::GetMemoryDescriptorList(IN PXTBL_PAGE_MAPPING PageMap,
IN PVOID *VirtualAddress,
OUT PLIST_ENTRY MemoryDescriptorList)
{
EFI_PHYSICAL_ADDRESS Address;
@@ -205,7 +206,7 @@ Xtos::GetMemoryDescriptorList(IN PXTBL_PAGE_MAPPING PageMap,
return Status;
}
Status = MapMemory(PageMap, Address, Pages, LoaderMemoryData, TRUE);
Status = XtLdrProtocol->Memory.MapVirtualMemory(PageMap, *VirtualAddress, (PVOID)Address, Pages, LoaderMemoryData);
if(Status != STATUS_EFI_SUCCESS)
{
XtLdrProtocol->Memory.FreePages(Address, Pages);
@@ -213,14 +214,13 @@ Xtos::GetMemoryDescriptorList(IN PXTBL_PAGE_MAPPING PageMap,
}
PVOID PhysicalBase = (PVOID)Address;
PVOID CurrentDescriptor = PhysicalBase;
PLIST_ENTRY ListEntry;
ListEntry = PageMap->MemoryMap.Flink;
while(ListEntry != &PageMap->MemoryMap)
{
PXTBL_MEMORY_MAPPING MemoryMapping = CONTAIN_RECORD(ListEntry, XTBL_MEMORY_MAPPING, ListEntry);
PLOADER_MEMORY_DESCRIPTOR MemoryDescriptor = (PLOADER_MEMORY_DESCRIPTOR)CurrentDescriptor;
PLOADER_MEMORY_DESCRIPTOR MemoryDescriptor = (PLOADER_MEMORY_DESCRIPTOR)Address;
MemoryDescriptor->MemoryType = MemoryMapping->MemoryType;
MemoryDescriptor->BasePage = (UINT_PTR)MemoryMapping->PhysicalAddress / EFI_PAGE_SIZE;
@@ -228,11 +228,11 @@ Xtos::GetMemoryDescriptorList(IN PXTBL_PAGE_MAPPING PageMap,
XtLdrProtocol->LinkedList.InsertTail(MemoryDescriptorList, &MemoryDescriptor->ListEntry);
CurrentDescriptor = (PUINT8)CurrentDescriptor + sizeof(LOADER_MEMORY_DESCRIPTOR);
Address = Address + sizeof(LOADER_MEMORY_DESCRIPTOR);
ListEntry = ListEntry->Flink;
}
PhysicalListToVirtual(MemoryDescriptorList);
XtLdrProtocol->Memory.PhysicalListToVirtual(PageMap, MemoryDescriptorList, PhysicalBase, *VirtualAddress);
return STATUS_EFI_SUCCESS;
}
@@ -240,6 +240,7 @@ Xtos::GetMemoryDescriptorList(IN PXTBL_PAGE_MAPPING PageMap,
XTCDECL
EFI_STATUS
Xtos::GetSystemResourcesList(IN PXTBL_PAGE_MAPPING PageMap,
IN PVOID *VirtualAddress,
OUT PLIST_ENTRY SystemResourcesList)
{
XTSTATUS Status;
@@ -256,6 +257,7 @@ Xtos::GetSystemResourcesList(IN PXTBL_PAGE_MAPPING PageMap,
PSYSTEM_RESOURCE_ACPI AcpiResource;
ULONGLONG Pages;
EFI_PHYSICAL_ADDRESS Address;
PVOID PhysicalBase, VirtualBase;
Pages = (ULONGLONG)EFI_SIZE_TO_PAGES(sizeof(SYSTEM_RESOURCE_ACPI) + sizeof(SYSTEM_RESOURCE_FRAMEBUFFER));
@@ -264,14 +266,19 @@ Xtos::GetSystemResourcesList(IN PXTBL_PAGE_MAPPING PageMap,
{
return Status;
}
Status = MapMemory(PageMap, Address, Pages, LoaderFirmwarePermanent, TRUE);
Status = XtLdrProtocol->Memory.MapVirtualMemory(PageMap, *VirtualAddress, (PVOID)Address, Pages, LoaderFirmwarePermanent);
if(Status != STATUS_EFI_SUCCESS)
{
XtLdrProtocol->Memory.FreePages(Address, Pages);
return Status;
}
PhysicalBase = (PVOID)Address;
VirtualBase = *VirtualAddress;
/* Calculate next valid virtual address */
*VirtualAddress = (PUINT8)*VirtualAddress + (Pages * EFI_PAGE_SIZE);
AcpiResource = (PSYSTEM_RESOURCE_ACPI)Address;
XtLdrProtocol->Memory.ZeroMemory(AcpiResource, sizeof(SYSTEM_RESOURCE_ACPI));
@@ -287,7 +294,7 @@ Xtos::GetSystemResourcesList(IN PXTBL_PAGE_MAPPING PageMap,
AcpiResource->Header.ResourceSize = sizeof(SYSTEM_RESOURCE_ACPI);
/* Get APIC and XSDP/RSDP addresses */
AcpiProtocol->GetApicBase((PVOID *)&AcpiResource->ApicBase);
AcpiProtocol->GetApicBase(&AcpiResource->ApicBase);
AcpiProtocol->GetAcpiDescriptionPointer(&AcpiResource->Header.PhysicalAddress);
/* No need to map ACPI */
@@ -326,19 +333,21 @@ Xtos::GetSystemResourcesList(IN PXTBL_PAGE_MAPPING PageMap,
FrameBufferPages = EFI_SIZE_TO_PAGES(FbSize);
/* Rewrite framebuffer address by using virtual address */
FrameBufferResource->Header.VirtualAddress = PhysicalAddressToVirtual(FrameBufferResource->Header.PhysicalAddress);
FrameBufferResource->Header.VirtualAddress = *VirtualAddress;
/* Map frame buffer memory */
XtLdrProtocol->Memory.MapVirtualMemory(PageMap, (ULONGLONG)FrameBufferResource->Header.VirtualAddress,
(ULONGLONG)FrameBufferResource->Header.PhysicalAddress,
FrameBufferPages, LoaderHardwareCachedMemory);
XtLdrProtocol->Memory.MapVirtualMemory(PageMap, FrameBufferResource->Header.VirtualAddress,
FrameBufferResource->Header.PhysicalAddress,
FrameBufferPages, LoaderFirmwarePermanent);
/* Close FrameBuffer protocol */
XtLdrProtocol->Protocol.Close(&ProtocolHandle, &FrameBufGuid);
*VirtualAddress = (PUINT8)*VirtualAddress + (FrameBufferPages * EFI_PAGE_SIZE);
XtLdrProtocol->LinkedList.InsertTail(SystemResourcesList, &FrameBufferResource->Header.ListEntry);
PhysicalListToVirtual(SystemResourcesList);
XtLdrProtocol->Memory.PhysicalListToVirtual(PageMap, SystemResourcesList, PhysicalBase, VirtualBase);
return STATUS_EFI_SUCCESS;
}
@@ -360,7 +369,7 @@ Xtos::InitializeApicBase(IN PXTBL_PAGE_MAPPING PageMap)
EFI_GUID AcpiGuid = XT_ACPI_PROTOCOL_GUID;
PXTBL_ACPI_PROTOCOL AcpiProtocol;
EFI_HANDLE ProtocolHandle;
EFI_PHYSICAL_ADDRESS ApicBaseAddress;
PVOID ApicBaseAddress;
EFI_STATUS Status;
/* Open ACPI protocol */
@@ -372,7 +381,7 @@ Xtos::InitializeApicBase(IN PXTBL_PAGE_MAPPING PageMap)
}
/* Get APIC base address */
Status = AcpiProtocol->GetApicBase((PVOID *)&ApicBaseAddress);
Status = AcpiProtocol->GetApicBase(&ApicBaseAddress);
if(Status != STATUS_EFI_SUCCESS)
{
/* Failed to get APIC base address */
@@ -380,21 +389,18 @@ Xtos::InitializeApicBase(IN PXTBL_PAGE_MAPPING PageMap)
}
/* Map APIC base address */
XtLdrProtocol->Memory.MapVirtualMemory(PageMap, APIC_BASE, ApicBaseAddress, 1, LoaderFirmwarePermanent);
XtLdrProtocol->Memory.MapVirtualMemory(PageMap, (PVOID)APIC_BASE, ApicBaseAddress, 1, LoaderFirmwarePermanent);
return STATUS_EFI_SUCCESS;
}
/**
* Initializes and maps the kernel initialization block.
*
* @param PageMap
* Supplies a pointer to the page map.
* @param MemoryMappings
* Supplies a pointer to linked list containing all memory mappings.
*
* @param KernelParameters
* Returns a pointer to the kernel initialization block.
*
* @param Parameters
* Supplies a list of input parameters passed to the kernel.
* @param VirtualAddress
* Supplies a pointer to the next valid, free and available virtual address.
*
* @return This routine returns a status code.
*
@@ -403,7 +409,7 @@ Xtos::InitializeApicBase(IN PXTBL_PAGE_MAPPING PageMap)
XTCDECL
EFI_STATUS
Xtos::InitializeLoaderBlock(IN PXTBL_PAGE_MAPPING PageMap,
OUT PKERNEL_INITIALIZATION_BLOCK *KernelParameters,
IN PVOID *VirtualAddress,
IN PXTBL_BOOT_PARAMETERS Parameters)
{
PKERNEL_INITIALIZATION_BLOCK LoaderBlock;
@@ -411,7 +417,6 @@ Xtos::InitializeLoaderBlock(IN PXTBL_PAGE_MAPPING PageMap,
EFI_STATUS Status;
UINT BlockPages;
UINT ParametersSize;
ULONGLONG LoaderBlockVa;
/* Calculate size of parameters */
ParametersSize = (XtLdrProtocol->WideString.Length(Parameters->Parameters, 0) + 1) * sizeof(WCHAR);
@@ -444,29 +449,25 @@ Xtos::InitializeLoaderBlock(IN PXTBL_PAGE_MAPPING PageMap,
// LoaderBlock->FirmwareInformation.EfiFirmware.EfiVersion = EfiSystemTable->Hdr.Revision;
LoaderBlock->FirmwareInformation.EfiFirmware.EfiRuntimeServices = NULLPTR;
/* Get the KSEG0-based virtual address for the loader block */
LoaderBlockVa = (ULONGLONG)PhysicalAddressToVirtual(LoaderBlock);
*KernelParameters = (PKERNEL_INITIALIZATION_BLOCK)LoaderBlockVa;
/* Copy parameters to kernel initialization block */
LoaderBlock->KernelParameters = (PWCHAR)(LoaderBlockVa + sizeof(KERNEL_INITIALIZATION_BLOCK));
LoaderBlock->KernelParameters = (PWCHAR)((UINT_PTR)*VirtualAddress + sizeof(KERNEL_INITIALIZATION_BLOCK));
XtLdrProtocol->Memory.CopyMemory((PVOID)((UINT_PTR)LoaderBlock + sizeof(KERNEL_INITIALIZATION_BLOCK)),
Parameters->Parameters,
ParametersSize);
/* Map kernel initialization block */
Status = MapMemory(PageMap, (ULONGLONG)LoaderBlock, BlockPages, LoaderSystemBlock, TRUE);
if(Status != STATUS_EFI_SUCCESS)
{
return Status;
}
XtLdrProtocol->Memory.MapVirtualMemory(PageMap, *VirtualAddress, (PVOID)LoaderBlock,
BlockPages, LoaderSystemBlock);
/* Calculate next valid virtual address */
*VirtualAddress = (PUINT8)*VirtualAddress + (BlockPages * EFI_PAGE_SIZE);
XtLdrProtocol->LinkedList.InitializeHead(&LoaderBlock->SystemResourcesListHead);
GetSystemResourcesList(PageMap, &LoaderBlock->SystemResourcesListHead);
GetSystemResourcesList(PageMap, VirtualAddress, &LoaderBlock->SystemResourcesListHead);
/* Initialize memory descriptor list */
XtLdrProtocol->LinkedList.InitializeHead(&LoaderBlock->MemoryDescriptorListHead);
GetMemoryDescriptorList(PageMap, &LoaderBlock->MemoryDescriptorListHead);
GetMemoryDescriptorList(PageMap, VirtualAddress, &LoaderBlock->MemoryDescriptorListHead);
/* Return success */
return STATUS_EFI_SUCCESS;
@@ -507,12 +508,12 @@ Xtos::InitializeModule(IN EFI_HANDLE ImageHandle,
* @param FileName
* An on disk filename of the module that will be loaded.
*
* @param VirtualAddress
* Optional virtual address pointing to the memory area where PE/COFF file will be loaded.
*
* @param MemoryType
* Supplies the type of memory to be assigned to the memory descriptor.
*
* @param PageMap
* Supplies pointer to the memory area where memory mappings will be stored.
*
* @param ImageContext
* Supplies pointer to the memory area where loaded PE/COFF image context will be stored.
*
@@ -524,8 +525,8 @@ XTCDECL
EFI_STATUS
Xtos::LoadModule(IN PEFI_FILE_HANDLE SystemDir,
IN PWCHAR FileName,
IN PVOID VirtualAddress,
IN LOADER_MEMORY_TYPE MemoryType,
IN OUT PXTBL_PAGE_MAPPING PageMap,
OUT PPECOFF_IMAGE_CONTEXT *ImageContext)
{
PEFI_FILE_HANDLE ModuleHandle;
@@ -544,8 +545,8 @@ Xtos::LoadModule(IN PEFI_FILE_HANDLE SystemDir,
return Status;
}
/* Load the PE/COFF image file into memory */
Status = PeCoffProtocol->LoadImage(ModuleHandle, MemoryType, NULLPTR, (PVOID*)ImageContext);
/* Load the PE/COFF image file */
Status = PeCoffProtocol->LoadImage(ModuleHandle, MemoryType, VirtualAddress, (PVOID*)ImageContext);
if(Status != STATUS_EFI_SUCCESS)
{
/* Unable to load the file */
@@ -553,15 +554,6 @@ Xtos::LoadModule(IN PEFI_FILE_HANDLE SystemDir,
return Status;
}
/* Relocate the PE/COFF image file */
Status = PeCoffProtocol->RelocateImage(*ImageContext, GetBaseMappingAddress() | (ULONGLONG)(*ImageContext)->PhysicalAddress);
if(Status != STATUS_EFI_SUCCESS)
{
/* Unable to relocate the file */
XtLdrProtocol->Debug.Print(L"ERROR: Failed to relocate '%S'\n", FileName);
return Status;
}
/* Close image file */
ModuleHandle->Close(ModuleHandle);
@@ -583,133 +575,9 @@ Xtos::LoadModule(IN PEFI_FILE_HANDLE SystemDir,
XtLdrProtocol->Debug.Print(L"WARNING: Loaded PE/COFF image with non-XT subsystem set\n");
}
/* Ensure that page map is provided */
if(PageMap != NULLPTR)
{
/* Add kernel image memory mapping */
Status = MapMemory(PageMap, (ULONGLONG)(*ImageContext)->PhysicalAddress,
(*ImageContext)->ImagePages, LoaderSystemCode, TRUE);
if(Status != STATUS_EFI_SUCCESS)
{
/* Failed to map kernel image memory */
return Status;
}
}
/* Print debug message */
XtLdrProtocol->Debug.Print(L"Loaded '%S' at PA: %P, VA: %P\n", FileName, (*ImageContext)->PhysicalAddress,
PhysicalAddressToVirtual((*ImageContext)->VirtualAddress));
/* Return success */
return STATUS_EFI_SUCCESS;
}
/**
* Adds a physical to virtual address mapping.
*
* @param PageMap
* Supplies a pointer to the page mapping structure.
*
* @param PhysicalAddress
* Supplies a physical address which will be mapped.
*
* @param NumberOfPages
* Supplies a number of pages that will be mapped.
*
* @param MemoryType
* Supplies the type of mapped memory that will be assigned to the memory descriptor.
*
* @param KernelMapping
* Supplies a flag that indicates if mapping should be done in kernel mode or if identity mapping should be used.
*
* @return This routine returns a status code.
*
* @since XT 1.0
*/
XTCDECL
EFI_STATUS
Xtos::MapMemory(IN OUT PXTBL_PAGE_MAPPING PageMap,
IN ULONGLONG Address,
IN ULONG NumberOfPages,
IN LOADER_MEMORY_TYPE MemoryType,
IN BOOLEAN KernelMapping)
{
ULONGLONG BaseAddress;
/* Check if kernel mode mapping */
if(KernelMapping)
{
/* Map memory based on kernel base address */
BaseAddress = GetBaseMappingAddress();
}
else
{
/* Use identity mapping */
BaseAddress = (ULONGLONG)NULLPTR;
}
/* Map memory and return status code */
return XtLdrProtocol->Memory.MapVirtualMemory(PageMap, BaseAddress + Address, Address, NumberOfPages, MemoryType);
}
/**
* Converts physical address to virtual address.
*
* @param PhysicalAddress
* Specifies physical address that will be converted to virtual address.
*
* @return This routine returns a mapped virtual address.
*
* @since XT 1.0
*/
XTCDECL
PVOID
Xtos::PhysicalAddressToVirtual(PVOID PhysicalAddress)
{
return (PVOID)((ULONG_PTR)PhysicalAddress | GetBaseMappingAddress());
}
/**
* Converts whole linked list addressing from physical to virtual for future use after enabling paging.
*
* @param ListHead
* Supplies a pointer to a structure that serves as the list header.
*
* @return This routine returns a status code.
*
* @since XT 1.0
*/
XTCDECL
EFI_STATUS
Xtos::PhysicalListToVirtual(IN OUT PLIST_ENTRY ListHead)
{
PLIST_ENTRY ListEntry, NextEntry;
/* Make sure list is properly initialized */
if(ListHead->Flink == 0 || ListHead->Blink == 0)
{
/* List not initialized, return error code */
return STATUS_EFI_INVALID_PARAMETER;
}
/* Iterate through the list */
ListEntry = ListHead->Flink;
while(ListEntry != ListHead)
{
/* Store the next entry */
NextEntry = ListEntry->Flink;
/* Convert the list entry */
ListEntry->Flink = (PLIST_ENTRY)PhysicalAddressToVirtual(ListEntry->Flink);
ListEntry->Blink = (PLIST_ENTRY)PhysicalAddressToVirtual(ListEntry->Blink);
/* Get the next element */
ListEntry = NextEntry;
}
/* Convert the list head */
ListHead->Flink = (PLIST_ENTRY)PhysicalAddressToVirtual(ListHead->Flink);
ListHead->Blink = (PLIST_ENTRY)PhysicalAddressToVirtual(ListHead->Blink);
XtLdrProtocol->Debug.Print(L"Loaded %S at PA: %P, VA: %P\n", FileName,
(*ImageContext)->PhysicalAddress, (*ImageContext)->VirtualAddress);
/* Return success */
return STATUS_EFI_SUCCESS;
@@ -739,6 +607,7 @@ Xtos::RunBootSequence(IN PEFI_FILE_HANDLE BootDir,
PXTBL_FRAMEBUFFER_PROTOCOL FrameBufProtocol;
PPECOFF_IMAGE_CONTEXT ImageContext = NULLPTR;
PEFI_LOADED_IMAGE_PROTOCOL ImageProtocol;
PVOID VirtualAddress, VirtualMemoryArea;
PXT_ENTRY_POINT KernelEntryPoint;
EFI_HANDLE ProtocolHandle;
EFI_STATUS Status;
@@ -759,23 +628,39 @@ Xtos::RunBootSequence(IN PEFI_FILE_HANDLE BootDir,
/* Close FrameBuffer protocol */
XtLdrProtocol->Protocol.Close(&ProtocolHandle, &FrameBufGuid);
/* Set base virtual memory area for the kernel mappings */
VirtualMemoryArea = (PVOID)KSEG0_BASE;
VirtualAddress = (PVOID)(KSEG0_BASE + KSEG0_KERNEL_BASE);
/* Initialize virtual memory mappings */
XtLdrProtocol->Memory.InitializePageMap(&PageMap, DeterminePagingLevel(Parameters->Parameters), Size4K);
Status = XtLdrProtocol->Memory.MapEfiMemory(&PageMap, GetBaseMappingAddress());
Status = XtLdrProtocol->Memory.MapEfiMemory(&PageMap, &VirtualMemoryArea, NULLPTR);
if(Status != STATUS_EFI_SUCCESS)
{
return Status;
}
/* Load the kernel */
Status = LoadModule(BootDir, Parameters->KernelFile, LoaderSystemCode, &PageMap, &ImageContext);
Status = LoadModule(BootDir, Parameters->KernelFile, VirtualAddress, LoaderSystemCode, &ImageContext);
if(Status != STATUS_EFI_SUCCESS)
{
/* Failed to load the kernel */
return Status;
}
/* Add kernel image memory mapping */
Status = XtLdrProtocol->Memory.MapVirtualMemory(&PageMap, ImageContext->VirtualAddress,
ImageContext->PhysicalAddress, ImageContext->ImagePages,
LoaderSystemCode);
if(Status != STATUS_EFI_SUCCESS)
{
return Status;
}
/* Set next valid virtual address right after the kernel */
VirtualAddress = (PUINT8)VirtualAddress + (ImageContext->ImagePages * EFI_PAGE_SIZE);
/* Find and map APIC base address */
Status = InitializeApicBase(&PageMap);
if(Status != STATUS_EFI_SUCCESS)
@@ -785,8 +670,11 @@ Xtos::RunBootSequence(IN PEFI_FILE_HANDLE BootDir,
return Status;
}
/* Store virtual address of kernel initialization block for future kernel call */
KernelParameters = (PKERNEL_INITIALIZATION_BLOCK)VirtualAddress;
/* Setup and map kernel initialization block */
Status = InitializeLoaderBlock(&PageMap, &KernelParameters, Parameters);
Status = InitializeLoaderBlock(&PageMap, &VirtualAddress, Parameters);
if(Status != STATUS_EFI_SUCCESS)
{
/* Failed to setup kernel initialization block */

2
boot/xtldr/protocol.cc
View File

@@ -1066,6 +1066,8 @@ Protocol::InstallXtLoaderProtocol()
LoaderProtocol.Memory.MapPage = Memory::MapPage;
LoaderProtocol.Memory.MapVirtualMemory = Memory::MapVirtualMemory;
LoaderProtocol.Memory.MoveMemory = RTL::Memory::MoveMemory;
LoaderProtocol.Memory.PhysicalAddressToVirtual = Memory::PhysicalAddressToVirtual;
LoaderProtocol.Memory.PhysicalListToVirtual = Memory::PhysicalListToVirtual;
LoaderProtocol.Memory.SetMemory = RTL::Memory::SetMemory;
LoaderProtocol.Memory.ZeroMemory = RTL::Memory::ZeroMemory;
LoaderProtocol.Protocol.Close = CloseProtocol;

9
boot/xtldr/xtldr.cc
View File

@@ -236,15 +236,6 @@ BlStartXtLoader(IN EFI_HANDLE ImageHandle,
PWCHAR Modules;
EFI_STATUS Status;
/* Check if system is EFI-based and provided parameters are valid */
if(ImageHandle == NULLPTR || SystemTable == NULLPTR)
{
/* Invalid parameters, print error message using BIOS calls and hang */
BiosUtils::ClearScreen();
BiosUtils::Print(L"XTLDR requires EFI-based system!");
for(;;);
}
/* Initialize XTLDR and */
XtLoader::InitializeBootLoader(ImageHandle, SystemTable);

51
configure.ps1
View File

@@ -4,41 +4,48 @@
# DESCRIPTION: Project configuration script for preparing the build environment
# DEVELOPERS: Aiken Harris <harraiken91@gmail.com>
# Check XTchain
if (-not $env:XTCVER) {
Write-Error "XTChain not detected or corrupted!"
Write-Host "XTChain not detected or corrupted!"
exit 1
}
# Set target architecture defaulting to amd64
$ARCH = if ($env:TARGET) { $env:TARGET } else { "amd64" }
# Set target build type defaulting to Debug
$env:BUILD_TYPE = if ($env:BUILD_TYPE -in @("Debug", "Release")) { $env:BUILD_TYPE } else { "Debug" }
# Set variables
$EXECTOS_SOURCE_DIR = $PSScriptRoot
$EXECTOS_BINARY_DIR = Join-Path $EXECTOS_SOURCE_DIR "build-$ARCH-$($env:BUILD_TYPE.ToLower())"
# Create build directory
if (-not (Test-Path $EXECTOS_BINARY_DIR)) {
Write-Host "Creating build directory: $EXECTOS_BINARY_DIR"
New-Item -ItemType Directory -Path $EXECTOS_BINARY_DIR -Force | Out-Null
# Set target architecture
if ($env:TARGET) {
$ARCH = $env:TARGET
} else {
$ARCH = "amd64"
}
Set-Location $EXECTOS_BINARY_DIR
# Set target build type
if (-not $env:BUILD_TYPE) {
$env:BUILD_TYPE = "DEBUG"
}
# Set variables
$EXECTOS_SOURCE_DIR = (Get-Location).Path
$EXECTOS_BINARY_DIR = "build-$($ARCH)-$($env:BUILD_TYPE.ToLower())"
# Create directories if needed
if ($EXECTOS_SOURCE_DIR -eq (Get-Location).Path) {
Write-Host "Creating directories in $EXECTOS_BINARY_DIR"
New-Item -ItemType Directory -Path $EXECTOS_BINARY_DIR -Force | Out-Null
Set-Location -Path $EXECTOS_BINARY_DIR
}
# Delete old cache
Remove-Item "CMakeCache.txt", "host-tools/CMakeCache.txt" -ErrorAction SilentlyContinue
Remove-Item -Path "CMakeCache.txt" -ErrorAction SilentlyContinue
Remove-Item -Path "host-tools/CMakeCache.txt" -ErrorAction SilentlyContinue
# Configure project using CMake
& cmake -G Ninja "-DARCH:STRING=$ARCH" "-DBUILD_TYPE:STRING=$($env:BUILD_TYPE)" $EXECTOS_SOURCE_DIR
& cmake -G Ninja -DARCH:STRING=$($ARCH) -DBUILD_TYPE:STRING=$($env:BUILD_TYPE) $EXECTOS_SOURCE_DIR
# Check if configuration succeeded
if ($LASTEXITCODE -ne 0) {
Write-Error "Configure script failed."
Write-Host "Configure script failed."
exit 1
} else {
"$($ARCH)" | Out-File -Encoding ASCII -NoNewline build.arch
Write-Host "Configure script completed. Enter '$EXECTOS_BINARY_DIR' directory and execute 'xbuild' to build ExectOS."
}
$ARCH | Out-File -Encoding ASCII -NoNewline "build.arch"
Write-Host "Configure completed. Run 'xbuild' to build ExectOS."

1
sdk/cmake/baseaddress/amd64.cmake
View File

@@ -1,3 +1,2 @@
# Set base addresses for all modules
set(BASEADDRESS_XTLDR 0x000000000000F800)
set(BASEADDRESS_XTOSKRNL 0x0000000140000000)

1
sdk/cmake/baseaddress/i686.cmake
View File

@@ -1,3 +1,2 @@
# Set base addresses for all modules
set(BASEADDRESS_XTLDR 0x0000F800)
set(BASEADDRESS_XTOSKRNL 0x00400000)

70
sdk/cmake/emulation.cmake
View File

@@ -23,57 +23,49 @@ endif()
find_program(QEMU_EMULATOR ${QEMU_COMMAND})
if(QEMU_EMULATOR)
if(CMAKE_HOST_LINUX)
# This target starts up a QEMU+OVMF virtual machine using KVM accelerator
add_custom_target(testefikvm
DEPENDS install
COMMAND ${QEMU_COMMAND} -name "ExectOS-${ARCH}-EFI-KVM" -machine type=q35,kernel_irqchip=on,accel=kvm,mem-merge=off,vmport=off -enable-kvm -cpu host,-hypervisor,+topoext
-smp 2,sockets=1,cores=1,threads=2 -m 4G -overcommit mem-lock=off -rtc clock=host,base=localtime,driftfix=none
-bios ${EXECTOS_SOURCE_DIR}/sdk/firmware/ovmf_${ARCH}.fd
-hda fat:rw:${EXECTOS_BINARY_DIR}/output/binaries
-boot menu=on -d int -M smm=off -no-reboot -no-shutdown -serial stdio
VERBATIM USES_TERMINAL)
elseif(CMAKE_HOST_WIN32)
# This target starts up a QEMU+OVMF virtual machine using WHPX accelerator
add_custom_target(testefiwhpx
DEPENDS install
COMMAND ${QEMU_COMMAND} -name "ExectOS-${ARCH}-EFI-WHPX" -machine type=q35,kernel_irqchip=off,accel=whpx,mem-merge=off,vmport=off
-m 4G -overcommit mem-lock=off -rtc clock=host,base=localtime,driftfix=none
-bios ${EXECTOS_SOURCE_DIR}/sdk/firmware/ovmf_${ARCH}.fd
-hda fat:rw:${EXECTOS_BINARY_DIR}/output/binaries
-boot menu=on -d int -M smm=off -no-reboot -no-shutdown -serial stdio
VERBATIM USES_TERMINAL)
endif()
# This target starts up a QEMU+OVMF virtual machine using KVM accelerator
add_custom_target(testefikvm
DEPENDS install
COMMAND ${QEMU_COMMAND} -name "ExectOS-${ARCH}-EFI-KVM" -machine type=q35,kernel_irqchip=on,accel="kvm:whpx",mem-merge=off,vmport=off -enable-kvm -cpu host,-hypervisor,+topoext
-smp 2,sockets=1,cores=1,threads=2 -m 4G -overcommit mem-lock=off -rtc clock=host,base=localtime,driftfix=none
-drive file=${EXECTOS_SOURCE_DIR}/sdk/firmware/ovmf_code_${ARCH}.fd,if=pflash,format=raw,unit=0,readonly=on
-drive file=${EXECTOS_SOURCE_DIR}/sdk/firmware/ovmf_vars_${ARCH}.fd,if=pflash,format=raw,unit=1
-hda fat:rw:${EXECTOS_BINARY_DIR}/output/binaries
-boot menu=on -d int -M smm=off -no-reboot -no-shutdown -serial stdio
VERBATIM USES_TERMINAL)
# This target starts up a QEMU+OVMF virtual machine using TCG accelerator
add_custom_target(testefitcg
DEPENDS install
COMMAND ${QEMU_COMMAND} -name "ExectOS-${ARCH}-EFI-TCG" -machine type=q35,accel=tcg -cpu max,-hypervisor
-smp 2,sockets=1,cores=1,threads=2 -m 4G -overcommit mem-lock=off -rtc clock=host,base=localtime,driftfix=none
-bios ${EXECTOS_SOURCE_DIR}/sdk/firmware/ovmf_${ARCH}.fd
-drive file=${EXECTOS_SOURCE_DIR}/sdk/firmware/ovmf_code_${ARCH}.fd,if=pflash,format=raw,unit=0,readonly=on
-drive file=${EXECTOS_SOURCE_DIR}/sdk/firmware/ovmf_vars_${ARCH}.fd,if=pflash,format=raw,unit=1
-hda fat:rw:${EXECTOS_BINARY_DIR}/output/binaries
-boot menu=on -d int -no-reboot -no-shutdown -serial stdio
VERBATIM USES_TERMINAL)
if(CMAKE_HOST_LINUX)
if(WIN32)
# This target starts up a QEMU+OVMF virtual machine using WHPX accelerator on Windows
add_custom_target(testkvm
DEPENDS install
COMMAND ${QEMU_COMMAND} -name "ExectOS-${ARCH}-WHPX" -machine accel=whpx,kernel-irqchip=off
-bios ${EXECTOS_SOURCE_DIR}/sdk/firmware/OVMF-pure-efi.fd
-hda fat:rw:${EXECTOS_BINARY_DIR}/output/binaries
-no-reboot -no-shutdown -serial stdio
COMMENT "Using WHPX acceleration on Windows"
VERBATIM USES_TERMINAL)
else()
# This target starts up a QEMU+SEABIOS virtual machine using KVM accelerator
add_custom_target(testkvm
DEPENDS diskimg
COMMAND ${QEMU_COMMAND} -name "ExectOS-${ARCH}-BIOS-KVM" -machine type=q35,kernel_irqchip=on,accel=kvm,mem-merge=off,vmport=off -enable-kvm -cpu host,-hypervisor,+topoext
-smp 2,sockets=1,cores=1,threads=2 -m 4G -overcommit mem-lock=off -rtc clock=host,base=localtime,driftfix=none
-hda ${EXECTOS_BINARY_DIR}/output/disk.img
-boot menu=on -d int -no-reboot -no-shutdown -serial stdio
VERBATIM USES_TERMINAL)
elseif(CMAKE_HOST_WIN32)
# This target starts up a QEMU+SEABIOS virtual machine using WHPX accelerator
add_custom_target(testwhpx
DEPENDS diskimg
COMMAND ${QEMU_COMMAND} -name "ExectOS-${ARCH}-BIOS-WHPX" -machine type=q35,kernel_irqchip=off,accel=whpx,mem-merge=off,vmport=off
-m 4G -overcommit mem-lock=off -rtc clock=host,base=localtime,driftfix=none
-hda ${EXECTOS_BINARY_DIR}/output/disk.img
-boot menu=on -d int -no-reboot -no-shutdown -serial stdio
VERBATIM USES_TERMINAL)
endif()
DEPENDS diskimg
COMMAND ${QEMU_COMMAND} -name "ExectOS-${ARCH}-BIOS-KVM" -machine type=q35,kernel_irqchip=on,accel="kvm:whpx",mem-merge=off,vmport=off -enable-kvm -cpu host,-hypervisor,+topoext
-smp 2,sockets=1,cores=1,threads=2 -m 4G -overcommit mem-lock=off -rtc clock=host,base=localtime,driftfix=none
-hda ${EXECTOS_BINARY_DIR}/output/disk.img
-boot menu=on -d int -no-reboot -no-shutdown -serial stdio
VERBATIM USES_TERMINAL)
endif()
# This target starts up a QEMU+SEABIOS virtual machine using TCG accelerator
add_custom_target(testtcg

6
sdk/cmake/functions.cmake
View File

@@ -64,17 +64,11 @@ function(compile_bootsector NAME SOURCE BASEADDR ENTRYPOINT)
set(BINARY_NAME "${NAME}.bin")
set(OBJECT_NAME "${NAME}.obj")
get_directory_property(DEFS COMPILE_DEFINITIONS)
foreach(def ${DEFS})
list(APPEND ASM_DEFS "-D${def}")
endforeach()
add_custom_command(
OUTPUT ${CMAKE_CURRENT_BINARY_DIR}/${BINARY_NAME}
COMMAND ${CMAKE_ASM_COMPILER}
/nologo
--target=i386-none-elf
${ASM_DEFS}
-I${CMAKE_CURRENT_SOURCE_DIR}
/Fo${CMAKE_CURRENT_BINARY_DIR}/${OBJECT_NAME}
-c -- ${SOURCE}

BIN
sdk/firmware/OVMF-pure-efi.fd Normal file
View File

Binary file not shown.

BIN
sdk/firmware/ovmf_i686.fd → sdk/firmware/ovmf_code_amd64.fd
View File

Binary file not shown.

BIN
sdk/firmware/ovmf_amd64.fd → sdk/firmware/ovmf_code_i686.fd
View File

Binary file not shown.

BIN
sdk/firmware/ovmf_vars_amd64.fd Normal file
View File

Binary file not shown.

BIN
sdk/firmware/ovmf_vars_i686.fd Normal file
View File

Binary file not shown.

20
sdk/xtdk/amd64/ketypes.h
View File

@@ -108,6 +108,9 @@
/* Static Kernel-Mode address start */
#define KSEG0_BASE 0xFFFFF80000000000
/* XTOS Kernel address base */
#define KSEG0_KERNEL_BASE 0x0000000800000000
/* XTOS Kernel stack size */
#define KERNEL_STACK_SIZE 0x8000
@@ -269,18 +272,11 @@ typedef struct _KIDTENTRY
{
USHORT OffsetLow;
USHORT Selector;
union
{
struct
{
USHORT IstIndex:3;
USHORT Reserved0:5;
USHORT Type:5;
USHORT Dpl:2;
USHORT Present:1;
};
USHORT Access;
};
USHORT IstIndex:3;
USHORT Reserved0:5;
USHORT Type:5;
USHORT Dpl:2;
USHORT Present:1;
USHORT OffsetMiddle;
ULONG OffsetHigh;
ULONG Reserved1;

69
sdk/xtdk/amd64/mmtypes.h
View File

@@ -25,11 +25,11 @@
#define MM_PXE_BASE 0xFFFFF6FB7DBED000ULL
/* Page directory and page base addresses for 5-level paging */
#define MM_PTE_LA57_BASE 0xFFED000000000000ULL
#define MM_PDE_LA57_BASE 0xFFEDF68000000000ULL
#define MM_PPE_LA57_BASE 0xFFEDF6FB40000000ULL
#define MM_PXE_LA57_BASE 0xFFEDF6FB7DA00000ULL
#define MM_P5E_LA57_BASE 0xFFEDF6FB7DBED000ULL
#define MM_PTE_LA57_BASE 0xFFFF000000000000ULL
#define MM_PDE_LA57_BASE 0xFFFF010000000000ULL
#define MM_PPE_LA57_BASE 0xFFFF010800000000ULL
#define MM_PXE_LA57_BASE 0xFFFF010840000000ULL
#define MM_P5E_LA57_BASE 0xFFFF010840200000ULL
/* PTE shift values */
#define MM_PTE_SHIFT 3
@@ -39,55 +39,15 @@
#define MM_PXI_SHIFT 39
#define MM_P5I_SHIFT 48
/* PTE state flags */
#define MM_PTE_VALID 0x0000000000000001ULL
#define MM_PTE_ACCESSED 0x0000000000000020ULL
#define MM_PTE_DIRTY 0x0000000000000040ULL
/* PTE scope flags */
#define MM_PTE_LARGE_PAGE 0x0000000000000080ULL
#define MM_PTE_GLOBAL 0x0000000000000100ULL
/* PTE access flags */
#define MM_PTE_NOACCESS 0x0000000000000000ULL
#define MM_PTE_READONLY 0x0000000000000000ULL
#define MM_PTE_EXECUTE 0x0000000000000000ULL
#define MM_PTE_EXECUTE_READ 0x0000000000000000ULL
#define MM_PTE_READWRITE 0x8000000000000002ULL
#define MM_PTE_WRITECOPY 0x8000000000000200ULL
#define MM_PTE_EXECUTE_READWRITE 0x0000000000000002ULL
#define MM_PTE_EXECUTE_WRITECOPY 0x0000000000000200ULL
/* PTE protection flags */
#define MM_PTE_NOEXECUTE 0x8000000000000000ULL
#define MM_PTE_PROTECT 0x8000000000000612ULL
/* PTE cache flags */
#define MM_PTE_CACHE_ENABLE 0x0000000000000000ULL
#define MM_PTE_CACHE_DISABLE 0x0000000000000010ULL
#define MM_PTE_CACHE_WRITECOMBINED 0x0000000000000010ULL
#define MM_PTE_CACHE_WRITETHROUGH 0x0000000000000008ULL
/* PTE software flags */
#define MM_PTE_COPY_ON_WRITE 0x0000000000000200ULL
#define MM_PTE_PROTOTYPE 0x0000000000000400ULL
#define MM_PTE_TRANSITION 0x0000000000000800ULL
/* PTE frame bits */
#define MM_PTE_FRAME_BITS 57
/* PTE protection bits */
#define MM_PTE_PROTECTION_BITS 5
/* Base address of the system page table */
#define MM_SYSTEM_PTE_BASE KSEG0_BASE
/* Number of PTEs per page */
#define MM_PTE_PER_PAGE 512
#define MM_PDE_PER_PAGE 512
#define MM_PPE_PER_PAGE 512
#define MM_PXE_PER_PAGE 512
/* Minimum number of physical pages needed by the system */
#define MM_MINIMUM_PHYSICAL_PAGES 2048
/* Number of system PTEs */
#define MM_DEFAULT_NUMBER_SYSTEM_PTES 22000
/* Default number of secondary colors */
#define MM_DEFAULT_SECONDARY_COLORS 64
@@ -103,9 +63,6 @@
/* Maximum physical address used by HAL allocations */
#define MM_MAXIMUM_PHYSICAL_ADDRESS 0x00000000FFFFFFFFULL
/* Highest system address */
#define MM_HIGHEST_SYSTEM_ADDRESS 0xFFFFFFFFFFFFFFFFULL
/* Trampoline code address */
#define MM_TRAMPOLINE_ADDRESS 0x80000
@@ -295,7 +252,6 @@ typedef struct _MMPFN
USHORT ReferenceCount;
} e2;
} u3;
ULONG UsedPageTableEntries;
union
{
MMPTE OriginalPte;
@@ -306,11 +262,12 @@ typedef struct _MMPFN
ULONG_PTR EntireFrame;
struct
{
ULONG_PTR PteFrame:57;
ULONG_PTR PteFrame:58;
ULONG_PTR InPageError:1;
ULONG_PTR VerifierAllocation:1;
ULONG_PTR AweAllocation:1;
ULONG_PTR Priority:3;
ULONG_PTR LockCharged:1;
ULONG_PTR KernelStack:1;
ULONG_PTR MustBeCached:1;
};
} u4;

14
sdk/xtdk/bltypes.h
View File

@@ -100,19 +100,21 @@ typedef VOID (XTCDECL *PBL_LLIST_INITIALIZE_HEAD)(IN PLIST_ENTRY ListHead);
typedef VOID (XTCDECL *PBL_LLIST_INSERT_HEAD)(IN OUT PLIST_ENTRY ListHead, IN PLIST_ENTRY Entry);
typedef VOID (XTCDECL *PBL_LLIST_INSERT_TAIL)(IN OUT PLIST_ENTRY ListHead, IN PLIST_ENTRY Entry);
typedef VOID (XTCDECL *PBL_LLIST_REMOVE_ENTRY)(IN PLIST_ENTRY Entry);
typedef EFI_STATUS (XTCDECL *PBL_MAP_EFI_MEMORY)(IN OUT PXTBL_PAGE_MAPPING PageMap, IN ULONG_PTR BaseAddress);
typedef EFI_STATUS (XTCDECL *PBL_MAP_PAGE)(IN PXTBL_PAGE_MAPPING PageMap, IN ULONGLONG VirtualAddress, IN ULONGLONG PhysicalAddress, IN ULONGLONG NumberOfPages);
typedef EFI_STATUS (XTCDECL *PBL_MAP_VIRTUAL_MEMORY)(IN OUT PXTBL_PAGE_MAPPING PageMap, IN ULONGLONG VirtualAddress, IN ULONGLONG PhysicalAddress, IN ULONGLONG NumberOfPages, IN LOADER_MEMORY_TYPE MemoryType);
typedef EFI_STATUS (XTCDECL *PBL_MAP_EFI_MEMORY)(IN OUT PXTBL_PAGE_MAPPING PageMap, IN OUT PVOID *MemoryMapAddress, IN PBL_GET_MEMTYPE_ROUTINE GetMemoryTypeRoutine);
typedef EFI_STATUS (XTCDECL *PBL_MAP_PAGE)(IN PXTBL_PAGE_MAPPING PageMap, IN ULONG_PTR VirtualAddress, IN ULONG_PTR PhysicalAddress, IN ULONG NumberOfPages);
typedef EFI_STATUS (XTCDECL *PBL_MAP_VIRTUAL_MEMORY)(IN OUT PXTBL_PAGE_MAPPING PageMap, IN PVOID VirtualAddress, IN PVOID PhysicalAddress, IN ULONGLONG NumberOfPages, IN LOADER_MEMORY_TYPE MemoryType);
typedef VOID (XTAPI *PBL_MOVE_MEMORY)(IN OUT PVOID Destination, IN PCVOID Source, IN SIZE_T Length);
typedef EFI_STATUS (XTCDECL *PBL_OPEN_VOLUME)(IN PEFI_DEVICE_PATH_PROTOCOL DevicePath, OUT PEFI_HANDLE DiskHandle, OUT PEFI_FILE_HANDLE *FsHandle);
typedef EFI_STATUS (XTCDECL *PBL_OPEN_PROTOCOL)(OUT PEFI_HANDLE Handle, OUT PVOID *ProtocolHandler, IN PEFI_GUID ProtocolGuid);
typedef EFI_STATUS (XTCDECL *PBL_OPEN_PROTOCOL_HANDLE)(IN EFI_HANDLE Handle, OUT PVOID *ProtocolHandler, IN PEFI_GUID ProtocolGuid);
typedef PVOID (XTCDECL *PBL_PHYSICAL_ADDRESS_TO_VIRTUAL)(IN PVOID PhysicalAddress, IN PVOID PhysicalBase, IN PVOID VirtualBase);
typedef UCHAR (XTCDECL *PBL_IOPORT_READ_8)(IN USHORT Port);
typedef USHORT (XTCDECL *PBL_IOPORT_READ_16)(IN USHORT Port);
typedef ULONG (XTCDECL *PBL_IOPORT_READ_32)(IN USHORT Port);
typedef VOID (XTCDECL *PBL_IOPORT_WRITE_8)(IN USHORT Port, IN UCHAR Value);
typedef VOID (XTCDECL *PBL_IOPORT_WRITE_16)(IN USHORT Port, IN USHORT Value);
typedef VOID (XTCDECL *PBL_IOPORT_WRITE_32)(IN USHORT Port, IN ULONG Value);
typedef EFI_STATUS (XTCDECL *PBL_PHYSICAL_LIST_TO_VIRTUAL)(IN PXTBL_PAGE_MAPPING PageMap, IN OUT PLIST_ENTRY ListHead, IN PVOID PhysicalBase, IN PVOID VirtualBase);
typedef EFI_STATUS (XTCDECL *PBL_POWER_SYSTEM)();
typedef EFI_STATUS (XTCDECL *PBL_READ_FILE)(IN PEFI_FILE_HANDLE DirHandle, IN PCWSTR FileName, OUT PVOID *FileData, OUT PSIZE_T FileSize);
typedef EFI_STATUS (XTCDECL *PBL_REGISTER_BOOT_PROTOCOL)(IN PCWSTR SystemType, IN PEFI_GUID BootProtocolGuid);
@@ -230,8 +232,8 @@ typedef struct _XTBL_KNOWN_BOOT_PROTOCOL
typedef struct _XTBL_MEMORY_MAPPING
{
LIST_ENTRY ListEntry;
ULONGLONG VirtualAddress;
ULONGLONG PhysicalAddress;
PVOID VirtualAddress;
PVOID PhysicalAddress;
ULONGLONG NumberOfPages;
LOADER_MEMORY_TYPE MemoryType;
} XTBL_MEMORY_MAPPING, *PXTBL_MEMORY_MAPPING;
@@ -459,6 +461,8 @@ typedef struct _XTBL_LOADER_PROTOCOL
PBL_MAP_PAGE MapPage;
PBL_MAP_VIRTUAL_MEMORY MapVirtualMemory;
PBL_MOVE_MEMORY MoveMemory;
PBL_PHYSICAL_ADDRESS_TO_VIRTUAL PhysicalAddressToVirtual;
PBL_PHYSICAL_LIST_TO_VIRTUAL PhysicalListToVirtual;
PBL_SET_MEMORY SetMemory;
PBL_ZERO_MEMORY ZeroMemory;
} Memory;

22
sdk/xtdk/i686/ketypes.h
View File

@@ -58,6 +58,12 @@
#define KIDT_ACCESS_RING0 0x00
#define KIDT_ACCESS_RING3 0x60
/* IDT gate types */
#define KIDT_TASK 0x05
#define KIDT_CALL 0x0C
#define KIDT_INTERRUPT 0x0E
#define KIDT_TRAP 0x0F
/* TSS Offsets */
#define KTSS_ESP0 0x04
#define KTSS_CR3 0x1C
@@ -128,6 +134,9 @@
/* Static Kernel-Mode address start */
#define KSEG0_BASE 0x80000000
/* XTOS Kernel address base */
#define KSEG0_KERNEL_BASE 0x01800000
/* XTOS Kernel stack size */
#define KERNEL_STACK_SIZE 0x4000
@@ -275,18 +284,7 @@ typedef struct _KIDTENTRY
{
USHORT Offset;
USHORT Selector;
union
{
struct
{
UCHAR Reserved;
UCHAR Type:4;
UCHAR Flag:1;
UCHAR Dpl:2;
UCHAR Present:1;
};
USHORT Access;
};
USHORT Access;
USHORT ExtendedOffset;
} KIDTENTRY, *PKIDTENTRY;

73
sdk/xtdk/i686/mmtypes.h
View File

@@ -35,57 +35,9 @@
#define MM_PTE_LEGACY_SHIFT 2
#define MM_PDI_LEGACY_SHIFT 22
/* PTE state flags */
#define MM_PTE_VALID 0x00000001
#define MM_PTE_ACCESSED 0x00000020
#define MM_PTE_DIRTY 0x00000040
/* PTE scope flags */
#define MM_PTE_LARGE_PAGE 0x00000080
#define MM_PTE_GLOBAL 0x00000100
/* PTE access flags */
#define MM_PTE_NOACCESS 0x00000000
#define MM_PTE_READONLY 0x00000000
#define MM_PTE_EXECUTE 0x00000000
#define MM_PTE_EXECUTE_READ 0x00000000
#define MM_PTE_READWRITE 0x00000002
#define MM_PTE_WRITECOPY 0x00000200
#define MM_PTE_EXECUTE_READWRITE 0x00000002
#define MM_PTE_EXECUTE_WRITECOPY 0x00000200
/* PTE protection flags */
#define MM_PTE_NOEXECUTE 0x00000000
#define MM_PTE_PROTECT 0x00000612
/* PTE cache flags */
#define MM_PTE_CACHE_ENABLE 0x00000000
#define MM_PTE_CACHE_DISABLE 0x00000010
#define MM_PTE_CACHE_WRITECOMBINED 0x00000010
#define MM_PTE_CACHE_WRITETHROUGH 0x00000008
/* PTE software flags */
#define MM_PTE_COPY_ON_WRITE 0x00000200
#define MM_PTE_PROTOTYPE 0x00000400
#define MM_PTE_TRANSITION 0x00000800
/* PTE frame bits */
#define MM_PTE_FRAME_BITS 25
/* PTE protection bits */
#define MM_PTE_PROTECTION_BITS 5
/* Base address of the system page table */
#define MM_SYSTEM_PTE_BASE NULLPTR
/* Minimum number of physical pages needed by the system */
#define MM_MINIMUM_PHYSICAL_PAGES 1100
/* Number of system PTEs */
#define MM_MINIMUM_NUMBER_SYSTEM_PTES 7000
#define MM_DEFAULT_NUMBER_SYSTEM_PTES 11000
#define MM_MAXIMUM_NUMBER_SYSTEM_PTES 22000
/* Default number of secondary colors */
#define MM_DEFAULT_SECONDARY_COLORS 64
@@ -101,9 +53,6 @@
/* Maximum physical address used by HAL allocations */
#define MM_MAXIMUM_PHYSICAL_ADDRESS 0xFFFFFFFF
/* Highest system address */
#define MM_HIGHEST_SYSTEM_ADDRESS 0xFFFFFFFF
/* Trampoline code address */
#define MM_TRAMPOLINE_ADDRESS 0x80000
@@ -157,6 +106,7 @@ typedef struct _HARDWARE_MODERN_PTE
/* Generic Page Table entry union to abstract PML2 and PML3 formats */
typedef union _HARDWARE_PTE
{
ULONGLONG Long;
HARDWARE_LEGACY_PTE Pml2;
HARDWARE_MODERN_PTE Pml3;
} HARDWARE_PTE, *PHARDWARE_PTE;
@@ -251,12 +201,12 @@ typedef struct _MMPML2_PTE_TRANSITION
typedef union _MMPML2_PTE
{
ULONG Long;
HARDWARE_LEGACY_PTE Flush;
MMPML2_PTE_HARDWARE Hardware;
MMPML2_PTE_PROTOTYPE Prototype;
MMPML2_PTE_SOFTWARE Software;
MMPML2_PTE_TRANSITION Transition;
MMPML2_PTE_SUBSECTION Subsection;
HARDWARE_PTE Flush;
MMPML2_PTE_HARDWARE Hard;
MMPML2_PTE_PROTOTYPE Proto;
MMPML2_PTE_SOFTWARE Soft;
MMPML2_PTE_TRANSITION Trans;
MMPML2_PTE_SUBSECTION Subsect;
MMPML2_PTE_LIST List;
} MMPML2_PTE, *PMMPML2_PTE;
@@ -346,7 +296,7 @@ typedef struct _MMPML3_PTE_TRANSITION
typedef union _MMPML3_PTE
{
ULONGLONG Long;
HARDWARE_MODERN_PTE Flush;
HARDWARE_PTE Flush;
MMPML3_PTE_HARDWARE Hardware;
MMPML3_PTE_PROTOTYPE Prototype;
MMPML3_PTE_SOFTWARE Software;
@@ -358,6 +308,7 @@ typedef union _MMPML3_PTE
/* Generic Page Table Entry union to abstract PML2 and PML3 formats */
typedef union _MMPTE
{
ULONGLONG Long;
MMPML2_PTE Pml2;
MMPML3_PTE Pml3;
} MMPTE, *PMMPTE;
@@ -388,7 +339,6 @@ typedef struct _MMPFN
USHORT ReferenceCount;
} e2;
} u3;
ULONG UsedPageTableEntries;
union
{
MMPTE OriginalPte;
@@ -399,11 +349,12 @@ typedef struct _MMPFN
ULONG_PTR EntireFrame;
struct
{
ULONG_PTR PteFrame:25;
ULONG_PTR PteFrame:26;
ULONG_PTR InPageError:1;
ULONG_PTR VerifierAllocation:1;
ULONG_PTR AweAllocation:1;
ULONG_PTR Priority:3;
ULONG_PTR LockCharged:1;
ULONG_PTR KernelStack:1;
ULONG_PTR MustBeCached:1;
};
} u4;

10
sdk/xtdk/ketypes.h
View File

@@ -150,23 +150,21 @@ typedef enum _KTHREAD_STATE
typedef enum _KSPIN_LOCK_QUEUE_LEVEL
{
DispatcherLock,
ExpansionLock,
UnusedSpareLock,
PfnLock,
SystemSpaceLock,
VacbLock,
MasterLock,
NonPagedAllocPoolLock,
NonPagedPoolLock,
IoCancelLock,
WorkQueueLock,
IoVpbLock,
IoDatabaseLock,
IoCompletionLock,
FileSystemLock,
FsStructLock,
AfdWorkQueueLock,
BcbLock,
NonPagedPoolLock,
ReservedSystemLock,
TimerTableLock,
MmNonPagedPoolLock,
MaximumLock
} KSPIN_LOCK_QUEUE_LEVEL, *PKSPIN_LOCK_QUEUE_LEVEL;

68
sdk/xtdk/mmtypes.h
View File

@@ -4,7 +4,6 @@
* FILE: sdk/xtdk/mmtypes.h
* DESCRIPTION: Memory management data structures
* DEVELOPERS: Rafal Kupiec <belliash@codingworkshop.eu.org>
* Aiken Harris <harraiken91@gmail.com>
*/
#ifndef __XTDK_MMTYPES_H
@@ -14,48 +13,6 @@
#include ARCH_HEADER(xtstruct.h)
/* Number of hyper space pages */
#define MM_HYPERSPACE_PAGE_COUNT 255
/* Number of paging colors */
#define MM_PAGING_COLORS 64
/* PTE frame mask definition */
#define MM_PFN_PTE_FRAME (((ULONG_PTR)1 << MM_PTE_FRAME_BITS) - 1)
/* Number of reserved zeroed PTEs */
#define MM_RESERVED_ZERO_PTES 32
/* Memory manager page lists */
typedef enum _MMPAGELISTS
{
ZeroedPageList = 0,
FreePageList = 1,
StandbyPageList = 2,
ModifiedPageList = 3,
ModifiedReadOnlyPageList = 4,
BadPageList = 5,
ActiveAndValid = 6,
TransitionPage = 7
} MMPAGELISTS, *PMMPAGELISTS;
/* Page cache attributes */
typedef enum _MMPFN_CACHE_ATTRIBUTE
{
PfnNonCached,
PfnCached,
PfnWriteCombined,
PfnNotMapped
} MMPFN_CACHE_ATTRIBUTE, *PMMPFN_CACHE_ATTRIBUTE;
/* Page table pool types */
typedef enum _MMSYSTEM_PTE_POOL_TYPE
{
SystemPteSpace,
NonPagedPoolExpansion,
MaximumPtePoolTypes
} MMSYSTEM_PTE_POOL_TYPE, *PMMSYSTEM_PTE_POOL_TYPE;
/* Page map routines structure definition */
typedef CONST STRUCT _CMMPAGEMAP_ROUTINES
{
@@ -73,22 +30,6 @@ typedef struct _MMCOLOR_TABLES
ULONG_PTR Count;
} MMCOLOR_TABLES, *PMMCOLOR_TABLES;
/* Memory layout structure definition */
typedef struct _MMMEMORY_LAYOUT
{
PMMPFN PfnDatabaseAddress;
PVOID SelfMapAddress;
PVOID HyperSpaceStart;
PVOID HyperSpaceEnd;
PVOID NonPagedPoolStart;
PVOID NonPagedPoolEnd;
PVOID PagedPoolStart;
PVOID PagedPoolEnd;
PVOID SystemSpaceStart;
PVOID SystemSpaceEnd;
PVOID UserSpaceEnd;
} MMMEMORY_LAYOUT, *PMMMEMORY_LAYOUT;
/* Page Frame Entry structure definition */
typedef struct _MMPFNENTRY
{
@@ -104,13 +45,4 @@ typedef struct _MMPFNENTRY
USHORT ParityError:1;
} MMPFNENTRY, *PMMPFNENTRY;
/* Page Frame List structure definition */
typedef struct _MMPFNLIST
{
PFN_NUMBER Total;
MMPAGELISTS ListName;
PFN_NUMBER Flink;
PFN_NUMBER Blink;
} MMPFNLIST, *PMMPFNLIST;
#endif /* __XTDK_MMTYPES_H */

3
sdk/xtdk/xtbase.h
View File

@@ -29,9 +29,6 @@ typedef UCHAR KRUNLEVEL, *PKRUNLEVEL;
/* Spin locks synchronization mechanism */
typedef ULONG_PTR KSPIN_LOCK, *PKSPIN_LOCK;
/* Page Frame Number count */
typedef ULONG PFN_COUNT;
/* Page Frame Number */
typedef ULONG_PTR PFN_NUMBER, *PPFN_NUMBER;

6
sdk/xtdk/xtcompat.h
View File

@@ -12,9 +12,8 @@
#ifdef __cplusplus
/* C++ definitions */
#define NULLPTR nullptr
#define VIRTUAL virtual
#define XTCLINK extern "C"
#define NULLPTR nullptr
/* C++ boolean type */
typedef bool BOOLEAN, *PBOOLEAN;
@@ -25,9 +24,8 @@
typedef wchar_t wchar;
#else
/* C definitions */
#define NULLPTR ((void *)0)
#define VIRTUAL
#define XTCLINK
#define NULLPTR ((void *)0)
/* C boolean type */
typedef enum _BOOLEAN

5
sdk/xtdk/xtstruct.h
View File

@@ -48,9 +48,6 @@ typedef enum _KTHREAD_STATE KTHREAD_STATE, *PKTHREAD_STATE;
typedef enum _KTIMER_TYPE KTIMER_TYPE, *PKTIMER_TYPE;
typedef enum _KUBSAN_DATA_TYPE KUBSAN_DATA_TYPE, *PKUBSAN_DATA_TYPE;
typedef enum _LOADER_MEMORY_TYPE LOADER_MEMORY_TYPE, *PLOADER_MEMORY_TYPE;
typedef enum _MMPAGELISTS MMPAGELISTS, *PMMPAGELISTS;
typedef enum _MMPFN_CACHE_ATTRIBUTE MMPFN_CACHE_ATTRIBUTE, *PMMPFN_CACHE_ATTRIBUTE;
typedef enum _MMSYSTEM_PTE_POOL_TYPE MMSYSTEM_PTE_POOL_TYPE, *PMMSYSTEM_PTE_POOL_TYPE;
typedef enum _MODE MODE, *PMODE;
typedef enum _RTL_VARIABLE_TYPE RTL_VARIABLE_TYPE, *PRTL_VARIABLE_TYPE;
typedef enum _SYSTEM_FIRMWARE_TYPE SYSTEM_FIRMWARE_TYPE, *PSYSTEM_FIRMWARE_TYPE;
@@ -277,9 +274,7 @@ typedef struct _LOADER_INFORMATION_BLOCK LOADER_INFORMATION_BLOCK, *PLOADER_INFO
typedef struct _LOADER_MEMORY_DESCRIPTOR LOADER_MEMORY_DESCRIPTOR, *PLOADER_MEMORY_DESCRIPTOR;
typedef struct _M128 M128, *PM128;
typedef struct _MMCOLOR_TABLES MMCOLOR_TABLES, *PMMCOLOR_TABLES;
typedef struct _MMMEMORY_LAYOUT MMMEMORY_LAYOUT, *PMMMEMORY_LAYOUT;
typedef struct _MMPFNENTRY MMPFNENTRY, *PMMPFNENTRY;
typedef struct _MMPFNLIST MMPFNLIST, *PMMPFNLIST;
typedef struct _PCAT_FIRMWARE_INFORMATION PCAT_FIRMWARE_INFORMATION, *PPCAT_FIRMWARE_INFORMATION;
typedef struct _PCI_BRIDGE_CONTROL_REGISTER PCI_BRIDGE_CONTROL_REGISTER, *PPCI_BRIDGE_CONTROL_REGISTER;
typedef struct _PCI_COMMON_CONFIG PCI_COMMON_CONFIG, *PPCI_COMMON_CONFIG;

15
xtoskrnl/CMakeLists.txt
View File

@@ -51,20 +51,14 @@ list(APPEND XTOSKRNL_SOURCE
${XTOSKRNL_SOURCE_DIR}/ke/spinlock.cc
${XTOSKRNL_SOURCE_DIR}/ke/sysres.cc
${XTOSKRNL_SOURCE_DIR}/ke/timer.cc
${XTOSKRNL_SOURCE_DIR}/mm/${ARCH}/mmgr.cc
${XTOSKRNL_SOURCE_DIR}/mm/${ARCH}/init.cc
${XTOSKRNL_SOURCE_DIR}/mm/${ARCH}/pagemap.cc
${XTOSKRNL_SOURCE_DIR}/mm/${ARCH}/paging.cc
${XTOSKRNL_SOURCE_DIR}/mm/${ARCH}/pfault.cc
${XTOSKRNL_SOURCE_DIR}/mm/${ARCH}/pfn.cc
${XTOSKRNL_SOURCE_DIR}/mm/${ARCH}/pte.cc
${XTOSKRNL_SOURCE_DIR}/mm/colors.cc
${XTOSKRNL_SOURCE_DIR}/mm/data.cc
${XTOSKRNL_SOURCE_DIR}/mm/hlpool.cc
${XTOSKRNL_SOURCE_DIR}/mm/init.cc
${XTOSKRNL_SOURCE_DIR}/mm/kpool.cc
${XTOSKRNL_SOURCE_DIR}/mm/mmgr.cc
${XTOSKRNL_SOURCE_DIR}/mm/paging.cc
${XTOSKRNL_SOURCE_DIR}/mm/pfn.cc
${XTOSKRNL_SOURCE_DIR}/mm/pte.cc
${XTOSKRNL_SOURCE_DIR}/po/idle.cc
${XTOSKRNL_SOURCE_DIR}/rtl/${ARCH}/dispatch.cc
${XTOSKRNL_SOURCE_DIR}/rtl/${ARCH}/exsup.cc
@@ -88,12 +82,11 @@ add_library(libxtos ${XTOSKRNL_SOURCE})
# Link kernel executable
add_executable(xtoskrnl
${XTOSKRNL_SOURCE}
${CMAKE_CURRENT_BINARY_DIR}/xtoskrnl.def)
# Add linker libraries
target_link_libraries(xtoskrnl
PRIVATE
libxtos)
target_link_libraries(xtoskrnl)
# Set proper binary name and install target
set_target_properties(xtoskrnl PROPERTIES SUFFIX .exe)

16
xtoskrnl/README.md
View File

@@ -4,18 +4,6 @@ within the XTOS kernel space. It is responsible for various core services, such
management, and process scheduling. The kernel contains the scheduler (sometimes referred to as the Dispatcher), the
cache, object, and memory managers, the security manager, and other executive components described below.
## Kernel Parameters
Kernel parameters are XTOS boot-time options used to ensure proper initialization and handling of hardware peripherals.
These parameters can be configured either temporarily by editing the boot entry in the bootloader’s selection menu, or
permanently by modifying the XTLDR configuration file.
The following is a consolidated list of available kernel parameters:
* **NOXPA**: Disables PAE or LA57 support, depending on the CPU architecture. This parameter is handled by the
bootloader, which configures paging and selects the appropriate Page Map Level (PML) before transferring control to
the kernel.
## Source Code
The source code of the kernel is organized into subsystem-specific directories. Each directory name also defines the
corresponding C++ namespace in which the subsystem's classes and routines reside. These subsystems include:
@@ -80,8 +68,8 @@ routine:
For all C++ code inside the kernel the naming model has evolved. Consider the **KE::KThread::InitializeThread()**
routine:
* **KE** - The namespace replaces the prefix and indicates the subsystem. Namespaces are written in uppercase and no
longer use the trailing p for private routines, because classes use C++ visibility to control access.
longer use the trailing p for private routines, because classes use C++ visibility to control access.
* **KThread** - Within each namespace, related functionality is grouped into classes, which encapsulate variables and
methods.
methods.
* **InitializeThread** - Method names follow the `<Operation><Object>` pattern.

70
xtoskrnl/ar/amd64/procsup.cc
View File

@@ -249,34 +249,34 @@ AR::ProcSup::InitializeIdt(IN PKPROCESSOR_BLOCK ProcessorBlock)
for(Vector = 0; Vector < IDT_ENTRIES; Vector++)
{
/* Set the IDT to handle unexpected interrupts */
SetIdtGate(ProcessorBlock->IdtBase, Vector, (PVOID)ArTrap0xFF, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0, AMD64_INTERRUPT_GATE);
SetIdtGate(ProcessorBlock->IdtBase, Vector, (PVOID)ArTrap0xFF, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0);
}
/* Setup IDT handlers for known interrupts and traps */
SetIdtGate(ProcessorBlock->IdtBase, 0x00, (PVOID)ArTrap0x00, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0, AMD64_TRAP_GATE);
SetIdtGate(ProcessorBlock->IdtBase, 0x01, (PVOID)ArTrap0x01, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0, AMD64_TRAP_GATE);
SetIdtGate(ProcessorBlock->IdtBase, 0x02, (PVOID)ArTrap0x02, KGDT_R0_CODE, KIDT_IST_PANIC, KIDT_ACCESS_RING0, AMD64_INTERRUPT_GATE);
SetIdtGate(ProcessorBlock->IdtBase, 0x03, (PVOID)ArTrap0x03, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING3, AMD64_TRAP_GATE);
SetIdtGate(ProcessorBlock->IdtBase, 0x04, (PVOID)ArTrap0x04, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING3, AMD64_TRAP_GATE);
SetIdtGate(ProcessorBlock->IdtBase, 0x05, (PVOID)ArTrap0x05, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0, AMD64_TRAP_GATE);
SetIdtGate(ProcessorBlock->IdtBase, 0x06, (PVOID)ArTrap0x06, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0, AMD64_TRAP_GATE);
SetIdtGate(ProcessorBlock->IdtBase, 0x07, (PVOID)ArTrap0x07, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0, AMD64_TRAP_GATE);
SetIdtGate(ProcessorBlock->IdtBase, 0x08, (PVOID)ArTrap0x08, KGDT_R0_CODE, KIDT_IST_PANIC, KIDT_ACCESS_RING0, AMD64_TRAP_GATE);
SetIdtGate(ProcessorBlock->IdtBase, 0x09, (PVOID)ArTrap0x09, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0, AMD64_TRAP_GATE);
SetIdtGate(ProcessorBlock->IdtBase, 0x0A, (PVOID)ArTrap0x0A, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0, AMD64_TRAP_GATE);
SetIdtGate(ProcessorBlock->IdtBase, 0x0B, (PVOID)ArTrap0x0B, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0, AMD64_TRAP_GATE);
SetIdtGate(ProcessorBlock->IdtBase, 0x0C, (PVOID)ArTrap0x0C, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0, AMD64_TRAP_GATE);
SetIdtGate(ProcessorBlock->IdtBase, 0x0D, (PVOID)ArTrap0x0D, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0, AMD64_TRAP_GATE);
SetIdtGate(ProcessorBlock->IdtBase, 0x0E, (PVOID)ArTrap0x0E, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0, AMD64_TRAP_GATE);
SetIdtGate(ProcessorBlock->IdtBase, 0x10, (PVOID)ArTrap0x10, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0, AMD64_TRAP_GATE);
SetIdtGate(ProcessorBlock->IdtBase, 0x11, (PVOID)ArTrap0x11, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0, AMD64_TRAP_GATE);
SetIdtGate(ProcessorBlock->IdtBase, 0x12, (PVOID)ArTrap0x12, KGDT_R0_CODE, KIDT_IST_MCA, KIDT_ACCESS_RING0, AMD64_TRAP_GATE);
SetIdtGate(ProcessorBlock->IdtBase, 0x13, (PVOID)ArTrap0x13, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0, AMD64_TRAP_GATE);
SetIdtGate(ProcessorBlock->IdtBase, 0x1F, (PVOID)ArTrap0x1F, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0, AMD64_INTERRUPT_GATE);
SetIdtGate(ProcessorBlock->IdtBase, 0x2C, (PVOID)ArTrap0x2C, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING3, AMD64_TRAP_GATE);
SetIdtGate(ProcessorBlock->IdtBase, 0x2D, (PVOID)ArTrap0x2D, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING3, AMD64_TRAP_GATE);
SetIdtGate(ProcessorBlock->IdtBase, 0x2F, (PVOID)ArTrap0x2F, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0, AMD64_INTERRUPT_GATE);
SetIdtGate(ProcessorBlock->IdtBase, 0xE1, (PVOID)ArTrap0xE1, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0, AMD64_INTERRUPT_GATE);
SetIdtGate(ProcessorBlock->IdtBase, 0x00, (PVOID)ArTrap0x00, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0);
SetIdtGate(ProcessorBlock->IdtBase, 0x01, (PVOID)ArTrap0x01, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0);
SetIdtGate(ProcessorBlock->IdtBase, 0x02, (PVOID)ArTrap0x02, KGDT_R0_CODE, KIDT_IST_PANIC, KIDT_ACCESS_RING0);
SetIdtGate(ProcessorBlock->IdtBase, 0x03, (PVOID)ArTrap0x03, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING3);
SetIdtGate(ProcessorBlock->IdtBase, 0x04, (PVOID)ArTrap0x04, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING3);
SetIdtGate(ProcessorBlock->IdtBase, 0x05, (PVOID)ArTrap0x05, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0);
SetIdtGate(ProcessorBlock->IdtBase, 0x06, (PVOID)ArTrap0x06, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0);
SetIdtGate(ProcessorBlock->IdtBase, 0x07, (PVOID)ArTrap0x07, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0);
SetIdtGate(ProcessorBlock->IdtBase, 0x08, (PVOID)ArTrap0x08, KGDT_R0_CODE, KIDT_IST_PANIC, KIDT_ACCESS_RING0);
SetIdtGate(ProcessorBlock->IdtBase, 0x09, (PVOID)ArTrap0x09, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0);
SetIdtGate(ProcessorBlock->IdtBase, 0x0A, (PVOID)ArTrap0x0A, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0);
SetIdtGate(ProcessorBlock->IdtBase, 0x0B, (PVOID)ArTrap0x0B, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0);
SetIdtGate(ProcessorBlock->IdtBase, 0x0C, (PVOID)ArTrap0x0C, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0);
SetIdtGate(ProcessorBlock->IdtBase, 0x0D, (PVOID)ArTrap0x0D, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0);
SetIdtGate(ProcessorBlock->IdtBase, 0x0E, (PVOID)ArTrap0x0E, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0);
SetIdtGate(ProcessorBlock->IdtBase, 0x10, (PVOID)ArTrap0x10, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0);
SetIdtGate(ProcessorBlock->IdtBase, 0x11, (PVOID)ArTrap0x11, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0);
SetIdtGate(ProcessorBlock->IdtBase, 0x12, (PVOID)ArTrap0x12, KGDT_R0_CODE, KIDT_IST_MCA, KIDT_ACCESS_RING0);
SetIdtGate(ProcessorBlock->IdtBase, 0x13, (PVOID)ArTrap0x13, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0);
SetIdtGate(ProcessorBlock->IdtBase, 0x1F, (PVOID)ArTrap0x1F, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0);
SetIdtGate(ProcessorBlock->IdtBase, 0x2C, (PVOID)ArTrap0x2C, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING3);
SetIdtGate(ProcessorBlock->IdtBase, 0x2D, (PVOID)ArTrap0x2D, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING3);
SetIdtGate(ProcessorBlock->IdtBase, 0x2F, (PVOID)ArTrap0x2F, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0);
SetIdtGate(ProcessorBlock->IdtBase, 0xE1, (PVOID)ArTrap0xE1, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0);
}
/**
@@ -636,9 +636,6 @@ AR::ProcSup::SetGdtEntryBase(IN PKGDTENTRY Gdt,
* @param Access
* Supplies the gate access rights.
*
* @param Type
* Supplies the gate type.
*
* @return This routine does not return any value.
*
* @since XT 1.0
@@ -650,22 +647,15 @@ AR::ProcSup::SetIdtGate(IN PKIDTENTRY Idt,
IN PVOID Handler,
IN USHORT Selector,
IN USHORT Ist,
IN USHORT Dpl,
IN USHORT Type)
IN USHORT Access)
{
/* Set the handler's address */
/* Setup the gate */
Idt[Vector].OffsetLow = ((ULONG_PTR)Handler & 0xFFFF);
Idt[Vector].OffsetMiddle = (((ULONG_PTR)Handler >> 16) & 0xFFFF);
Idt[Vector].OffsetHigh = (ULONG_PTR)Handler >> 32;
/* Set the code segment selector */
Idt[Vector].Selector = Selector;
/* Initialize the gate's attributes and flags */
Idt[Vector].Access = 0;
Idt[Vector].Dpl = Dpl;
Idt[Vector].Dpl = Access;
Idt[Vector].IstIndex = Ist;
Idt[Vector].Present = 1;
Idt[Vector].Reserved1 = 0;
Idt[Vector].Type = Type;
Idt[Vector].Selector = Selector;
Idt[Vector].Type = 0xE;
}

67
xtoskrnl/ar/i686/procsup.cc
View File

@@ -242,34 +242,34 @@ AR::ProcSup::InitializeIdt(IN PKPROCESSOR_BLOCK ProcessorBlock)
for(Vector = 0; Vector < IDT_ENTRIES; Vector++)
{
/* Set the IDT to handle unexpected interrupts */
SetIdtGate(ProcessorBlock->IdtBase, Vector, (PVOID)ArTrap0xFF, KGDT_R0_CODE, 0, KIDT_ACCESS_RING0, I686_INTERRUPT_GATE);
SetIdtGate(ProcessorBlock->IdtBase, Vector, (PVOID)ArTrap0xFF, KGDT_R0_CODE, 0, KIDT_INTERRUPT | KIDT_ACCESS_RING0);
}
/* Setup IDT handlers for known interrupts and traps */
SetIdtGate(ProcessorBlock->IdtBase, 0x00, (PVOID)ArTrap0x00, KGDT_R0_CODE, 0, KIDT_ACCESS_RING0, I686_TRAP_GATE);
SetIdtGate(ProcessorBlock->IdtBase, 0x01, (PVOID)ArTrap0x01, KGDT_R0_CODE, 0, KIDT_ACCESS_RING0, I686_TRAP_GATE);
SetIdtGate(ProcessorBlock->IdtBase, 0x02, (PVOID)ArTrap0x02, KGDT_R0_CODE, 0, KIDT_ACCESS_RING0, I686_INTERRUPT_GATE);
SetIdtGate(ProcessorBlock->IdtBase, 0x03, (PVOID)ArTrap0x03, KGDT_R0_CODE, 0, KIDT_ACCESS_RING3, I686_TRAP_GATE);
SetIdtGate(ProcessorBlock->IdtBase, 0x04, (PVOID)ArTrap0x04, KGDT_R0_CODE, 0, KIDT_ACCESS_RING3, I686_TRAP_GATE);
SetIdtGate(ProcessorBlock->IdtBase, 0x05, (PVOID)ArTrap0x05, KGDT_R0_CODE, 0, KIDT_ACCESS_RING0, I686_TRAP_GATE);
SetIdtGate(ProcessorBlock->IdtBase, 0x06, (PVOID)ArTrap0x06, KGDT_R0_CODE, 0, KIDT_ACCESS_RING0, I686_TRAP_GATE);
SetIdtGate(ProcessorBlock->IdtBase, 0x07, (PVOID)ArTrap0x07, KGDT_R0_CODE, 0, KIDT_ACCESS_RING0, I686_TRAP_GATE);
SetIdtGate(ProcessorBlock->IdtBase, 0x08, (PVOID)ArTrap0x08, KGDT_R0_CODE, 0, KIDT_ACCESS_RING0, I686_TRAP_GATE);
SetIdtGate(ProcessorBlock->IdtBase, 0x09, (PVOID)ArTrap0x09, KGDT_R0_CODE, 0, KIDT_ACCESS_RING0, I686_TRAP_GATE);
SetIdtGate(ProcessorBlock->IdtBase, 0x0A, (PVOID)ArTrap0x0A, KGDT_R0_CODE, 0, KIDT_ACCESS_RING0, I686_TRAP_GATE);
SetIdtGate(ProcessorBlock->IdtBase, 0x0B, (PVOID)ArTrap0x0B, KGDT_R0_CODE, 0, KIDT_ACCESS_RING0, I686_TRAP_GATE);
SetIdtGate(ProcessorBlock->IdtBase, 0x0C, (PVOID)ArTrap0x0C, KGDT_R0_CODE, 0, KIDT_ACCESS_RING0, I686_TRAP_GATE);
SetIdtGate(ProcessorBlock->IdtBase, 0x0D, (PVOID)ArTrap0x0D, KGDT_R0_CODE, 0, KIDT_ACCESS_RING0, I686_TRAP_GATE);
SetIdtGate(ProcessorBlock->IdtBase, 0x0E, (PVOID)ArTrap0x0E, KGDT_R0_CODE, 0, KIDT_ACCESS_RING0, I686_TRAP_GATE);
SetIdtGate(ProcessorBlock->IdtBase, 0x10, (PVOID)ArTrap0x10, KGDT_R0_CODE, 0, KIDT_ACCESS_RING0, I686_TRAP_GATE);
SetIdtGate(ProcessorBlock->IdtBase, 0x11, (PVOID)ArTrap0x11, KGDT_R0_CODE, 0, KIDT_ACCESS_RING0, I686_TRAP_GATE);
SetIdtGate(ProcessorBlock->IdtBase, 0x12, (PVOID)ArTrap0x12, KGDT_R0_CODE, 0, KIDT_ACCESS_RING0, I686_TRAP_GATE);
SetIdtGate(ProcessorBlock->IdtBase, 0x13, (PVOID)ArTrap0x13, KGDT_R0_CODE, 0, KIDT_ACCESS_RING0, I686_TRAP_GATE);
SetIdtGate(ProcessorBlock->IdtBase, 0x2A, (PVOID)ArTrap0x2A, KGDT_R0_CODE, 0, KIDT_ACCESS_RING3, I686_TRAP_GATE);
SetIdtGate(ProcessorBlock->IdtBase, 0x2B, (PVOID)ArTrap0x2B, KGDT_R0_CODE, 0, KIDT_ACCESS_RING3, I686_TRAP_GATE);
SetIdtGate(ProcessorBlock->IdtBase, 0x2C, (PVOID)ArTrap0x2C, KGDT_R0_CODE, 0, KIDT_ACCESS_RING3, I686_TRAP_GATE);
SetIdtGate(ProcessorBlock->IdtBase, 0x2D, (PVOID)ArTrap0x2D, KGDT_R0_CODE, 0, KIDT_ACCESS_RING3, I686_TRAP_GATE);
SetIdtGate(ProcessorBlock->IdtBase, 0x2E, (PVOID)ArTrap0x2E, KGDT_R0_CODE, 0, KIDT_ACCESS_RING3, I686_TRAP_GATE);
SetIdtGate(ProcessorBlock->IdtBase, 0x00, (PVOID)ArTrap0x00, KGDT_R0_CODE, 0, KIDT_INTERRUPT | KIDT_ACCESS_RING0);
SetIdtGate(ProcessorBlock->IdtBase, 0x01, (PVOID)ArTrap0x01, KGDT_R0_CODE, 0, KIDT_INTERRUPT | KIDT_ACCESS_RING0);
SetIdtGate(ProcessorBlock->IdtBase, 0x02, (PVOID)ArTrap0x02, KGDT_R0_CODE, 0, KIDT_INTERRUPT | KIDT_ACCESS_RING0);
SetIdtGate(ProcessorBlock->IdtBase, 0x03, (PVOID)ArTrap0x03, KGDT_R0_CODE, 0, KIDT_INTERRUPT | KIDT_ACCESS_RING3);
SetIdtGate(ProcessorBlock->IdtBase, 0x04, (PVOID)ArTrap0x04, KGDT_R0_CODE, 0, KIDT_INTERRUPT | KIDT_ACCESS_RING3);
SetIdtGate(ProcessorBlock->IdtBase, 0x05, (PVOID)ArTrap0x05, KGDT_R0_CODE, 0, KIDT_INTERRUPT | KIDT_ACCESS_RING0);
SetIdtGate(ProcessorBlock->IdtBase, 0x06, (PVOID)ArTrap0x06, KGDT_R0_CODE, 0, KIDT_INTERRUPT | KIDT_ACCESS_RING0);
SetIdtGate(ProcessorBlock->IdtBase, 0x07, (PVOID)ArTrap0x07, KGDT_R0_CODE, 0, KIDT_INTERRUPT | KIDT_ACCESS_RING0);
SetIdtGate(ProcessorBlock->IdtBase, 0x08, (PVOID)ArTrap0x08, KGDT_R0_CODE, 0, KIDT_INTERRUPT | KIDT_ACCESS_RING0);
SetIdtGate(ProcessorBlock->IdtBase, 0x09, (PVOID)ArTrap0x09, KGDT_R0_CODE, 0, KIDT_INTERRUPT | KIDT_ACCESS_RING0);
SetIdtGate(ProcessorBlock->IdtBase, 0x0A, (PVOID)ArTrap0x0A, KGDT_R0_CODE, 0, KIDT_INTERRUPT | KIDT_ACCESS_RING0);
SetIdtGate(ProcessorBlock->IdtBase, 0x0B, (PVOID)ArTrap0x0B, KGDT_R0_CODE, 0, KIDT_INTERRUPT | KIDT_ACCESS_RING0);
SetIdtGate(ProcessorBlock->IdtBase, 0x0C, (PVOID)ArTrap0x0C, KGDT_R0_CODE, 0, KIDT_INTERRUPT | KIDT_ACCESS_RING0);
SetIdtGate(ProcessorBlock->IdtBase, 0x0D, (PVOID)ArTrap0x0D, KGDT_R0_CODE, 0, KIDT_INTERRUPT | KIDT_ACCESS_RING0);
SetIdtGate(ProcessorBlock->IdtBase, 0x0E, (PVOID)ArTrap0x0E, KGDT_R0_CODE, 0, KIDT_INTERRUPT | KIDT_ACCESS_RING0);
SetIdtGate(ProcessorBlock->IdtBase, 0x10, (PVOID)ArTrap0x10, KGDT_R0_CODE, 0, KIDT_INTERRUPT | KIDT_ACCESS_RING0);
SetIdtGate(ProcessorBlock->IdtBase, 0x11, (PVOID)ArTrap0x11, KGDT_R0_CODE, 0, KIDT_INTERRUPT | KIDT_ACCESS_RING0);
SetIdtGate(ProcessorBlock->IdtBase, 0x12, (PVOID)ArTrap0x12, KGDT_R0_CODE, 0, KIDT_INTERRUPT | KIDT_ACCESS_RING0);
SetIdtGate(ProcessorBlock->IdtBase, 0x13, (PVOID)ArTrap0x13, KGDT_R0_CODE, 0, KIDT_INTERRUPT | KIDT_ACCESS_RING0);
SetIdtGate(ProcessorBlock->IdtBase, 0x2A, (PVOID)ArTrap0x2A, KGDT_R0_CODE, 0, KIDT_INTERRUPT | KIDT_ACCESS_RING3);
SetIdtGate(ProcessorBlock->IdtBase, 0x2B, (PVOID)ArTrap0x2B, KGDT_R0_CODE, 0, KIDT_INTERRUPT | KIDT_ACCESS_RING3);
SetIdtGate(ProcessorBlock->IdtBase, 0x2C, (PVOID)ArTrap0x2C, KGDT_R0_CODE, 0, KIDT_INTERRUPT | KIDT_ACCESS_RING3);
SetIdtGate(ProcessorBlock->IdtBase, 0x2D, (PVOID)ArTrap0x2D, KGDT_R0_CODE, 0, KIDT_INTERRUPT | KIDT_ACCESS_RING3);
SetIdtGate(ProcessorBlock->IdtBase, 0x2E, (PVOID)ArTrap0x2E, KGDT_R0_CODE, 0, KIDT_INTERRUPT | KIDT_ACCESS_RING3);
}
/**
@@ -656,9 +656,6 @@ AR::ProcSup::SetGdtEntryBase(IN PKGDTENTRY Gdt,
* @param Access
* Supplies the gate access rights.
*
* @param Type
* Supplies the gate type.
*
* @return This routine does not return any value.
*
* @since XT 1.0
@@ -670,21 +667,13 @@ AR::ProcSup::SetIdtGate(IN PKIDTENTRY Idt,
IN PVOID Handler,
IN USHORT Selector,
IN USHORT Ist,
IN USHORT Dpl,
IN USHORT Type)
IN USHORT Access)
{
/* Set the handler's address */
/* Setup the gate */
Idt[Vector].Offset = (USHORT)((ULONG)Handler & 0xFFFF);
Idt[Vector].ExtendedOffset = (USHORT)((ULONG)Handler >> 16);
/* Set the code segment selector */
Idt[Vector].Access = 0x8000 | (Access << 8);
Idt[Vector].Selector = Selector;
/* Initialize the gate's attributes and flags */
Idt[Vector].Access = 0;
Idt[Vector].Dpl = Dpl;
Idt[Vector].Present = 1;
Idt[Vector].Type = Type;
}
/**

3
xtoskrnl/includes/ar/amd64/procsup.hh
View File

@@ -67,8 +67,7 @@ namespace AR
IN PVOID Handler,
IN USHORT Selector,
IN USHORT Ist,
IN USHORT Dpl,
IN USHORT Type);
IN USHORT Access);
};
}

3
xtoskrnl/includes/ar/i686/procsup.hh
View File

@@ -72,8 +72,7 @@ namespace AR
IN PVOID Handler,
IN USHORT Selector,
IN USHORT Ist,
IN USHORT Dpl,
IN USHORT Type);
IN USHORT Access);
STATIC XTAPI VOID SetNonMaskableInterruptTssEntry(IN PKPROCESSOR_BLOCK ProcessorBlock,
IN PVOID KernelFaultStack);

42
xtoskrnl/includes/ke/runlevel.hh
View File

@@ -22,48 +22,6 @@ namespace KE
STATIC XTFASTCALL VOID LowerRunLevel(IN KRUNLEVEL RunLevel);
STATIC XTFASTCALL KRUNLEVEL RaiseRunLevel(IN KRUNLEVEL RunLevel);
};
class LowerRunLevel
{
private:
KRUNLEVEL PreviousRunLevel;
public:
LowerRunLevel(KRUNLEVEL RunLevel)
{
PreviousRunLevel = KE::RunLevel::GetCurrentRunLevel();
KE::RunLevel::LowerRunLevel(RunLevel);
}
~LowerRunLevel()
{
KE::RunLevel::RaiseRunLevel(PreviousRunLevel);
}
LowerRunLevel(const LowerRunLevel&) = delete;
LowerRunLevel& operator=(const LowerRunLevel&) = delete;
};
class RaiseRunLevel
{
private:
KRUNLEVEL PreviousRunLevel;
public:
RaiseRunLevel(KRUNLEVEL RunLevel)
{
PreviousRunLevel = KE::RunLevel::GetCurrentRunLevel();
KE::RunLevel::RaiseRunLevel(RunLevel);
}
~RaiseRunLevel()
{
KE::RunLevel::LowerRunLevel(PreviousRunLevel);
}
RaiseRunLevel(const RaiseRunLevel&) = delete;
RaiseRunLevel& operator=(const RaiseRunLevel&) = delete;
};
}
#endif /* __XTOSKRNL_KE_RUNLEVEL_HH */

61
xtoskrnl/includes/ke/spinlock.hh
View File

@@ -17,73 +17,12 @@ namespace KE
{
class SpinLock
{
private:
STATIC KSPIN_LOCK DispatcherLockQueue;
STATIC KSPIN_LOCK ExpansionLockQueue;
STATIC KSPIN_LOCK FileSystemLockQueue;
STATIC KSPIN_LOCK IoCancelLockQueue;
STATIC KSPIN_LOCK IoCompletionLockQueue;
STATIC KSPIN_LOCK IoDatabaseLockQueue;
STATIC KSPIN_LOCK IoVpbLockQueue;
STATIC KSPIN_LOCK MasterLockQueue;
STATIC KSPIN_LOCK NonPagedAllocLockQueue;
STATIC KSPIN_LOCK NonPagedPoolLockQueue;
STATIC KSPIN_LOCK PfnLockQueue;
STATIC KSPIN_LOCK SystemSpaceLockQueue;
STATIC KSPIN_LOCK TimerTableLockQueue;
STATIC KSPIN_LOCK VacbLockQueue;
STATIC KSPIN_LOCK WorkLockQueue;
public:
STATIC XTFASTCALL VOID AcquireQueuedSpinLock(IN KSPIN_LOCK_QUEUE_LEVEL LockLevel);
STATIC XTFASTCALL VOID AcquireSpinLock(IN OUT PKSPIN_LOCK SpinLock);
STATIC XTAPI VOID InitializeAllLocks();
STATIC XTAPI VOID InitializeLockQueues();
STATIC XTAPI VOID InitializeSpinLock(IN PKSPIN_LOCK SpinLock);
STATIC XTFASTCALL VOID ReleaseQueuedSpinLock(IN KSPIN_LOCK_QUEUE_LEVEL LockLevel);
STATIC XTFASTCALL VOID ReleaseSpinLock(IN OUT PKSPIN_LOCK SpinLock);
STATIC XTFASTCALL BOOLEAN TestSpinLock(IN PKSPIN_LOCK SpinLock);
};
class QueuedSpinLockGuard
{
private:
KSPIN_LOCK_QUEUE_LEVEL QueuedLockLevel;
public:
QueuedSpinLockGuard(IN OUT KSPIN_LOCK_QUEUE_LEVEL LockLevel)
{
QueuedLockLevel = LockLevel;
KE::SpinLock::AcquireQueuedSpinLock(QueuedLockLevel);
}
~QueuedSpinLockGuard()
{
KE::SpinLock::ReleaseQueuedSpinLock(QueuedLockLevel);
}
QueuedSpinLockGuard(const QueuedSpinLockGuard&) = delete;
QueuedSpinLockGuard& operator=(const QueuedSpinLockGuard&) = delete;
};
class SpinLockGuard
{
private:
PKSPIN_LOCK SpinLock;
public:
SpinLockGuard(IN OUT PKSPIN_LOCK SpinLock)
{
KE::SpinLock::AcquireSpinLock(SpinLock);
}
~SpinLockGuard()
{
KE::SpinLock::ReleaseSpinLock(SpinLock);
}
SpinLockGuard(const SpinLockGuard&) = delete;
SpinLockGuard& operator=(const SpinLockGuard&) = delete;
};
}

8
xtoskrnl/includes/mm.hh
View File

@@ -12,14 +12,10 @@
#include <xtos.hh>
#include XTOS_ARCH_HEADER(mm, pagemap.hh)
#include XTOS_ARCH_HEADER(mm, paging.hh)
#include XTOS_ARCH_HEADER(mm, pte.hh)
#include <mm/colors.hh>
#include <mm/hlpool.hh>
#include <mm/init.hh>
#include <mm/kpool.hh>
#include <mm/mmgr.hh>
#include <mm/pfault.hh>
#include <mm/pfn.hh>
#include <mm/paging.hh>
#endif /* __XTOSKRNL_MM_HH */

78
xtoskrnl/includes/mm/amd64/pagemap.hh
View File

@@ -1,13 +1,13 @@
/**
* PROJECT: ExectOS
* COPYRIGHT: See COPYING.md in the top level directory
* FILE: xtoskrnl/includes/mm/amd64/pagemap.hh
* FILE: xtoskrnl/includes/mm/pagemap.hh
* DESCRIPTION: Low-level support for page map manipulation
* DEVELOPERS: Aiken Harris <harraiken91@gmail.com>
*/
#ifndef __XTOSKRNL_MM_AMD64_PAGEMAP_HH
#define __XTOSKRNL_MM_AMD64_PAGEMAP_HH
#ifndef __XTOSKRNL_MM_PAGEMAP_HH
#define __XTOSKRNL_MM_PAGEMAP_HH
#include <xtos.hh>
@@ -21,75 +21,33 @@ namespace MM
MMPAGEMAP_INFO PageMapInfo;
public:
XTAPI PMMPTE AdvancePte(IN PMMPTE Pte,
IN LONG Count);
XTAPI VOID ClearPte(IN PMMPTE PtePointer);
XTAPI ULONG_PTR GetNextEntry(IN PMMPTE Pte);
XTAPI PMMPTE GetNextPte(IN PMMPTE Pte);
XTAPI BOOLEAN GetOneEntry(IN PMMPTE Pte);
XTAPI PMMP5E GetP5eAddress(IN PVOID Address);
XTAPI ULONG GetP5eOffset(IN PVOID Address);
XTAPI PVOID GetP5eVirtualAddress(IN PMMP5E P5ePointer);
XTAPI PFN_NUMBER GetPageFrameNumber(IN PMMPTE Pte);
XTAPI PMMPDE GetPdeAddress(IN PVOID Address);
XTAPI ULONG GetPdeOffset(IN PVOID Address);
VIRTUAL XTAPI PVOID GetPdeVirtualAddress(IN PMMPDE PdePointer) = 0;
XTAPI PMMPPE GetPpeAddress(IN PVOID Address);
XTAPI ULONG GetPpeOffset(IN PVOID Address);
VIRTUAL XTAPI PVOID GetPpeVirtualAddress(IN PMMPPE PpePointer) = 0;
XTAPI ULONG_PTR GetPte(IN PMMPTE PtePointer);
XTAPI PMMPTE GetPteAddress(IN PVOID Address);
XTAPI LONG GetPteDistance(PMMPTE EndPte,
PMMPTE StartPte);
XTAPI ULONG GetPteOffset(IN PVOID Address);
XTAPI ULONG GetPteSize(VOID);
XTAPI ULONG GetPteSoftwareProtection(IN PMMPTE PtePointer);
XTAPI ULONG GetPteSoftwarePrototype(IN PMMPTE PtePointer);
XTAPI ULONG GetPteSoftwareTransition(IN PMMPTE PtePointer);
VIRTUAL XTAPI PVOID GetPteVirtualAddress(IN PMMPTE PtePointer) = 0;
XTAPI PMMPXE GetPxeAddress(IN PVOID Address);
XTAPI ULONG GetPxeOffset(IN PVOID Address);
VIRTUAL XTAPI PVOID GetPxeVirtualAddress(IN PMMPXE PxePointer) = 0;
XTAPI BOOLEAN GetXpaStatus();
VIRTUAL XTAPI VOID InitializePageMapInfo(VOID) = 0;
XTAPI BOOLEAN PteValid(IN PMMPTE PtePointer);
XTAPI VOID SetNextEntry(IN PMMPTE Pte,
IN ULONG_PTR Value);
XTAPI VOID SetOneEntry(IN PMMPTE Pte,
IN BOOLEAN Value);
XTAPI VOID SetPte(IN PMMPTE PtePointer,
IN PFN_NUMBER PageFrameNumber,
IN ULONG_PTR AttributesMask);
XTAPI VOID SetPte(IN PMMPTE PtePointer,
IN ULONG_PTR Attributes);
XTAPI VOID SetPteCaching(IN PMMPTE PtePointer,
IN BOOLEAN CacheDisable,
IN BOOLEAN WriteThrough);
XTAPI VOID TransitionPte(IN PMMPTE PointerPte,
IN ULONG_PTR Protection);
XTAPI VOID WritePte(IN PMMPTE Pte,
IN MMPTE Value);
XTAPI VOID ClearPte(PHARDWARE_PTE PtePointer);
XTAPI PMMP5E GetP5eAddress(PVOID Address);
XTAPI PMMPDE GetPdeAddress(PVOID Address);
XTAPI PMMPPE GetPpeAddress(PVOID Address);
XTAPI PMMPTE GetPteAddress(PVOID Address);
XTAPI PMMPXE GetPxeAddress(PVOID Address);
virtual XTAPI VOID InitializePageMapInfo(VOID) = 0;
XTAPI BOOLEAN PteValid(PHARDWARE_PTE PtePointer);
XTAPI VOID SetPte(PHARDWARE_PTE PtePointer,
PFN_NUMBER PageFrameNumber,
BOOLEAN Writable);
XTAPI VOID SetPteCaching(PHARDWARE_PTE PtePointer,
BOOLEAN CacheDisable,
BOOLEAN WriteThrough);
} PAGEMAP, *PPAGEMAP;
class PageMapBasic final : public PageMap
{
public:
XTAPI PVOID GetPdeVirtualAddress(IN PMMPDE PdePointer);
XTAPI PVOID GetPpeVirtualAddress(IN PMMPPE PpePointer);
XTAPI PVOID GetPteVirtualAddress(IN PMMPTE PtePointer);
XTAPI PVOID GetPxeVirtualAddress(IN PMMPXE PxePointer);
XTAPI VOID InitializePageMapInfo(VOID);
};
class PageMapXpa final : public PageMap
{
public:
XTAPI PVOID GetPdeVirtualAddress(IN PMMPDE PdePointer);
XTAPI PVOID GetPpeVirtualAddress(IN PMMPPE PpePointer);
XTAPI PVOID GetPteVirtualAddress(IN PMMPTE PtePointer);
XTAPI PVOID GetPxeVirtualAddress(IN PMMPXE PxePointer);
XTAPI VOID InitializePageMapInfo(VOID);
};
}
#endif /* __XTOSKRNL_MM_AMD64_PAGEMAP_HH */
#endif /* __XTOSKRNL_MM_PAGEMAP_HH */

78
xtoskrnl/includes/mm/amd64/paging.hh
View File

@@ -1,78 +0,0 @@
/**
* PROJECT: ExectOS
* COPYRIGHT: See COPYING.md in the top level directory
* FILE: xtoskrnl/includes/mm/amd64/paging.hh
* DESCRIPTION: Low level page management support for AMD64
* DEVELOPERS: Aiken Harris <harraiken91@gmail.com>
*/
#ifndef __XTOSKRNL_MM_AMD64_PAGING_HH
#define __XTOSKRNL_MM_AMD64_PAGING_HH
#include <xtos.hh>
/* Memory Manager */
namespace MM
{
class Paging
{
private:
STATIC PPAGEMAP PmlRoutines;
public:
STATIC XTAPI PMMPTE AdvancePte(IN PMMPTE Pte,
IN LONG Count);
STATIC XTAPI VOID ClearPte(IN PMMPTE PtePointer);
STATIC XTAPI VOID FlushTlb(VOID);
STATIC XTAPI ULONG_PTR GetNextEntry(IN PMMPTE Pte);
STATIC XTAPI PMMPTE GetNextPte(IN PMMPTE Pte);
STATIC XTAPI BOOLEAN GetOneEntry(IN PMMPTE Pte);
STATIC XTAPI PMMP5E GetP5eAddress(IN PVOID Address);
STATIC XTAPI PVOID GetP5eVirtualAddress(IN PMMP5E P5ePointer);
STATIC XTAPI PFN_NUMBER GetPageFrameNumber(IN PMMPTE Pte);
STATIC XTAPI PMMPDE GetPdeAddress(IN PVOID Address);
STATIC XTAPI PVOID GetPdeVirtualAddress(IN PMMPDE PdePointer);
STATIC XTAPI PMMPPE GetPpeAddress(IN PVOID Address);
STATIC XTAPI PVOID GetPpeVirtualAddress(IN PMMPPE PpePointer);
STATIC XTAPI ULONG_PTR GetPte(IN PMMPTE PtePointer);
STATIC XTAPI PMMPTE GetPteAddress(IN PVOID Address);
STATIC XTAPI LONG GetPteDistance(PMMPTE EndPte,
PMMPTE StartPte);
STATIC XTAPI ULONG GetPteSize(VOID);
STATIC XTAPI ULONG GetPteSoftwareProtection(IN PMMPTE PtePointer);
STATIC XTAPI ULONG GetPteSoftwarePrototype(IN PMMPTE PtePointer);
STATIC XTAPI ULONG GetPteSoftwareTransition(IN PMMPTE PtePointer);
STATIC XTAPI PVOID GetPteVirtualAddress(IN PMMPTE PtePointer);
STATIC XTAPI PMMPXE GetPxeAddress(IN PVOID Address);
STATIC XTAPI PVOID GetPxeVirtualAddress(IN PMMPXE PxePointer);
STATIC XTAPI BOOLEAN GetXpaStatus(VOID);
STATIC XTAPI VOID InitializePageMapSupport(VOID);
STATIC XTAPI BOOLEAN PteValid(IN PMMPTE PtePointer);
STATIC XTAPI VOID SetNextEntry(IN PMMPTE Pte,
IN ULONG_PTR Value);
STATIC XTAPI VOID SetOneEntry(IN PMMPTE Pte,
IN BOOLEAN Value);
STATIC XTAPI VOID SetPte(IN PMMPTE PtePointer,
IN PFN_NUMBER PageFrameNumber,
IN ULONG_PTR AttributesMask);
STATIC XTAPI VOID SetPte(IN PMMPTE PtePointer,
IN ULONG_PTR Attributes);
STATIC XTAPI VOID SetPteCaching(IN PMMPTE PtePointer,
IN BOOLEAN CacheDisable,
IN BOOLEAN WriteThrough);
STATIC XTAPI VOID WritePte(IN PMMPTE Pte,
IN MMPTE Value);
STATIC XTAPI VOID TransitionPte(IN PMMPTE PointerPte,
IN ULONG_PTR Protection);
STATIC XTFASTCALL VOID ZeroPages(IN PVOID Address,
IN ULONG Size);
private:
STATIC XTAPI BOOLEAN GetExtendedPhysicalAddressingStatus(VOID);
STATIC XTAPI PPAGEMAP GetPageMapBasicRoutines(VOID);
STATIC XTAPI PPAGEMAP GetPageMapXpaRoutines(VOID);
};
}
#endif /* __XTOSKRNL_MM_AMD64_PAGING_HH */

69
xtoskrnl/includes/mm/amd64/pte.hh
View File

@@ -1,69 +0,0 @@
/**
* PROJECT: ExectOS
* COPYRIGHT: See COPYING.md in the top level directory
* FILE: xtoskrnl/includes/mm/amd64/pte.hh
* DESCRIPTION: Page Table Entry (PTE) for AMD64 support
* DEVELOPERS: Aiken Harris <harraiken91@gmail.com>
*/
#ifndef __XTOSKRNL_MM_AMD64_PTE_HH
#define __XTOSKRNL_MM_AMD64_PTE_HH
#include <xtos.hh>
/* Memory Manager */
namespace MM
{
class Pte
{
private:
STATIC MMPTE FirstSystemFreePte[MaximumPtePoolTypes];
STATIC PMMPTE SystemPteBase;
STATIC PMMPTE SystemPtesEnd[MaximumPtePoolTypes];
STATIC PMMPTE SystemPtesStart[MaximumPtePoolTypes];
STATIC PFN_COUNT TotalSystemFreePtes[MaximumPtePoolTypes];
STATIC MMPTE ValidPte;
public:
STATIC XTAPI BOOLEAN AddressValid(IN PVOID VirtualAddress);
STATIC XTAPI PFN_COUNT GetPtesPerPage(VOID);
STATIC XTAPI PMMPTE GetSystemPteBaseAddress(VOID);
STATIC XTAPI PMMPTE GetValidPte(VOID);
STATIC XTAPI VOID InitializePageTable(VOID);
STATIC XTAPI VOID InitializeSystemPte(VOID);
STATIC XTAPI VOID InitializeSystemPteSpace(VOID);
STATIC XTAPI VOID MapP5E(IN PVOID StartAddress,
IN PVOID EndAddress,
IN PMMP5E TemplateP5e);
STATIC XTAPI VOID MapPDE(IN PVOID StartAddress,
IN PVOID EndAddress,
IN PMMPDE TemplatePde);
STATIC XTAPI VOID MapPPE(IN PVOID StartAddress,
IN PVOID EndAddress,
IN PMMPPE TemplatePpe);
STATIC XTAPI VOID MapPTE(IN PVOID StartAddress,
IN PVOID EndAddress,
IN PMMPTE TemplatePte);
STATIC XTAPI VOID MapPXE(IN PVOID StartAddress,
IN PVOID EndAddress,
IN PMMPXE TemplatePxe);
STATIC XTAPI VOID ReleaseSystemPtes(IN PMMPTE StartingPte,
IN PFN_COUNT NumberOfPtes,
IN MMSYSTEM_PTE_POOL_TYPE SystemPtePoolType);
STATIC XTAPI PMMPTE ReserveSystemPtes(IN PFN_COUNT NumberOfPtes,
IN MMSYSTEM_PTE_POOL_TYPE SystemPtePoolType);
private:
STATIC XTAPI BOOLEAN FindFreeCluster(IN PFN_COUNT NumberOfPtes,
IN MMSYSTEM_PTE_POOL_TYPE SystemPtePoolType,
OUT PMMPTE *FoundCluster,
OUT PMMPTE *PreviousClusterNode);
STATIC XTAPI ULONG GetClusterSize(IN PMMPTE Pte);
STATIC XTAPI VOID InitializeSystemPtePool(IN PMMPTE StartingPte,
IN PFN_COUNT NumberOfPtes,
IN MMSYSTEM_PTE_POOL_TYPE PoolType);
};
}
#endif /* __XTOSKRNL_MM_AMD64_PTE_HH */

38
xtoskrnl/includes/mm/colors.hh
View File

@@ -1,38 +0,0 @@
/**
* PROJECT: ExectOS
* COPYRIGHT: See COPYING.md in the top level directory
* FILE: xtoskrnl/includes/mm/colors.hh
* DESCRIPTION: Memory manager page coloring subsystem
* DEVELOPERS: Aiken Harris <harraiken91@gmail.com>
*/
#ifndef __XTOSKRNL_MM_COLORS_HH
#define __XTOSKRNL_MM_COLORS_HH
#include <xtos.hh>
/* Memory Manager */
namespace MM
{
class Colors
{
private:
STATIC PMMCOLOR_TABLES FreePages[FreePageList + 1];
STATIC MMPFNLIST ModifiedPages[MM_PAGING_COLORS];
STATIC ULONG PagingColors;
STATIC ULONG PagingColorsMask;
public:
STATIC XTAPI VOID ComputePageColoring(VOID);
STATIC XTAPI PMMCOLOR_TABLES GetFreePages(IN MMPAGELISTS PageList,
IN ULONG Color);
STATIC XTAPI PMMPFNLIST GetModifiedPages(IN ULONG Color);
STATIC XTAPI ULONG GetNextColor(VOID);
STATIC XTAPI ULONG GetPagingColors(VOID);
STATIC XTAPI ULONG GetPagingColorsMask(VOID);
STATIC XTAPI VOID InitializeColorTables(VOID);
};
}
#endif /* __XTOSKRNL_MM_PFN_HH */

143
xtoskrnl/includes/mm/i686/pagemap.hh
View File

@@ -1,13 +1,13 @@
/**
* PROJECT: ExectOS
* COPYRIGHT: See COPYING.md in the top level directory
* FILE: xtoskrnl/includes/mm/i686/pagemap.hh
* FILE: xtoskrnl/includes/mm/pagemap.hh
* DESCRIPTION: Low-level support for page map manipulation
* DEVELOPERS: Aiken Harris <harraiken91@gmail.com>
*/
#ifndef __XTOSKRNL_MM_I686_PAGEMAP_HH
#define __XTOSKRNL_MM_I686_PAGEMAP_HH
#ifndef __XTOSKRNL_MM_PAGEMAP_HH
#define __XTOSKRNL_MM_PAGEMAP_HH
#include <xtos.hh>
@@ -21,128 +21,45 @@ namespace MM
MMPAGEMAP_INFO PageMapInfo;
public:
VIRTUAL XTAPI PMMPTE AdvancePte(IN PMMPTE Pte,
IN ULONG Count) = 0;
VIRTUAL XTAPI VOID ClearPte(IN PMMPTE PtePointer) = 0;
VIRTUAL XTAPI ULONG_PTR GetNextEntry(IN PMMPTE Pte) = 0;
VIRTUAL XTAPI PMMPTE GetNextPte(IN PMMPTE Pte) = 0;
VIRTUAL XTAPI BOOLEAN GetOneEntry(IN PMMPTE Pte) = 0;
VIRTUAL XTAPI PFN_NUMBER GetPageFrameNumber(IN PMMPTE Pte) = 0;
XTAPI PMMPDE GetPdeAddress(IN PVOID Address);
XTAPI ULONG GetPdeOffset(IN PVOID Address);
VIRTUAL XTAPI PVOID GetPdeVirtualAddress(IN PMMPDE PdePointer) = 0;
XTAPI PMMPPE GetPpeAddress(IN PVOID Address);
XTAPI ULONG GetPpeOffset(IN PVOID Address);
XTAPI PVOID GetPpeVirtualAddress(IN PMMPPE PpePointer);
VIRTUAL XTAPI ULONG_PTR GetPte(IN PMMPTE PtePointer) = 0;
XTAPI PMMPTE GetPteAddress(IN PVOID Address);
XTAPI ULONG GetPteOffset(IN PVOID Address);
VIRTUAL XTAPI LONG GetPteDistance(PMMPTE EndPte,
PMMPTE StartPte) = 0;
VIRTUAL XTAPI ULONG GetPteSize(VOID) = 0;
VIRTUAL XTAPI ULONG GetPteSoftwareProtection(IN PMMPTE PtePointer) = 0;
VIRTUAL XTAPI ULONG GetPteSoftwarePrototype(IN PMMPTE PtePointer) = 0;
VIRTUAL XTAPI ULONG GetPteSoftwareTransition(IN PMMPTE PtePointer) = 0;
VIRTUAL XTAPI PVOID GetPteVirtualAddress(IN PMMPTE PtePointer) = 0;
XTAPI BOOLEAN GetXpaStatus();
VIRTUAL XTAPI VOID InitializePageMapInfo(VOID) = 0;
VIRTUAL XTAPI BOOLEAN PteValid(IN PMMPTE PtePointer) = 0;
VIRTUAL XTAPI VOID SetNextEntry(IN PMMPTE Pte,
IN ULONG_PTR Value) = 0;
VIRTUAL XTAPI VOID SetOneEntry(IN PMMPTE Pte,
IN BOOLEAN Value) = 0;
VIRTUAL XTAPI VOID SetPte(IN PMMPTE PtePointer,
IN PFN_NUMBER PageFrameNumber,
IN ULONG_PTR AttributesMask) = 0;
VIRTUAL XTAPI VOID SetPte(IN PMMPTE PtePointer,
IN ULONG_PTR Attributes) = 0;
VIRTUAL XTAPI VOID SetPteCaching(IN PMMPTE PtePointer,
IN BOOLEAN CacheDisable,
IN BOOLEAN WriteThrough) = 0;
VIRTUAL XTAPI VOID TransitionPte(IN PMMPTE PointerPte,
IN ULONG_PTR Protection) = 0;
VIRTUAL XTAPI VOID WritePte(IN PMMPTE Pte,
IN MMPTE Value) = 0;
XTAPI VOID ClearPte(PHARDWARE_PTE PtePointer);
XTAPI PMMPDE GetPdeAddress(PVOID Address);
XTAPI PMMPPE GetPpeAddress(PVOID Address);
XTAPI PMMPTE GetPteAddress(PVOID Address);
virtual XTAPI VOID InitializePageMapInfo(VOID) = 0;
virtual XTAPI BOOLEAN PteValid(PHARDWARE_PTE PtePointer) = 0;
virtual XTAPI VOID SetPte(PHARDWARE_PTE PtePointer,
PFN_NUMBER PageFrameNumber,
BOOLEAN Writable) = 0;
virtual XTAPI VOID SetPteCaching(PHARDWARE_PTE PtePointer,
BOOLEAN CacheDisable,
BOOLEAN WriteThrough) = 0;
} PAGEMAP, *PPAGEMAP;
class PageMapBasic final : public PageMap
{
public:
XTAPI PMMPTE AdvancePte(IN PMMPTE Pte,
IN ULONG Count);
XTAPI VOID ClearPte(IN PMMPTE PtePointer);
XTAPI ULONG_PTR GetNextEntry(IN PMMPTE Pte);
XTAPI PMMPTE GetNextPte(IN PMMPTE Pte);
XTAPI BOOLEAN GetOneEntry(IN PMMPTE Pte);
XTAPI PFN_NUMBER GetPageFrameNumber(IN PMMPTE Pte);
XTAPI PVOID GetPdeVirtualAddress(IN PMMPDE PdePointer);
XTAPI ULONG_PTR GetPte(IN PMMPTE PtePointer);
XTAPI LONG GetPteDistance(PMMPTE EndPte,
PMMPTE StartPte);
XTAPI ULONG GetPteSize(VOID);
XTAPI ULONG GetPteSoftwareProtection(IN PMMPTE PtePointer);
XTAPI ULONG GetPteSoftwarePrototype(IN PMMPTE PtePointer);
XTAPI ULONG GetPteSoftwareTransition(IN PMMPTE PtePointer);
XTAPI PVOID GetPteVirtualAddress(IN PMMPTE PtePointer);
XTAPI VOID InitializePageMapInfo(VOID);
XTAPI BOOLEAN PteValid(IN PMMPTE PtePointer);
XTAPI VOID SetNextEntry(IN PMMPTE Pte,
IN ULONG_PTR Value);
XTAPI VOID SetOneEntry(IN PMMPTE Pte,
IN BOOLEAN Value);
XTAPI VOID SetPte(IN PMMPTE PtePointer,
IN PFN_NUMBER PageFrameNumber,
IN ULONG_PTR AttributesMask);
XTAPI VOID SetPte(IN PMMPTE PtePointer,
IN ULONG_PTR Attributes);
XTAPI VOID SetPteCaching(IN PMMPTE PtePointer,
IN BOOLEAN CacheDisable,
IN BOOLEAN WriteThrough);
XTAPI VOID TransitionPte(IN PMMPTE PointerPte,
IN ULONG_PTR Protection);
XTAPI VOID WritePte(IN PMMPTE Pte,
IN MMPTE Value);
XTAPI BOOLEAN PteValid(PHARDWARE_PTE PtePointer);
XTAPI VOID SetPte(PHARDWARE_PTE PtePointer,
PFN_NUMBER PageFrameNumber,
BOOLEAN Writable);
XTAPI VOID SetPteCaching(PHARDWARE_PTE PtePointer,
BOOLEAN CacheDisable,
BOOLEAN WriteThrough);
};
class PageMapXpa final : public PageMap
{
public:
XTAPI PMMPTE AdvancePte(IN PMMPTE Pte,
IN ULONG Count);
XTAPI VOID ClearPte(IN PMMPTE PtePointer);
XTAPI ULONG_PTR GetNextEntry(IN PMMPTE Pte);
XTAPI PMMPTE GetNextPte(IN PMMPTE Pte);
XTAPI BOOLEAN GetOneEntry(IN PMMPTE Pte);
XTAPI PFN_NUMBER GetPageFrameNumber(IN PMMPTE Pte);
XTAPI PVOID GetPdeVirtualAddress(IN PMMPDE PdePointer);
XTAPI ULONG_PTR GetPte(IN PMMPTE PtePointer);
XTAPI LONG GetPteDistance(PMMPTE EndPte,
PMMPTE StartPte);
XTAPI ULONG GetPteSize(VOID);
XTAPI ULONG GetPteSoftwareProtection(IN PMMPTE PtePointer);
XTAPI ULONG GetPteSoftwarePrototype(IN PMMPTE PtePointer);
XTAPI ULONG GetPteSoftwareTransition(IN PMMPTE PtePointer);
XTAPI PVOID GetPteVirtualAddress(IN PMMPTE PtePointer);
XTAPI VOID InitializePageMapInfo(VOID);
XTAPI BOOLEAN PteValid(IN PMMPTE PtePointer);
XTAPI VOID SetNextEntry(IN PMMPTE Pte,
IN ULONG_PTR Value);
XTAPI VOID SetOneEntry(IN PMMPTE Pte,
IN BOOLEAN Value);
XTAPI VOID SetPte(IN PMMPTE PtePointer,
IN PFN_NUMBER PageFrameNumber,
IN ULONG_PTR AttributesMask);
XTAPI VOID SetPte(IN PMMPTE PtePointer,
IN ULONG_PTR Attributes);
XTAPI VOID SetPteCaching(IN PMMPTE PtePointer,
IN BOOLEAN CacheDisable,
IN BOOLEAN WriteThrough);
XTAPI VOID TransitionPte(IN PMMPTE PointerPte,
IN ULONG_PTR Protection);
XTAPI VOID WritePte(IN PMMPTE Pte,
IN MMPTE Value);
XTAPI BOOLEAN PteValid(PHARDWARE_PTE PtePointer);
XTAPI VOID SetPte(PHARDWARE_PTE PtePointer,
PFN_NUMBER PageFrameNumber,
BOOLEAN Writable);
XTAPI VOID SetPteCaching(PHARDWARE_PTE PtePointer,
BOOLEAN CacheDisable,
BOOLEAN WriteThrough);
};
}
#endif /* __XTOSKRNL_MM_I686_PAGEMAP_HH */
#endif /* __XTOSKRNL_MM_PAGEMAP_HH */

74
xtoskrnl/includes/mm/i686/paging.hh
View File

@@ -1,74 +0,0 @@
/**
* PROJECT: ExectOS
* COPYRIGHT: See COPYING.md in the top level directory
* FILE: xtoskrnl/includes/mm/i686/paging.hh
* DESCRIPTION: Low level page management support for i686
* DEVELOPERS: Aiken Harris <harraiken91@gmail.com>
*/
#ifndef __XTOSKRNL_MM_I686_PAGING_HH
#define __XTOSKRNL_MM_I686_PAGING_HH
#include <xtos.hh>
/* Memory Manager */
namespace MM
{
class Paging
{
private:
STATIC PPAGEMAP PmlRoutines;
public:
STATIC XTAPI PMMPTE AdvancePte(IN PMMPTE Pte,
IN LONG Count);
STATIC XTAPI VOID ClearPte(IN PMMPTE PtePointer);
STATIC XTAPI VOID FlushTlb(VOID);
STATIC XTAPI ULONG_PTR GetNextEntry(IN PMMPTE Pte);
STATIC XTAPI PMMPTE GetNextPte(IN PMMPTE Pte);
STATIC XTAPI BOOLEAN GetOneEntry(IN PMMPTE Pte);
STATIC XTAPI PFN_NUMBER GetPageFrameNumber(IN PMMPTE Pte);
STATIC XTAPI PMMPDE GetPdeAddress(IN PVOID Address);
STATIC XTAPI PVOID GetPdeVirtualAddress(IN PMMPDE PdePointer);
STATIC XTAPI PMMPPE GetPpeAddress(IN PVOID Address);
STATIC XTAPI PVOID GetPpeVirtualAddress(IN PMMPPE PpePointer);
STATIC XTAPI ULONG_PTR GetPte(IN PMMPTE PtePointer);
STATIC XTAPI PMMPTE GetPteAddress(IN PVOID Address);
STATIC XTAPI LONG GetPteDistance(PMMPTE EndPte,
PMMPTE StartPte);
STATIC XTAPI ULONG GetPteSize(VOID);
STATIC XTAPI ULONG GetPteSoftwareProtection(IN PMMPTE PtePointer);
STATIC XTAPI ULONG GetPteSoftwarePrototype(IN PMMPTE PtePointer);
STATIC XTAPI ULONG GetPteSoftwareTransition(IN PMMPTE PtePointer);
STATIC XTAPI PVOID GetPteVirtualAddress(IN PMMPTE PtePointer);
STATIC XTAPI BOOLEAN GetXpaStatus(VOID);
STATIC XTAPI VOID InitializePageMapSupport(VOID);
STATIC XTAPI BOOLEAN PteValid(IN PMMPTE PtePointer);
STATIC XTAPI VOID SetNextEntry(IN PMMPTE Pte,
IN ULONG_PTR Value);
STATIC XTAPI VOID SetOneEntry(IN PMMPTE Pte,
IN BOOLEAN Value);
STATIC XTAPI VOID SetPte(IN PMMPTE PtePointer,
IN PFN_NUMBER PageFrameNumber,
IN ULONG_PTR AttributesMask);
STATIC XTAPI VOID SetPte(IN PMMPTE PtePointer,
IN ULONG_PTR Attributes);
STATIC XTAPI VOID SetPteCaching(IN PMMPTE PtePointer,
IN BOOLEAN CacheDisable,
IN BOOLEAN WriteThrough);
STATIC XTAPI VOID WritePte(IN PMMPTE Pte,
IN MMPTE Value);
STATIC XTAPI VOID TransitionPte(IN PMMPTE PointerPte,
IN ULONG_PTR Protection);
STATIC XTFASTCALL VOID ZeroPages(IN PVOID Address,
IN ULONG Size);
private:
STATIC XTAPI BOOLEAN GetExtendedPhysicalAddressingStatus(VOID);
STATIC XTAPI PPAGEMAP GetPageMapBasicRoutines(VOID);
STATIC XTAPI PPAGEMAP GetPageMapXpaRoutines(VOID);
};
}
#endif /* __XTOSKRNL_MM_I686_PAGING_HH */

63
xtoskrnl/includes/mm/i686/pte.hh
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@@ -1,63 +0,0 @@
/**
* PROJECT: ExectOS
* COPYRIGHT: See COPYING.md in the top level directory
* FILE: xtoskrnl/includes/mm/i686/pte.hh
* DESCRIPTION: Page Table Entry (PTE) for i686 support
* DEVELOPERS: Aiken Harris <harraiken91@gmail.com>
*/
#ifndef __XTOSKRNL_MM_I686_PTE_HH
#define __XTOSKRNL_MM_I686_PTE_HH
#include <xtos.hh>
/* Memory Manager */
namespace MM
{
class Pte
{
private:
STATIC MMPTE FirstSystemFreePte[MaximumPtePoolTypes];
STATIC PMMPTE SystemPteBase;
STATIC PMMPTE SystemPtesEnd[MaximumPtePoolTypes];
STATIC PMMPTE SystemPtesStart[MaximumPtePoolTypes];
STATIC PFN_COUNT TotalSystemFreePtes[MaximumPtePoolTypes];
STATIC MMPTE ValidPte;
public:
STATIC XTAPI BOOLEAN AddressValid(IN PVOID VirtualAddress);
STATIC XTAPI PFN_COUNT GetPtesPerPage(VOID);
STATIC XTAPI PMMPTE GetSystemPteBaseAddress(VOID);
STATIC XTAPI PMMPTE GetValidPte(VOID);
STATIC XTAPI VOID InitializePageTable(VOID);
STATIC XTAPI VOID InitializeSystemPte(VOID);
STATIC XTAPI VOID InitializeSystemPteSpace(VOID);
STATIC XTAPI VOID MapPDE(IN PVOID StartAddress,
IN PVOID EndAddress,
IN PMMPDE TemplatePde);
STATIC XTAPI VOID MapPPE(IN PVOID StartAddress,
IN PVOID EndAddress,
IN PMMPPE TemplatePpe);
STATIC XTAPI VOID MapPTE(IN PVOID StartAddress,
IN PVOID EndAddress,
IN PMMPTE TemplatePte);
STATIC XTAPI VOID ReleaseSystemPtes(IN PMMPTE StartingPte,
IN PFN_COUNT NumberOfPtes,
IN MMSYSTEM_PTE_POOL_TYPE SystemPtePoolType);
STATIC XTAPI PMMPTE ReserveSystemPtes(IN PFN_COUNT NumberOfPtes,
IN MMSYSTEM_PTE_POOL_TYPE SystemPtePoolType);
private:
STATIC XTAPI BOOLEAN FindFreeCluster(IN PFN_COUNT NumberOfPtes,
IN MMSYSTEM_PTE_POOL_TYPE SystemPtePoolType,
OUT PMMPTE *FoundCluster,
OUT PMMPTE *PreviousClusterNode);
STATIC XTAPI ULONG GetClusterSize(IN PMMPTE Pte);
STATIC XTAPI VOID InitializeSystemPtePool(IN PMMPTE StartingPte,
IN PFN_COUNT NumberOfPtes,
IN MMSYSTEM_PTE_POOL_TYPE PoolType);
};
}
#endif /* __XTOSKRNL_MM_I686_PTE_HH */

39
xtoskrnl/includes/mm/init.hh Normal file
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@@ -0,0 +1,39 @@
/**
* PROJECT: ExectOS
* COPYRIGHT: See COPYING.md in the top level directory
* FILE: xtoskrnl/includes/mm/init.hh
* DESCRIPTION: Memory Manager initialization
* DEVELOPERS: Aiken Harris <harraiken91@gmail.com>
*/
#ifndef __XTOSKRNL_MM_INIT_HH
#define __XTOSKRNL_MM_INIT_HH
#include <xtos.hh>
/* Memory Manager */
namespace MM
{
class Init
{
private:
STATIC PLOADER_MEMORY_DESCRIPTOR FreeDescriptor;
STATIC ULONG_PTR HighestPhysicalPage;
STATIC ULONG_PTR LowestPhysicalPage;
STATIC ULONG NumberOfPhysicalPages;
STATIC LOADER_MEMORY_DESCRIPTOR OldFreeDescriptor;
public:
STATIC XTAPI VOID InitializeMemoryManager(VOID);
STATIC XTAPI VOID InitializePageMapSupport(VOID);
STATIC XTAPI VOID ScanMemoryDescriptors(VOID);
private:
STATIC XTAPI VOID InitializeArchitecture(VOID);
STATIC XTAPI BOOLEAN VerifyMemoryTypeFree(LOADER_MEMORY_TYPE MemoryType);
STATIC XTAPI BOOLEAN VerifyMemoryTypeInvisible(LOADER_MEMORY_TYPE MemoryType);
};
}
#endif /* __XTOSKRNL_MM_INIT_HH */

9
xtoskrnl/includes/mm/kpool.hh
View File

@@ -21,12 +21,13 @@ namespace MM
STATIC UCHAR ProcessorStructuresData[MAXIMUM_PROCESSORS][KPROCESSOR_STRUCTURES_SIZE];
public:
STATIC XTAPI XTSTATUS AllocateKernelStack(OUT PVOID *Stack,
IN ULONG StackSize);
STATIC XTAPI XTSTATUS AllocateKernelStack(IN PVOID *Stack,
IN BOOLEAN LargeStack,
IN UCHAR SystemNode);
STATIC XTAPI XTSTATUS AllocateProcessorStructures(IN ULONG CpuNumber,
OUT PVOID *StructuresData);
OUT PVOID *StructuresData);
STATIC XTAPI VOID FreeKernelStack(IN PVOID Stack,
IN ULONG StackSize);
IN BOOLEAN LargeStack);
STATIC XTAPI VOID FreeProcessorStructures(IN PVOID StructuresData);
};
}

35
xtoskrnl/includes/mm/mmgr.hh
View File

@@ -1,35 +0,0 @@
/**
* PROJECT: ExectOS
* COPYRIGHT: See COPYING.md in the top level directory
* FILE: xtoskrnl/includes/mm/mmgr.hh
* DESCRIPTION: Memory Manager
* DEVELOPERS: Aiken Harris <harraiken91@gmail.com>
*/
#ifndef __XTOSKRNL_MM_MMGR_HH
#define __XTOSKRNL_MM_MMGR_HH
#include <xtos.hh>
/* Memory Manager */
namespace MM
{
class Manager
{
private:
STATIC MMMEMORY_LAYOUT MemoryLayout;
STATIC PFN_NUMBER NumberOfSystemPtes;
public:
STATIC XTAPI ULONG_PTR GetInstalledMemorySize(VOID);
STATIC XTAPI PMMMEMORY_LAYOUT GetMemoryLayout(VOID);
STATIC XTAPI PFN_NUMBER GetNumberOfSystemPtes();
STATIC XTAPI VOID InitializeMemoryLayout(VOID);
STATIC XTAPI VOID InitializeMemoryManager(VOID);
STATIC XTAPI BOOLEAN VerifyMemoryTypeFree(LOADER_MEMORY_TYPE MemoryType);
STATIC XTAPI BOOLEAN VerifyMemoryTypeInvisible(LOADER_MEMORY_TYPE MemoryType);
};
}
#endif /* __XTOSKRNL_MM_MMGR_HH */

47
xtoskrnl/includes/mm/paging.hh Normal file
View File

@@ -0,0 +1,47 @@
/**
* PROJECT: ExectOS
* COPYRIGHT: See COPYING.md in the top level directory
* FILE: xtoskrnl/includes/mm/paging.hh
* DESCRIPTION: Low level page management support
* DEVELOPERS: Aiken Harris <harraiken91@gmail.com>
*/
#ifndef __XTOSKRNL_MM_PAGING_HH
#define __XTOSKRNL_MM_PAGING_HH
#include <xtos.hh>
/* Memory Manager */
namespace MM
{
class Paging
{
private:
STATIC PPAGEMAP PmlRoutines;
public:
STATIC XTAPI VOID ClearPte(PHARDWARE_PTE PtePointer);
STATIC XTAPI VOID FlushTlb(VOID);
STATIC XTAPI PMMPDE GetPdeAddress(PVOID Address);
STATIC XTAPI PMMPPE GetPpeAddress(PVOID Address);
STATIC XTAPI PMMPTE GetPteAddress(PVOID Address);
STATIC XTAPI VOID InitializePageMapSupport(VOID);
STATIC XTAPI BOOLEAN PteValid(PHARDWARE_PTE PtePointer);
STATIC XTAPI VOID SetPte(PHARDWARE_PTE PtePointer,
PFN_NUMBER PageFrameNumber,
BOOLEAN Writable);
STATIC XTAPI VOID SetPteCaching(PHARDWARE_PTE PtePointer,
BOOLEAN CacheDisable,
BOOLEAN WriteThrough);
STATIC XTFASTCALL VOID ZeroPages(IN PVOID Address,
IN ULONG Size);
private:
STATIC XTAPI BOOLEAN GetExtendedPhysicalAddressingStatus(VOID);
STATIC XTAPI PPAGEMAP GetPageMapBasicRoutines(VOID);
STATIC XTAPI PPAGEMAP GetPageMapXpaRoutines(VOID);
};
}
#endif /* __XTOSKRNL_MM_PAGING_HH */

25
xtoskrnl/includes/mm/pfault.hh
View File

@@ -1,25 +0,0 @@
/**
* PROJECT: ExectOS
* COPYRIGHT: See COPYING.md in the top level directory
* FILE: xtoskrnl/includes/mm/pfault.hh
* DESCRIPTION: Page fault support
* DEVELOPERS: Aiken Harris <harraiken91@gmail.com>
*/
#ifndef __XTOSKRNL_MM_PFAULT_HH
#define __XTOSKRNL_MM_PFAULT_HH
#include <xtos.hh>
/* Memory Manager */
namespace MM
{
class PageFault
{
public:
STATIC XTFASTCALL XTSTATUS CheckPdeForPagedPool(IN PVOID VirtualAddress);
};
}
#endif /* __XTOSKRNL_MM_PFAULT_HH */

79
xtoskrnl/includes/mm/pfn.hh
View File

@@ -1,79 +0,0 @@
/**
* PROJECT: ExectOS
* COPYRIGHT: See COPYING.md in the top level directory
* FILE: xtoskrnl/includes/mm/pfn.hh
* DESCRIPTION: Physical Frame Number (PFN) support
* DEVELOPERS: Aiken Harris <harraiken91@gmail.com>
*/
#ifndef __XTOSKRNL_MM_PFN_HH
#define __XTOSKRNL_MM_PFN_HH
#include <xtos.hh>
/* Memory Manager */
namespace MM
{
class Pfn
{
private:
STATIC PFN_NUMBER AvailablePages;
STATIC MMPFNLIST BadPagesList;
STATIC PLOADER_MEMORY_DESCRIPTOR FreeDescriptor;
STATIC MMPFNLIST FreePagesList;
STATIC ULONG_PTR HighestPhysicalPage;
STATIC PVOID HighestUserAddress;
STATIC ULONG_PTR LowestPhysicalPage;
STATIC MMPFNLIST ModifiedPagesList;
STATIC MMPFNLIST ModifiedReadOnlyPagesList;
STATIC ULONGLONG NumberOfPhysicalPages;
STATIC LOADER_MEMORY_DESCRIPTOR OriginalFreeDescriptor;
STATIC PMMPFNLIST PageLocationList[];
STATIC PFN_NUMBER PfnDatabaseSize;
STATIC MMPFNLIST RomPagesList;
STATIC MMPFNLIST StandbyPagesList;
STATIC MMPFNLIST ZeroedPagesList;
public:
STATIC XTAPI PFN_NUMBER AllocateBootstrapPages(IN PFN_NUMBER NumberOfPages);
STATIC XTAPI PFN_NUMBER AllocatePhysicalPage(IN ULONG Color);
STATIC XTAPI VOID ComputePfnDatabaseSize(VOID);
STATIC XTAPI VOID DecrementReferenceCount(IN PMMPFN Pfn1,
IN PFN_NUMBER PageFrameIndex,
IN BOOLEAN BeginStandbyList = FALSE);
STATIC XTAPI VOID DecrementShareCount(IN PMMPFN Pfn1,
IN PFN_NUMBER PageFrameIndex,
IN BOOLEAN BeginStandbyList = FALSE);
STATIC XTAPI VOID FreePhysicalPage(IN PMMPTE PointerPte);
STATIC XTAPI ULONG_PTR GetHighestPhysicalPage(VOID);
STATIC XTAPI ULONGLONG GetNumberOfPhysicalPages(VOID);
STATIC XTAPI PFN_NUMBER GetPfnDatabaseSize(VOID);
STATIC XTAPI PMMPFN GetPfnEntry(IN PFN_NUMBER Pfn);
STATIC XTAPI VOID InitializePfnDatabase(VOID);
STATIC VOID XTAPI LinkPfnToPte(IN PFN_NUMBER PageFrameIndex,
IN PMMPTE PointerPte,
IN BOOLEAN Modified);
STATIC XTAPI VOID ScanMemoryDescriptors(VOID);
private:
STATIC XTAPI VOID DecrementAvailablePages(VOID);
STATIC XTAPI VOID IncrementAvailablePages(VOID);
STATIC XTAPI VOID InitializePageTablePfns(VOID);
STATIC XTAPI VOID LinkFreePage(IN PFN_NUMBER PageFrameIndex);
STATIC XTAPI VOID LinkPage(IN PMMPFNLIST ListHead,
IN PFN_NUMBER PageFrameIndex);
STATIC XTAPI VOID LinkPfnForPageTable(IN PFN_NUMBER PageFrameIndex,
IN PMMPTE PointerPte);
STATIC XTFASTCALL VOID LinkStandbyPage(IN PFN_NUMBER PageFrameIndex);
STATIC XTAPI VOID ProcessMemoryDescriptor(IN PFN_NUMBER BasePage,
IN PFN_NUMBER PageCount,
IN LOADER_MEMORY_TYPE MemoryType);
STATIC XTAPI VOID ScanPageTable(IN PMMPTE PointerPte,
IN ULONG Level);
STATIC XTAPI PFN_NUMBER UnlinkFreePage(IN PFN_NUMBER PageFrameIndex,
IN ULONG Color);
};
}
#endif /* __XTOSKRNL_MM_PFN_HH */

7
xtoskrnl/ke/amd64/krnlinit.cc
View File

@@ -86,10 +86,6 @@ KE::KernelInit::StartKernel(VOID)
/* Save processor state */
Processor::SaveProcessorState(&Prcb->ProcessorState);
/* Initialize spin locks */
SpinLock::InitializeAllLocks();
SpinLock::InitializeLockQueues();
/* Lower to APC runlevel */
RunLevel::LowerRunLevel(APC_LEVEL);
@@ -112,9 +108,6 @@ KE::KernelInit::StartKernel(VOID)
CurrentThread->WaitRunLevel = DISPATCH_LEVEL;
CurrentProcess->ActiveProcessors |= (ULONG_PTR)1 << Prcb->CpuNumber;
/* Initialize Memory Manager */
MM::Manager::InitializeMemoryManager();
/* Enter infinite loop */
DebugPrint(L"KernelInit::StartKernel() finished. Entering infinite loop.\n");
Crash::HaltSystem();

57
xtoskrnl/ke/data.cc
View File

@@ -12,6 +12,12 @@
/* Kernel initialization block passed by boot loader */
PKERNEL_INITIALIZATION_BLOCK KE::BootInformation::InitializationBlock = {};
/* Kernel boot resources list */
LIST_ENTRY KE::SystemResources::ResourcesListHead;
/* Kernel boot resources lock */
KSPIN_LOCK KE::SystemResources::ResourcesLock;
/* Kernel initial process */
EPROCESS KE::KProcess::InitialProcess;
@@ -20,54 +26,3 @@ ETHREAD KE::KThread::InitialThread = {};
/* Kernel UBSAN active frame flag */
BOOLEAN KE::KUbsan::ActiveFrame = FALSE;
/* Kernel dispatcher lock queue */
KSPIN_LOCK KE::SpinLock::DispatcherLockQueue;
/* Kernel expansion lock queue */
KSPIN_LOCK KE::SpinLock::ExpansionLockQueue;
/* Kernel file system structures lock queue */
KSPIN_LOCK KE::SpinLock::FileSystemLockQueue;
/* Kernel IO cancel lock queue */
KSPIN_LOCK KE::SpinLock::IoCancelLockQueue;
/* Kernel IO completion lock queue */
KSPIN_LOCK KE::SpinLock::IoCompletionLockQueue;
/* Kernel IO database lock queue */
KSPIN_LOCK KE::SpinLock::IoDatabaseLockQueue;
/* Kernel IO VPB lock queue */
KSPIN_LOCK KE::SpinLock::IoVpbLockQueue;
/* Kernel cache master lock queue */
KSPIN_LOCK KE::SpinLock::MasterLockQueue;
/* Kernel non-paged allocator lock queue */
KSPIN_LOCK KE::SpinLock::NonPagedAllocLockQueue;
/* Kernel non-paged pool lock queue */
KSPIN_LOCK KE::SpinLock::NonPagedPoolLockQueue;
/* Kernel PFN lock queue */
KSPIN_LOCK KE::SpinLock::PfnLockQueue;
/* Kernel system space lock queue */
KSPIN_LOCK KE::SpinLock::SystemSpaceLockQueue;
/* Kernel Timer table lock queue */
KSPIN_LOCK KE::SpinLock::TimerTableLockQueue;
/* Kernel VACB lock queue */
KSPIN_LOCK KE::SpinLock::VacbLockQueue;
/* Kernel work queue lock queue */
KSPIN_LOCK KE::SpinLock::WorkLockQueue;
/* Kernel boot resources list */
LIST_ENTRY KE::SystemResources::ResourcesListHead;
/* Kernel boot resources lock */
KSPIN_LOCK KE::SystemResources::ResourcesLock;

7
xtoskrnl/ke/i686/krnlinit.cc
View File

@@ -86,10 +86,6 @@ KE::KernelInit::StartKernel(VOID)
/* Save processor state */
Processor::SaveProcessorState(&Prcb->ProcessorState);
/* Initialize spin locks */
SpinLock::InitializeAllLocks();
SpinLock::InitializeLockQueues();
/* Lower to APC runlevel */
RunLevel::LowerRunLevel(APC_LEVEL);
@@ -112,9 +108,6 @@ KE::KernelInit::StartKernel(VOID)
CurrentThread->WaitRunLevel = DISPATCH_LEVEL;
CurrentProcess->ActiveProcessors |= (ULONG_PTR)1 << Prcb->CpuNumber;
/* Initialize Memory Manager */
MM::Manager::InitializeMemoryManager();
/* Enter infinite loop */
DebugPrint(L"KernelInit::StartKernel() finished. Entering infinite loop.\n");
Crash::HaltSystem();

2
xtoskrnl/ke/kthread.cc
View File

@@ -152,7 +152,7 @@ KE::KThread::InitializeThread(IN PKPROCESS Process,
if(!Stack)
{
/* Allocate new stack */
Status = MM::KernelPool::AllocateKernelStack(&Stack, KERNEL_STACK_SIZE);
Status = MM::KernelPool::AllocateKernelStack(&Stack, FALSE, 0);
if(Status != STATUS_SUCCESS || !Stack)
{
/* Stack allocation failed */

99
xtoskrnl/ke/spinlock.cc
View File

@@ -4,7 +4,6 @@
* FILE: xtoskrnl/ke/spinlock.cc
* DESCRIPTION: Spinlocks support
* DEVELOPERS: Rafal Kupiec <belliash@codingworkshop.eu.org>
* Aiken Harris <harraiken91@gmail.com>
*/
#include <xtos.hh>
@@ -57,78 +56,6 @@ KE::SpinLock::AcquireSpinLock(IN OUT PKSPIN_LOCK SpinLock)
AR::CpuFunc::ReadWriteBarrier();
}
/**
* Initializes all kernel spinlocks.
*
* @return This routine does not return any value.
*
* @since XT 1.0
*/
XTAPI
VOID
KE::SpinLock::InitializeAllLocks()
{
/* Initialize all spin locks */
InitializeSpinLock(&DispatcherLockQueue);
InitializeSpinLock(&PfnLockQueue);
InitializeSpinLock(&SystemSpaceLockQueue);
}
/**
* Initializes spinlock queues for current processor.
*
* @return This routine does not return any value.
*
* @since XT 1.0
*/
XTAPI
VOID
KE::SpinLock::InitializeLockQueues()
{
PKPROCESSOR_CONTROL_BLOCK ControlBlock;
/* Get current processor control block */
ControlBlock = KE::Processor::GetCurrentProcessorControlBlock();
/* Initialize PCB lock queues */
ControlBlock->LockQueue[DispatcherLock].Lock = &DispatcherLockQueue;
ControlBlock->LockQueue[DispatcherLock].Next = NULLPTR;
ControlBlock->LockQueue[ExpansionLock].Lock = &ExpansionLockQueue;
ControlBlock->LockQueue[ExpansionLock].Next = NULLPTR;
ControlBlock->LockQueue[PfnLock].Lock = &PfnLockQueue;
ControlBlock->LockQueue[PfnLock].Next = NULLPTR;
ControlBlock->LockQueue[SystemSpaceLock].Lock = &SystemSpaceLockQueue;
ControlBlock->LockQueue[SystemSpaceLock].Next = NULLPTR;
ControlBlock->LockQueue[VacbLock].Lock = &VacbLockQueue;
ControlBlock->LockQueue[VacbLock].Next = NULLPTR;
ControlBlock->LockQueue[MasterLock].Lock = &MasterLockQueue;
ControlBlock->LockQueue[MasterLock].Next = NULLPTR;
ControlBlock->LockQueue[NonPagedAllocPoolLock].Lock = &NonPagedAllocLockQueue;
ControlBlock->LockQueue[NonPagedAllocPoolLock].Next = NULLPTR;
ControlBlock->LockQueue[IoCancelLock].Lock = &IoCancelLockQueue;
ControlBlock->LockQueue[IoCancelLock].Next = NULLPTR;
ControlBlock->LockQueue[WorkQueueLock].Lock = &WorkLockQueue;
ControlBlock->LockQueue[WorkQueueLock].Next = NULLPTR;
ControlBlock->LockQueue[IoVpbLock].Lock = &IoVpbLockQueue;
ControlBlock->LockQueue[IoVpbLock].Next = NULLPTR;
ControlBlock->LockQueue[IoDatabaseLock].Lock = &IoDatabaseLockQueue;
ControlBlock->LockQueue[IoDatabaseLock].Next = NULLPTR;
ControlBlock->LockQueue[IoCompletionLock].Lock = &IoCompletionLockQueue;
ControlBlock->LockQueue[IoCompletionLock].Next = NULLPTR;
ControlBlock->LockQueue[FileSystemLock].Lock = &FileSystemLockQueue;
ControlBlock->LockQueue[FileSystemLock].Next = NULLPTR;
ControlBlock->LockQueue[AfdWorkQueueLock].Lock = NULLPTR;
ControlBlock->LockQueue[AfdWorkQueueLock].Next = NULLPTR;
ControlBlock->LockQueue[BcbLock].Lock = NULLPTR;
ControlBlock->LockQueue[BcbLock].Next = NULLPTR;
ControlBlock->LockQueue[NonPagedPoolLock].Lock = &NonPagedPoolLockQueue;
ControlBlock->LockQueue[NonPagedPoolLock].Next = NULLPTR;
ControlBlock->LockQueue[ReservedSystemLock].Lock = NULLPTR;
ControlBlock->LockQueue[ReservedSystemLock].Next = NULLPTR;
ControlBlock->LockQueue[TimerTableLock].Lock = &TimerTableLockQueue;
ControlBlock->LockQueue[TimerTableLock].Next = NULLPTR;
}
/**
* Initializes a kernel spinlock object.
*
@@ -185,29 +112,3 @@ KE::SpinLock::ReleaseSpinLock(IN OUT PKSPIN_LOCK SpinLock)
/* Add an explicit memory barrier */
AR::CpuFunc::ReadWriteBarrier();
}
/**
* Tests a kernel spin lock.
*
* @param SpinLock
* Supplies a pointer to the kernel spin lock.
*
* @return This routine returns TRUE if the lock is free, FALSE otherwise.
*
* @since XT 1.0
*/
XTFASTCALL
BOOLEAN
TestSpinLock(IN PKSPIN_LOCK SpinLock)
{
/* Check if the lock is free */
if(*SpinLock)
{
/* Spinlock is busy, yield processor and return FALSE */
AR::CpuFunc::YieldProcessor();
return FALSE;
}
/* Spinlock is free, return TRUE */
return TRUE;
}

25
xtoskrnl/mm/amd64/init.cc Normal file
View File

@@ -0,0 +1,25 @@
/**
* PROJECT: ExectOS
* COPYRIGHT: See COPYING.md in the top level directory
* FILE: xtoskrnl/mm/amd64/init.cc
* DESCRIPTION: Architecture specific Memory Manager initialization routines
* DEVELOPERS: Rafal Kupiec <belliash@codingworkshop.eu.org>
* Aiken Harris <harraiken91@gmail.com>
*/
#include <xtos.hh>
/**
* Performs architecture specific initialization of the XTOS Memory Manager.
*
* @return This routine does not return any value.
*
* @since XT 1.0
*/
XTAPI
VOID
MM::Init::InitializeArchitecture(VOID)
{
UNIMPLEMENTED;
}

77
xtoskrnl/mm/amd64/mmgr.cc
View File

@@ -1,77 +0,0 @@
/**
* PROJECT: ExectOS
* COPYRIGHT: See COPYING.md in the top level directory
* FILE: xtoskrnl/mm/amd64/mmgr.cc
* DESCRIPTION: Memory Manager
* DEVELOPERS: Aiken Harris <harraiken91@gmail.com>
*/
#include <xtos.hh>
/**
* Initializes the kernel's virtual memory layout.
*
* @return This routine does not return any value.
*
* @since XT 1.0
*/
XTAPI
VOID
MM::Manager::InitializeMemoryLayout(VOID)
{
ULONG_PTR PagedPoolSize, PteCount;
PFN_NUMBER PfnDatabaseSize;
ULONG PtesPerPage;
/* Get the number of PTEs per page and calculate size of paged pool (at least 32MiB) */
PtesPerPage = MM::Pte::GetPtesPerPage();
PteCount = ((SIZE_TO_PAGES(33554432) + (PtesPerPage - 1)) / PtesPerPage);
PagedPoolSize = PteCount * PtesPerPage * MM_PAGE_SIZE;
/* Retrieve the PFN database size */
PfnDatabaseSize = MM::Pfn::GetPfnDatabaseSize();
/* Define the number of system PTEs */
NumberOfSystemPtes = MM_DEFAULT_NUMBER_SYSTEM_PTES;
/* Check if 5-level paging (LA57) is enabled */
if(MM::Paging::GetXpaStatus())
{
/* Configure memory layout for 5-level paging, using 57bit address space and providing a 128 PB address space */
MemoryLayout.PfnDatabaseAddress = (PMMPFN)0xFFFEFA8000000000ULL;
MemoryLayout.SelfMapAddress = (PVOID)MM_P5E_LA57_BASE;
/* Define the non-paged and paged pool regions */
MemoryLayout.NonPagedPoolStart = (PVOID)((ULONG_PTR)MemoryLayout.PfnDatabaseAddress + PfnDatabaseSize * MM_PAGE_SIZE);
MemoryLayout.NonPagedPoolEnd = (PVOID)0xFFFEFFFFFFBFFFFFULL;
MemoryLayout.PagedPoolStart = (PVOID)0xFFFEF8A000000000ULL;
MemoryLayout.PagedPoolEnd = (PVOID)(((ULONG_PTR)MemoryLayout.PagedPoolStart + PagedPoolSize) - 1);
/* Define hyperspace, system PTE space, and the user space limit */
MemoryLayout.HyperSpaceStart = (PVOID)0xFFFEF70000000000ULL;
MemoryLayout.HyperSpaceEnd = (PVOID)0xFFFEF77FFFFFFFFFULL;
MemoryLayout.SystemSpaceStart = (PVOID)0xFFFEF88000000000ULL;
MemoryLayout.SystemSpaceEnd = (PVOID)((ULONG_PTR)MemoryLayout.SystemSpaceStart + (NumberOfSystemPtes + 1) * MM_PAGE_SIZE);
MemoryLayout.UserSpaceEnd = (PVOID)0x07FFFFFFFFFFFFFULL;
}
else
{
/* Configure memory layout for 4-level paging, using 48bit address space and providing a 128 TB address space */
MemoryLayout.PfnDatabaseAddress = (PMMPFN)0xFFFFFA8000000000ULL;
MemoryLayout.SelfMapAddress = (PVOID)MM_PXE_BASE;
/* Define the non-paged and paged pool regions */
MemoryLayout.NonPagedPoolStart = (PVOID)((ULONG_PTR)MemoryLayout.PfnDatabaseAddress + PfnDatabaseSize * MM_PAGE_SIZE);
MemoryLayout.NonPagedPoolEnd = (PVOID)0xFFFFFFFFFFBFFFFFULL;
MemoryLayout.PagedPoolStart = (PVOID)0xFFFFF8A000000000ULL;
MemoryLayout.PagedPoolEnd = (PVOID)(((ULONG_PTR)MemoryLayout.PagedPoolStart + PagedPoolSize) - 1);
/* Define hyperspace, system PTE space, and the user space limit */
MemoryLayout.HyperSpaceStart = (PVOID)0xFFFFF70000000000ULL;
MemoryLayout.HyperSpaceEnd = (PVOID)0xFFFFF77FFFFFFFFFULL;
MemoryLayout.SystemSpaceStart = (PVOID)0xFFFFF88000000000ULL;
MemoryLayout.SystemSpaceEnd = (PVOID)((ULONG_PTR)MemoryLayout.SystemSpaceStart + (NumberOfSystemPtes + 1) * MM_PAGE_SIZE);
MemoryLayout.UserSpaceEnd = (PVOID)0x000007FFFFFEFFFFULL;
}
}

642
xtoskrnl/mm/amd64/pagemap.cc
View File

@@ -9,28 +9,6 @@
#include <xtos.hh>
/**
* Advances a PTE pointer by a given number of entries, considering the actual PTE size.
*
* @param Pte
* The PTE pointer to advance.
*
* @param Count
* The number of PTE entries to advance by.
*
* @return The advanced PTE pointer.
*
* @since XT 1.0
*/
XTAPI
PMMPTE
MM::PageMap::AdvancePte(IN PMMPTE Pte,
IN LONG Count)
{
/* Return advanced PTE pointer */
return (PMMPTE)((ULONG_PTR)Pte + (Count * sizeof(MMPTE)));
}
/**
* Clears the contents of a page table entry (PTE).
*
@@ -43,64 +21,13 @@ MM::PageMap::AdvancePte(IN PMMPTE Pte,
*/
XTAPI
VOID
MM::PageMap::ClearPte(IN PMMPTE PtePointer)
MM::PageMap::ClearPte(PHARDWARE_PTE PtePointer)
{
/* Clear PTE */
PtePointer->Long = 0;
}
/**
* Gets the next entry in a PTE list.
*
* @param Pte
* The PTE pointer to get the next entry from.
*
* @return This routine returns the next entry in the PTE list.
*
* @since XT 1.0
*/
XTAPI
ULONG_PTR
MM::PageMap::GetNextEntry(IN PMMPTE Pte)
{
/* Return next entry in PTE list */
return Pte->List.NextEntry;
}
/**
* Advances a PTE pointer, considering the actual PTE size.
*
* @param Pte
* The PTE pointer to advance.
*
* @return The advanced PTE pointer.
*
* @since XT 1.0
*/
XTAPI
PMMPTE
MM::PageMap::GetNextPte(IN PMMPTE Pte)
{
/* Return advanced PTE pointer */
return AdvancePte(Pte, 1);
}
/**
* Checks if a PTE list contains only one entry.
*
* @param Pte
* The PTE pointer to check.
*
* @return This routine returns TRUE if the PTE list has only one entry, FALSE otherwise.
*
* @since XT 1.0
*/
XTAPI
BOOLEAN
MM::PageMap::GetOneEntry(IN PMMPTE Pte)
{
/* Return one entry status */
return Pte->List.OneEntry;
PtePointer->CacheDisable = 0;
PtePointer->PageFrameNumber = 0;
PtePointer->Valid = 0;
PtePointer->Writable = 0;
PtePointer->WriteThrough = 0;
}
/**
@@ -115,7 +42,7 @@ MM::PageMap::GetOneEntry(IN PMMPTE Pte)
*/
XTAPI
PMMP5E
MM::PageMap::GetP5eAddress(IN PVOID Address)
MM::PageMap::GetP5eAddress(PVOID Address)
{
ULONGLONG Offset;
@@ -124,58 +51,6 @@ MM::PageMap::GetP5eAddress(IN PVOID Address)
return (PMMP5E)((PageMapInfo.P5eBase + Offset) * PageMapInfo.Xpa);
}
/**
* Gets the Offset of the P5E (Page Map Level 5 Entry), that maps given address.
*
* @param Address
* Specifies the virtual address for which to retrieve the corresponding P5E.
*
* @return This routine returns the Offset of the P5E, or NULLPTR if LA57 is not enabled.
*
* @since XT 1.0
*/
XTAPI
ULONG
MM::PageMap::GetP5eOffset(IN PVOID Address)
{
/* Return P5E Offset */
return (((((ULONGLONG)Address) >> MM_P5I_SHIFT) & 0x1FF) * PageMapInfo.Xpa);
}
/**
* Gets the virtual address that is mapped by a given Page Map Level 5 Entry.
*
* @param P5ePointer
* Specifies the address of the P5E.
*
* @return This routine returns the virtual address mapped by the P5E, or NULLPTR if LA57 is not enabled.
*
* @since XT 1.0
*/
XTAPI
PVOID
MM::PageMap::GetP5eVirtualAddress(IN PMMP5E P5ePointer)
{
return (PVOID)((((LONGLONG)P5ePointer << 52) >> 7) * PageMapInfo.Xpa);
}
/**
* Gets the page frame number from a corresponding PTE.
*
* @param Pte
* The PTE pointer to get the page frame number from.
*
* @return This routine returns the page frame number.
*
* @since XT 1.0
*/
XTAPI
PFN_NUMBER
MM::PageMap::GetPageFrameNumber(IN PMMPTE Pte)
{
return Pte->Hardware.PageFrameNumber;
}
/**
* Gets the address of the PDE (Page Directory Entry), that maps given address.
*
@@ -188,7 +63,7 @@ MM::PageMap::GetPageFrameNumber(IN PMMPTE Pte)
*/
XTAPI
PMMPDE
MM::PageMap::GetPdeAddress(IN PVOID Address)
MM::PageMap::GetPdeAddress(PVOID Address)
{
ULONGLONG Offset;
@@ -197,29 +72,11 @@ MM::PageMap::GetPdeAddress(IN PVOID Address)
return (PMMPDE)(PageMapInfo.PdeBase + Offset);
}
/**
* Gets the Offset of the PDE (Page Directory Entry), that maps given address.
*
* @param Address
* Specifies the virtual address for which to retrieve the corresponding PDE.
*
* @return This routine returns the Offset of the PDE.
*
* @since XT 1.0
*/
XTAPI
ULONG
MM::PageMap::GetPdeOffset(IN PVOID Address)
{
/* Return PDE Offset */
return ((((ULONGLONG)Address) >> MM_PDI_SHIFT) & 0x1FF);
}
/**
* Gets the address of the PPE (Page Directory Pointer Table Entry), that maps given address.
*
* @param Address
* Specifies the virtual address for which to retrieve the corresponding PPE.
* Specifies the virtual address for which to retrieve the corresponding PDE.
*
* @return This routine returns the address of the PPE.
*
@@ -227,7 +84,7 @@ MM::PageMap::GetPdeOffset(IN PVOID Address)
*/
XTAPI
PMMPPE
MM::PageMap::GetPpeAddress(IN PVOID Address)
MM::PageMap::GetPpeAddress(PVOID Address)
{
ULONGLONG Offset;
@@ -236,42 +93,6 @@ MM::PageMap::GetPpeAddress(IN PVOID Address)
return (PMMPPE)(PageMapInfo.PpeBase + Offset);
}
/**
* Gets the Offset of the PPE (Page Directory Pointer Table Entry), that maps given address.
*
* @param Address
* Specifies the virtual address for which to retrieve the corresponding PPE.
*
* @return This routine returns the Offset of the PPE.
*
* @since XT 1.0
*/
XTAPI
ULONG
MM::PageMap::GetPpeOffset(IN PVOID Address)
{
/* Return PPE Offset */
return ((((ULONGLONG)Address) >> MM_PPI_SHIFT) & 0x1FF);
}
/**
* Gets the entire contents of a Page Table Entry (PTE) as a single value.
*
* @param PtePointer
* Pointer to the Page Table Entry (PTE) to read.
*
* @return This routine returns the contents of the PTE as a single value.
*
* @since XT 1.0
*/
XTAPI
ULONG_PTR
MM::PageMap::GetPte(IN PMMPTE PtePointer)
{
/* Return PTE value */
return PtePointer->Long;
}
/**
* Gets the address of the PTE (Page Table Entry), that maps given address.
*
@@ -284,7 +105,7 @@ MM::PageMap::GetPte(IN PMMPTE PtePointer)
*/
XTAPI
PMMPTE
MM::PageMap::GetPteAddress(IN PVOID Address)
MM::PageMap::GetPteAddress(PVOID Address)
{
ULONGLONG Offset;
@@ -293,115 +114,6 @@ MM::PageMap::GetPteAddress(IN PVOID Address)
return (PMMPTE)(PageMapInfo.PteBase + Offset);
}
/**
* Calculates the distance between two PTE pointers.
*
* @param EndPte
* Pointer to the ending Page Table Entry.
*
* @param StartPte
* Pointer to the starting Page Table Entry.
*
* @return This routine returns a signed value representing the number of PTEs between EndPte and StartPte.
*
* @since XT 1.0
*/
XTAPI
LONG
MM::PageMap::GetPteDistance(PMMPTE EndPte,
PMMPTE StartPte)
{
/* Return distance between PTE pointers */
return ((ULONG_PTR)EndPte - (ULONG_PTR)StartPte) / sizeof(MMPTE);
}
/**
* Gets the Offset of the PTE (Page Table Entry), that maps given address.
*
* @param Address
* Specifies the virtual address for which to retrieve the corresponding PTE.
*
* @return This routine returns the Offset of the PTE.
*
* @since XT 1.0
*/
XTAPI
ULONG
MM::PageMap::GetPteOffset(IN PVOID Address)
{
/* Return PTE Offset */
return ((((ULONGLONG)Address) >> MM_PTI_SHIFT) & 0x1FF);
}
/**
* Gets the size of a PTE.
*
* @return This routine returns the size of a PTE.
*
* @since XT 1.0
*/
XTAPI
ULONG
MM::PageMap::GetPteSize(VOID)
{
/* Return the size of MMPTE */
return sizeof(MMPTE);
}
/**
* Gets the software protection value of the corresponding Page Table Entry.
*
* @param PtePointer
* Specifies the address of the PTE.
*
* @return This routine returns the PTE software protection value.
*
* @since XT 1.0
*/
XTAPI
ULONG
MM::PageMap::GetPteSoftwareProtection(IN PMMPTE PtePointer)
{
/* Return PTE software protection value */
return (ULONG)PtePointer->Software.Protection;
}
/**
* Gets the software prototype value of the corresponding Page Table Entry.
*
* @param PtePointer
* Specifies the address of the PTE.
*
* @return This routine returns the PTE software prototype value.
*
* @since XT 1.0
*/
XTAPI
ULONG
MM::PageMap::GetPteSoftwarePrototype(IN PMMPTE PtePointer)
{
/* Return PTE software prototype value */
return (ULONG)PtePointer->Software.Prototype;
}
/**
* Gets the software transition value of the corresponding Page Table Entry.
*
* @param PtePointer
* Specifies the address of the PTE.
*
* @return This routine returns the PTE software transition value.
*
* @since XT 1.0
*/
XTAPI
ULONG
MM::PageMap::GetPteSoftwareTransition(IN PMMPTE PtePointer)
{
/* Return PTE software transition value */
return (ULONG)PtePointer->Software.Transition;
}
/**
* Gets the address of the PXE (Extended Page Entry), that maps given address.
*
@@ -414,47 +126,14 @@ MM::PageMap::GetPteSoftwareTransition(IN PMMPTE PtePointer)
*/
XTAPI
PMMPXE
MM::PageMap::GetPxeAddress(IN PVOID Address)
MM::PageMap::GetPxeAddress(PVOID Address)
{
ULONGLONG Offset;
/* Calculate offset and return PXE address */
Offset = ((((ULONGLONG)Address & (((ULONGLONG)1 << PageMapInfo.VaBits) - 1)) >> MM_PXI_SHIFT) << MM_PTE_SHIFT);
return (PMMPXE)(PageMapInfo.PxeBase + Offset);
}
/**
* Gets the Offset of the PXE (Extended Page Entry), that maps given address.
*
* @param Address
* Specifies the virtual address for which to retrieve the corresponding PXE.
*
* @return This routine returns the Offset of the PXE.
*
* @since XT 1.0
*/
XTAPI
ULONG
MM::PageMap::GetPxeOffset(IN PVOID Address)
{
/* Return PXE Offset */
return ((((ULONGLONG)Address) >> MM_PXI_SHIFT) & 0x1FF);
}
/**
* Gets the status of Extended Paging Address (XPA) mode.
*
* @return This routine returns TRUE if XPA is enabled, FALSE otherwise.
*
* @since XT 1.0
*/
XTAPI
BOOLEAN
MM::PageMap::GetXpaStatus()
{
return PageMapInfo.Xpa;
}
/**
* Checks whether the given PML2 page table entry (PTE) is valid.
*
@@ -467,58 +146,13 @@ MM::PageMap::GetXpaStatus()
*/
XTAPI
BOOLEAN
MM::PageMap::PteValid(IN PMMPTE PtePointer)
MM::PageMap::PteValid(PHARDWARE_PTE PtePointer)
{
/* Check if PTE is valid */
return (BOOLEAN)PtePointer->Hardware.Valid;
return (BOOLEAN)PtePointer->Valid;
}
/**
* Sets the next entry in a PTE list.
*
* @param Pte
* The PTE pointer to modify.
*
* @param Value
* The value to set as the next entry.
*
* @return This routine does not return any value.
*
* @since XT 1.0
*/
XTAPI
VOID
MM::PageMap::SetNextEntry(IN PMMPTE Pte,
IN ULONG_PTR Value)
{
/* Set next entry in PTE list */
Pte->List.NextEntry = Value;
}
/**
* Sets the flag indicating whether a PTE list contains only one entry.
*
* @param Pte
* The PTE pointer to modify.
*
* @param Value
* The value to set. TRUE if the list has only one entry, FALSE otherwise.
*
* @return This routine does not return any value.
*
* @since XT 1.0
*/
XTAPI
VOID
MM::PageMap::SetOneEntry(IN PMMPTE Pte,
IN BOOLEAN Value)
{
/* Set one entry status */
Pte->List.OneEntry = Value;
}
/**
* Sets a Page Table Entry (PTE) with the specified physical page and access flags.
* Sets a PML2 page table entry (PTE) with the specified physical page and access flags.
*
* @param PtePointer
* Pointer to the page table entry (PTE) to set.
@@ -526,8 +160,8 @@ MM::PageMap::SetOneEntry(IN PMMPTE Pte,
* @param PageFrameNumber
* Physical frame number to map.
*
* @param AttributesMask
* Specifies the attributes mask to apply to the PTE.
* @param Writable
* Indicates whether the page should be writable.
*
* @return This routine does not return any value.
*
@@ -535,35 +169,13 @@ MM::PageMap::SetOneEntry(IN PMMPTE Pte,
*/
XTAPI
VOID
MM::PageMap::SetPte(IN PMMPTE PtePointer,
IN PFN_NUMBER PageFrameNumber,
IN ULONG_PTR AttributesMask)
MM::PageMap::SetPte(PHARDWARE_PTE PtePointer,
PFN_NUMBER PageFrameNumber,
BOOLEAN Writable)
{
/* Set PTE */
PtePointer->Hardware.PageFrameNumber = PageFrameNumber;
PtePointer->Hardware.Valid = 1;
PtePointer->Long |= AttributesMask;
}
/**
* Sets a Page Table Entry (PTE) with the specified attributes.
*
* @param PtePointer
* Pointer to the page table entry (PTE) to set.
*
* @param Attributes
* Specifies the attributes to apply to the PTE.
*
* @return This routine does not return any value.
*
* @since XT 1.0
*/
XTAPI
VOID
MM::PageMap::SetPte(IN PMMPTE PtePointer,
IN ULONG_PTR Attributes)
{
PtePointer->Long = Attributes;
PtePointer->PageFrameNumber = PageFrameNumber;
PtePointer->Valid = 1;
PtePointer->Writable = Writable;
}
/**
@@ -584,138 +196,12 @@ MM::PageMap::SetPte(IN PMMPTE PtePointer,
*/
XTAPI
VOID
MM::PageMap::SetPteCaching(IN PMMPTE PtePointer,
IN BOOLEAN CacheDisable,
IN BOOLEAN WriteThrough)
MM::PageMap::SetPteCaching(PHARDWARE_PTE PtePointer,
BOOLEAN CacheDisable,
BOOLEAN WriteThrough)
{
/* Set caching attributes */
PtePointer->Hardware.CacheDisable = CacheDisable;
PtePointer->Hardware.WriteThrough = WriteThrough;
}
/**
* Transitions a Page Table Entry (PTE) to invalid state
*
* @param PointerPte
* Pointer to the page table entry (PTE) to transition.
*
* @param Protection
* Specifies the protection attribute to apply to the PTE.
*
* @return This routine does not return any value.
*
* @since XT 1.0
*/
XTAPI
VOID
MM::PageMap::TransitionPte(IN PMMPTE PointerPte,
IN ULONG_PTR Protection)
{
MMPTE TempPte;
/* Set transition PTE */
TempPte = *PointerPte;
TempPte.Software.Protection = Protection;
TempPte.Software.Prototype = 0;
TempPte.Software.Transition = 1;
TempPte.Software.Valid = 0;
/* Write PTE value */
*PointerPte = TempPte;
}
/**
* Writes a Page Table Entry (PTE) with the specified value.
*
* @param Pte
* Pointer to the page table entry (PTE) to write.
*
* @param Value
* The value to write to the PTE.
*
* @return This routine does not return any value.
*
* @since XT 1.0
*/
XTAPI
VOID
MM::PageMap::WritePte(IN PMMPTE Pte,
IN MMPTE Value)
{
/* Write PTE value */
Pte->Long = Value.Long;
}
/**
* Gets the virtual address that is mapped by a given Page Directory Entry (PML4).
*
* @param PdePointer
* Specifies the address of the PDE.
*
* @return This routine returns the virtual address mapped by the PDE.
*
* @since XT 1.0
*/
XTAPI
PVOID
MM::PageMapBasic::GetPdeVirtualAddress(IN PMMPDE PdePointer)
{
/* Return PDE virtual address */
return (PVOID)(((LONGLONG)PdePointer << 34) >> 16);
}
/**
* Gets the virtual address that is mapped by a given Page Directory Pointer Table Entry (PML4).
*
* @param PpePointer
* Specifies the address of the PPE.
*
* @return This routine returns the virtual address mapped by the PPE.
*
* @since XT 1.0
*/
XTAPI
PVOID
MM::PageMapBasic::GetPpeVirtualAddress(IN PMMPPE PpePointer)
{
/* Return PPE virtual address */
return (PVOID)(((LONGLONG)PpePointer << 43) >> 16);
}
/**
* Gets the virtual address that is mapped by a given Page Table Entry (PML4).
*
* @param PtePointer
* Specifies the address of the PTE.
*
* @return This routine returns the virtual address mapped by the PTE.
*
* @since XT 1.0
*/
XTAPI
PVOID
MM::PageMapBasic::GetPteVirtualAddress(IN PMMPTE PtePointer)
{
/* Return PTE virtual address */
return (PVOID)(((LONGLONG)PtePointer << 25) >> 16);
}
/**
* Gets the virtual address that is mapped by a given Extended Page Entry (PML4).
*
* @param PxePointer
* Specifies the address of the PXE.
*
* @return This routine returns the virtual address mapped by the PXE.
*
* @since XT 1.0
*/
XTAPI
PVOID
MM::PageMapBasic::GetPxeVirtualAddress(IN PMMPXE PxePointer)
{
/* Return PXE virtual address */
return (PVOID)(((LONGLONG)PxePointer << 52) >> 16);
PtePointer->CacheDisable = CacheDisable;
PtePointer->WriteThrough = WriteThrough;
}
/**
@@ -743,78 +229,6 @@ MM::PageMapBasic::InitializePageMapInfo(VOID)
PageMapInfo.VaBits = 48;
}
/**
* Gets the virtual address that is mapped by a given Page Directory Entry (PML5).
*
* @param PdePointer
* Specifies the address of the PDE.
*
* @return This routine returns the virtual address mapped by the PDE.
*
* @since XT 1.0
*/
XTAPI
PVOID
MM::PageMapXpa::GetPdeVirtualAddress(IN PMMPDE PdePointer)
{
/* Return PDE virtual address */
return (PVOID)(((LONGLONG)PdePointer << 25) >> 7);
}
/**
* Gets the virtual address that is mapped by a given Page Directory Pointer Table Entry (PML5).
*
* @param PpePointer
* Specifies the address of the PPE.
*
* @return This routine returns the virtual address mapped by the PPE.
*
* @since XT 1.0
*/
XTAPI
PVOID
MM::PageMapXpa::GetPpeVirtualAddress(IN PMMPPE PpePointer)
{
/* Return PPE virtual address */
return (PVOID)(((LONGLONG)PpePointer << 34) >> 7);
}
/**
* Gets the virtual address that is mapped by a given Page Table Entry (PML5).
*
* @param PtePointer
* Specifies the address of the PTE.
*
* @return This routine returns the virtual address mapped by the PTE.
*
* @since XT 1.0
*/
XTAPI
PVOID
MM::PageMapXpa::GetPteVirtualAddress(IN PMMPTE PtePointer)
{
/* Return PTE virtual address */
return (PVOID)(((LONGLONG)PtePointer << 16) >> 7);
}
/**
* Gets the virtual address that is mapped by a given Extended Page Entry (PML5).
*
* @param PxePointer
* Specifies the address of the PXE.
*
* @return This routine returns the virtual address mapped by the PXE.
*
* @since XT 1.0
*/
XTAPI
PVOID
MM::PageMapXpa::GetPxeVirtualAddress(IN PMMPXE PxePointer)
{
/* Return PXE virtual address */
return (PVOID)(((LONGLONG)PxePointer << 43) >> 7);
}
/**
* Initializes page map information for XPA paging (PML5).
*

72
xtoskrnl/mm/amd64/paging.cc
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@@ -25,78 +25,6 @@ MM::Paging::GetExtendedPhysicalAddressingStatus(VOID)
return ((AR::CpuFunc::ReadControlRegister(4) & CR4_LA57) != 0) ? TRUE : FALSE;
}
/**
* Gets the address of the P5E (Page Map Level 5 Entry), that maps given address.
*
* @param Address
* Specifies the virtual address for which to retrieve the corresponding P5E.
*
* @return This routine returns the address of the P5E, or NULLPTR if LA57 is not enabled.
*
* @since XT 1.0
*/
XTAPI
PMMP5E
MM::Paging::GetP5eAddress(IN PVOID Address)
{
/* Return PDE address */
return PmlRoutines->GetP5eAddress(Address);
}
/**
* Gets the virtual address that is mapped by a given Page Map Level 5 Entry.
*
* @param P5ePointer
* Specifies the address of the P5E.
*
* @return This routine returns the virtual address mapped by the P5E, or NULLPTR if LA57 is not enabled.
*
* @since XT 1.0
*/
XTAPI
PVOID
MM::Paging::GetP5eVirtualAddress(IN PMMP5E P5ePointer)
{
/* Return PTE virtual address */
return PmlRoutines->GetP5eVirtualAddress(P5ePointer);
}
/**
* Gets the address of the PXE (Extended Page Entry), that maps given address.
*
* @param Address
* Specifies the virtual address for which to retrieve the corresponding PXE.
*
* @return This routine returns the address of the PXE.
*
* @since XT 1.0
*/
XTAPI
PMMPXE
MM::Paging::GetPxeAddress(IN PVOID Address)
{
/* Return PXE address */
return PmlRoutines->GetPxeAddress(Address);
}
/**
* Gets the virtual address that is mapped by a given Extended Page Entry.
*
* @param PxePointer
* Specifies the address of the PXE.
*
* @return This routine returns the virtual address mapped by the PXE.
*
* @since XT 1.0
*/
XTAPI
PVOID
MM::Paging::GetPxeVirtualAddress(IN PMMPXE PxePointer)
{
/* Return PXE virtual address */
return PmlRoutines->GetPxeVirtualAddress(PxePointer);
}
/**
* Fills a section of memory with zeroes like RtlZeroMemory(), but in more efficient way.
*

26
xtoskrnl/mm/amd64/pfault.cc
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@@ -1,26 +0,0 @@
/**
* PROJECT: ExectOS
* COPYRIGHT: See COPYING.md in the top level directory
* FILE: xtoskrnl/mm/amd64/pfault.cc
* DESCRIPTION: Page fault support for AMD64 architecture
* DEVELOPERS: Aiken Harris <harraiken91@gmail.com>
*/
#include <xtos.hh>
/**
* Evaluates the PDE for for paged pool and per-session mappings.
*
* @param VirtualAddress
* Specifies the virtual address to verify.
*
* @return This routine returns ACCESS_VIOLATION regardless PML4 or PML5 is used.
*/
XTFASTCALL
XTSTATUS
MM::PageFault::CheckPdeForPagedPool(IN PVOID VirtualAddress)
{
/* Return access violation */
return STATUS_ACCESS_VIOLATION;
}

357
xtoskrnl/mm/amd64/pfn.cc
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@@ -1,357 +0,0 @@
/**
* PROJECT: ExectOS
* COPYRIGHT: See COPYING.md in the top level directory
* FILE: xtoskrnl/mm/amd64/pfn.cc
* DESCRIPTION: Physical Frame Number for AMD64 support
* DEVELOPERS: Aiken Harris <harraiken91@gmail.com>
* Rafal Kupiec <belliash@codingworkshop.eu.org>
*/
#include <xtos.hh>
/**
* Initializes the PFN database by mapping virtual memory and populating entries.
*
* @return This routine does not return any value.
*
* @since XT 1.0
*/
XTAPI
VOID
MM::Pfn::InitializePfnDatabase(VOID)
{
PKERNEL_INITIALIZATION_BLOCK InitializationBlock;
PLIST_ENTRY ListEntry;
PLOADER_MEMORY_DESCRIPTOR Descriptor;
PFN_NUMBER BasePage, PageCount;
PUCHAR PfnDatabaseEnd;
PMMMEMORY_LAYOUT MemoryLayout;
PMMPTE ValidPte;
/* Raise runlevel and acquire the PFN lock */
KE::RaiseRunLevel RunLevel(DISPATCH_LEVEL);
KE::QueuedSpinLockGuard SpinLock(SystemSpaceLock);
/* Get the kernel initialization block */
InitializationBlock = KE::BootInformation::GetInitializationBlock();
/* Get the memory layout */
MemoryLayout = MM::Manager::GetMemoryLayout();
/* Get the PFN database size and calculate the end of the PFN database virtual address space */
PfnDatabaseEnd = (PUCHAR)MemoryLayout->PfnDatabaseAddress + (PfnDatabaseSize * MM_PAGE_SIZE) - 1;
/* Get a template PTE for mapping the PFN database pages */
ValidPte = MM::Pte::GetValidPte();
/* Map the Page Directory and Page Directory Pointer tables for the PFN database */
MM::Pte::MapPPE(MemoryLayout->PfnDatabaseAddress, PfnDatabaseEnd, ValidPte);
MM::Pte::MapPDE(MemoryLayout->PfnDatabaseAddress, PfnDatabaseEnd, ValidPte);
/* Initialize the color tables */
MM::Colors::InitializeColorTables();
/* Iterate over memory descriptors to map the PFN database and initialize entries */
ListEntry = InitializationBlock->MemoryDescriptorListHead.Flink;
while(ListEntry != &InitializationBlock->MemoryDescriptorListHead)
{
/* Get the descriptor */
Descriptor = CONTAIN_RECORD(ListEntry, LOADER_MEMORY_DESCRIPTOR, ListEntry);
/* Skip invisible memory regions */
if(MM::Manager::VerifyMemoryTypeInvisible(Descriptor->MemoryType))
{
/* Move to the next descriptor and continue */
ListEntry = ListEntry->Flink;
continue;
}
/* Determine the physical page range to process */
if(Descriptor == FreeDescriptor)
{
BasePage = OriginalFreeDescriptor.BasePage;
PageCount = OriginalFreeDescriptor.PageCount;
}
else
{
BasePage = Descriptor->BasePage;
PageCount = Descriptor->PageCount;
}
/* Map PFN database entries for this physical range */
MM::Pte::MapPTE(&((PMMPFN)MemoryLayout->PfnDatabaseAddress)[BasePage],
(PUCHAR)&((PMMPFN)MemoryLayout->PfnDatabaseAddress)[BasePage + PageCount] - 1,
ValidPte);
/* Split PFN database allocation out of the free descriptor */
if(Descriptor == FreeDescriptor)
{
/* Initialize PFNs for the remaining free memory */
ProcessMemoryDescriptor(BasePage + PfnDatabaseSize, PageCount - PfnDatabaseSize, LoaderFree);
/* Initialize PFNs for the physical pages backing the PFN database */
ProcessMemoryDescriptor(BasePage, PfnDatabaseSize, LoaderMemoryData);
}
else
{
/* Initialize PFNs for this memory range */
ProcessMemoryDescriptor(BasePage, PageCount, Descriptor->MemoryType);
}
/* Move to the next descriptor */
ListEntry = ListEntry->Flink;
}
/* Restore original free descriptor */
*FreeDescriptor = OriginalFreeDescriptor;
/* Initialize PFNs backing page tables */
InitializePageTablePfns();
}
/**
* Initializes PFN database entries for the system page tables.
*
* @return This routine does not return any value.
*
* @since XT 1.0
*/
XTAPI
VOID
MM::Pfn::InitializePageTablePfns(VOID)
{
PFN_NUMBER PageFrameIndex;
PMMPFN Pfn;
ULONG RootLevel;
PMMPTE RootPte;
/* Determine root structure based on paging mode */
if(MM::Paging::GetXpaStatus())
{
/* XPA enabled, 5-level paging (LA57) */
RootLevel = 5;
/* Retrieve the PFN of the PML5 table and its virtual base address */
PageFrameIndex = MM::Paging::GetPageFrameNumber(MM::Paging::GetPteAddress((PVOID)MM_P5E_LA57_BASE));
RootPte = (PMMPTE)MM::Paging::GetP5eAddress(NULLPTR);
}
else
{
/* XPA disabled, 4-level paging */
RootLevel = 4;
/* Retrieve the PFN of the PML4 table and its virtual base address */
PageFrameIndex = MM::Paging::GetPageFrameNumber(MM::Paging::GetPteAddress((PVOID)MM_PXE_BASE));
RootPte = (PMMPTE)MM::Paging::GetPxeAddress(NULLPTR);
}
/* Initialize the PFN entry for the root page table itself */
Pfn = GetPfnEntry(PageFrameIndex);
if(Pfn)
{
/* Initialize the PFN entry */
Pfn->PteAddress = NULLPTR;
Pfn->u1.WsIndex = 0;
Pfn->u2.ShareCount = 1;
Pfn->u3.e1.CacheAttribute = PfnNonCached;
Pfn->u3.e2.ReferenceCount = 1;
Pfn->u4.PteFrame = 0;
}
/* Start recursive scan from the top level */
if(RootPte)
{
/* Scan the root page table */
ScanPageTable(RootPte, RootLevel);
}
}
/**
* Processes a memory descriptor and initializes the corresponding PFN database entries
*
* @param BasePage
* The starting physical page number of the memory run
*
* @param PageCount
* The number of pages in the memory run
*
* @param MemoryType
* The type of memory as reported by the bootloader (e.g., free, ROM, in-use)
*
* @return This routine does not return any value.
*
* @since XT 1.0
*/
XTAPI
VOID
MM::Pfn::ProcessMemoryDescriptor(IN PFN_NUMBER BasePage,
IN PFN_NUMBER PageCount,
IN LOADER_MEMORY_TYPE MemoryType)
{
PFN_NUMBER PageNumber;
PMMPDE PointerPde;
PMMPFN Pfn;
/* Check if the memory descriptor describes a free memory region */
if(MM::Manager::VerifyMemoryTypeFree(MemoryType))
{
/* Iterate over each page in this free memory run */
for(PageNumber = 0; PageNumber < PageCount; PageNumber++)
{
/* Get the PFN entry for the current page and ensure it is not referenced */
Pfn = GetPfnEntry(BasePage + PageNumber);
if(Pfn->u3.e2.ReferenceCount == 0)
{
/* Add the page to the free list to make it available for allocation */
LinkFreePage(BasePage + PageNumber);
}
}
}
else
{
/* Handle all other (non-free) memory types */
switch(MemoryType)
{
case LoaderBad:
/* This memory is marked as bad and should not be used */
for(PageNumber = 0; PageNumber < PageCount; PageNumber++)
{
/* Link the page to the bad pages list */
LinkPage(&BadPagesList, BasePage + PageNumber);
}
break;
case LoaderXIPRom:
/* This memory range contains Read-Only Memory (ROM) */
for(PageNumber = 0; PageNumber < PageCount; PageNumber++)
{
/* Get the PFN entry for the current ROM page */
Pfn = GetPfnEntry(BasePage + PageNumber);
/* Ensure that the page is not already in-use */
if(Pfn->u3.e2.ReferenceCount == 0)
{
/* Get the page directory entry for the current page */
PointerPde = MM::Paging::GetPdeAddress((PVOID)(KSEG0_BASE + (BasePage << MM_PAGE_SHIFT)));
/* Initialize the PFN entry to represent a ROM page */
Pfn->PteAddress = MM::Paging::GetPteAddress((PVOID)(KSEG0_BASE + (BasePage << MM_PAGE_SHIFT)));
Pfn->u1.Flink = 0;
Pfn->u2.ShareCount = 0;
Pfn->u3.e1.CacheAttribute = PfnCached;
Pfn->u3.e1.PageLocation = 0;
Pfn->u3.e1.PrototypePte = 1;
Pfn->u3.e1.Rom = 1;
Pfn->u3.e2.ReferenceCount = 0;
Pfn->u4.InPageError = 0;
Pfn->u4.PteFrame = MM::Paging::GetPageFrameNumber(PointerPde);
}
}
break;
default:
/* All other types are considered in-use (ie, by the kernel, ACPI, etc) */
for(PageNumber = 0; PageNumber < PageCount; PageNumber++)
{
/* Get the PFN entry for the current in-use page */
Pfn = GetPfnEntry(BasePage + PageNumber);
/* Ensure that the page is not already in-use */
if(Pfn->u3.e2.ReferenceCount == 0)
{
/* Get the page directory entry for the current page */
PointerPde = MM::Paging::GetPdeAddress((PVOID)(KSEG0_BASE + (BasePage << MM_PAGE_SHIFT)));
/* Initialize the PFN entry to represent an in-use page and prevent it from being allocated */
Pfn->PteAddress = MM::Paging::GetPteAddress((PVOID)(KSEG0_BASE + (BasePage << MM_PAGE_SHIFT)));
Pfn->u2.ShareCount++;
Pfn->u3.e1.CacheAttribute = PfnCached;
Pfn->u3.e1.PageLocation = ActiveAndValid;
Pfn->u3.e2.ReferenceCount = 1;
Pfn->u4.PteFrame = MM::Paging::GetPageFrameNumber(PointerPde);
}
}
break;
}
}
}
/**
* Recursively scans a page table to initialize PFN database entries for active pages.
*
* @param PointerPte
* Pointer to the base of the page table to scan.
*
* @param Level
* The paging level of the table being scanned.
*
* @return This routine does not return any value.
*
* @since XT 1.0
*/
XTAPI
VOID
MM::Pfn::ScanPageTable(IN PMMPTE PointerPte,
IN ULONG Level)
{
PVOID Address;
ULONG Index;
PMMPTE NextLevelPte;
ULONG PtesPerPage;
/* Get the number of PTEs per page */
PtesPerPage = MM::Pte::GetPtesPerPage();
/* Iterate through all entries in the current page table */
for(Index = 0; Index < PtesPerPage; Index++)
{
/* Check if the page table entry is present */
if(MM::Paging::PteValid(PointerPte))
{
/* Mark the PFN pointed to by this entry as active */
LinkPfnForPageTable(MM::Paging::GetPageFrameNumber(PointerPte), PointerPte);
/* Recurse to the next level, if this is not a leaf node (PTE) */
if(Level > 1)
{
/* Calculate the virtual address mapped by this entry to find the next table */
switch(Level)
{
case 5:
/* Calculate PXE */
Address = MM::Paging::GetP5eVirtualAddress((PMMP5E)PointerPte);
NextLevelPte = (PMMPTE)MM::Paging::GetPxeAddress(Address);
break;
case 4:
/* Calculate PPE */
Address = MM::Paging::GetPxeVirtualAddress((PMMPXE)PointerPte);
NextLevelPte = (PMMPTE)MM::Paging::GetPpeAddress(Address);
break;
case 3:
/* Calculate PDE */
Address = MM::Paging::GetPpeVirtualAddress((PMMPPE)PointerPte);
NextLevelPte = (PMMPTE)MM::Paging::GetPdeAddress(Address);
break;
case 2:
/* Calculate PTE */
Address = MM::Paging::GetPdeVirtualAddress((PMMPDE)PointerPte);
NextLevelPte = MM::Paging::GetPteAddress(Address);
break;
default:
/* Nothing to calculate, return NULLPTR */
NextLevelPte = NULLPTR;
break;
}
/* Recurse deeper if not at the bottom level (PTE) already */
if(NextLevelPte)
{
/* Recursively scan the next level page table */
ScanPageTable(NextLevelPte, Level - 1);
}
}
}
/* Move to the next entry in the current table */
PointerPte = MM::Paging::GetNextPte(PointerPte);
}
}

295
xtoskrnl/mm/amd64/pte.cc
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@@ -1,295 +0,0 @@
/**
* PROJECT: ExectOS
* COPYRIGHT: See COPYING.md in the top level directory
* FILE: xtoskrnl/mm/amd64/pte.cc
* DESCRIPTION: Page Table Entry (PTE) for AMD64 support
* DEVELOPERS: Aiken Harris <harraiken91@gmail.com>
*/
#include <xtos.hh>
/**
* Checks if the virtual address is valid and mapped in the page tables.
*
* @param VirtualAddress
* The virtual address to check.
*
* @return This routine returns TRUE if the address is valid, or FALSE otherwise.
*
* @since XT 1.0
*/
XTAPI
BOOLEAN
MM::Pte::AddressValid(IN PVOID VirtualAddress)
{
/* Check XPA status */
if(MM::Paging::GetXpaStatus())
{
/* Check if the P5E is valid */
if(!MM::Paging::PteValid(MM::Paging::GetP5eAddress(VirtualAddress)))
{
/* Invalid P5E, return FALSE */
return FALSE;
}
}
/* Check if PXE, PPE, PDE and PTE are valid */
if(!MM::Paging::PteValid(MM::Paging::GetPxeAddress(VirtualAddress)) ||
!MM::Paging::PteValid(MM::Paging::GetPpeAddress(VirtualAddress)) ||
!MM::Paging::PteValid(MM::Paging::GetPdeAddress(VirtualAddress)) ||
!MM::Paging::PteValid(MM::Paging::GetPteAddress(VirtualAddress)))
{
/* Invalid PXE, PPE, PDE or PTE, return FALSE */
return FALSE;
}
/* Address is valid, return TRUE */
return TRUE;
}
/**
* Retrieves the base virtual address of the system PTEs.
*
* @return This routine returns a pointer to the first PTE in the system PTE space.
*
* @since XT 1.0
*/
XTAPI
PMMPTE
MM::Pte::GetSystemPteBaseAddress(VOID)
{
PMMMEMORY_LAYOUT MemoryLayout;
/* Retrieve the system's memory layout */
MemoryLayout = MM::Manager::GetMemoryLayout();
/* Determine the base address for system PTEs based on the paging mode */
if(MM::Paging::GetXpaStatus())
{
/* For 5-level paging, system PTEs start at the beginning of system space */
return MM::Paging::GetPteAddress((PVOID)MemoryLayout->SystemSpaceStart);
}
else
{
/* For 4-level paging, system PTEs start at the legacy KSEG0_BASE */
return MM::Paging::GetPteAddress((PVOID)KSEG0_BASE);
}
}
/**
* Performs the initial setup of the system's page table hierarchy.
*
* @return This routine does not return any value.
*
* @since XT 1.0
*/
XTAPI
VOID
MM::Pte::InitializePageTable(VOID)
{
PMMPTE EndSpacePte, PointerPte;
PMMMEMORY_LAYOUT MemoryLayout;
PVOID MappingRange;
MMPTE TemplatePte;
BOOLEAN Xpa;
/* Retrieve current paging mode and memory layout */
Xpa = MM::Paging::GetXpaStatus();
MemoryLayout = MM::Manager::GetMemoryLayout();
/* Enable the Global Paging (PGE) feature */
AR::CpuFunc::WriteControlRegister(4, AR::CpuFunc::ReadControlRegister(4) | CR4_PGE);
/* Check XPA status */
if(Xpa)
{
/* Get the PML5 user-space range if 5-level paging is active */
PointerPte = MM::Paging::GetP5eAddress(0);
EndSpacePte = MM::Paging::GetP5eAddress(MemoryLayout->UserSpaceEnd);
}
else
{
/* Otherwise, get the PML4 user-space range for 4-level paging */
PointerPte = MM::Paging::GetPxeAddress(0);
EndSpacePte = MM::Paging::GetPxeAddress(MemoryLayout->UserSpaceEnd);
}
/* Clear all top-level entries mapping the user address space */
while(PointerPte <= EndSpacePte)
{
MM::Paging::ClearPte(PointerPte);
PointerPte = MM::Paging::GetNextPte(PointerPte);
}
/* Flush the TLB to invalidate all non-global entries */
AR::CpuFunc::FlushTlb();
/* Create a template PTE for mapping kernel pages */
MM::Paging::ClearPte(&TemplatePte);
MM::Paging::SetPte(&TemplatePte, 0, MM_PTE_READWRITE | MM_PTE_CACHE_ENABLE);
/* Check XPA status */
if(Xpa)
{
/* Map the kernel's PML5 entries if 5-level paging is active */
MM::Pte::MapP5E(MemoryLayout->HyperSpaceStart, (PVOID)MM_HIGHEST_SYSTEM_ADDRESS, &TemplatePte);
}
/* Map the kernel's PML4 entries */
MM::Pte::MapPXE(MemoryLayout->HyperSpaceStart, (PVOID)MM_HIGHEST_SYSTEM_ADDRESS, &TemplatePte);
/* Calculate the end address of the hyperspace working set mapping */
MappingRange = (PVOID)((ULONG_PTR)MemoryLayout->HyperSpaceStart + MM_HYPERSPACE_PAGE_COUNT * MM_PAGE_SIZE);
/* Map the PDPT entries for paged pool and hyperspace */
MM::Pte::MapPPE(MemoryLayout->PagedPoolStart, MemoryLayout->PagedPoolEnd, &ValidPte);
MM::Pte::MapPPE(MemoryLayout->HyperSpaceStart, MemoryLayout->HyperSpaceEnd, &ValidPte);
/* Map the PDEs for the hyperspace working set */
MM::Pte::MapPDE(MemoryLayout->HyperSpaceStart, MappingRange, &ValidPte);
/* Set the hyperspace working set's PTE with the total PTE count */
MM::Paging::SetPte(MM::Paging::GetPteAddress((PVOID)MemoryLayout->HyperSpaceStart), MM_HYPERSPACE_PAGE_COUNT, 0);
}
/**
* Maps a range of virtual addresses at the P5E (PML5) level.
*
* @param StartAddress
* The beginning of the virtual address range to map.
*
* @param EndAddress
* The end of the virtual address range to map.
*
* @param TemplateP5e
* A template P5E to use for creating new entries.
*
* @return This routine does not return any value.
*
* @since XT 1.0
*/
XTAPI
VOID
MM::Pte::MapP5E(IN PVOID StartAddress,
IN PVOID EndAddress,
IN PMMP5E TemplateP5e)
{
PMMP5E EndSpace, PointerP5e;
/* Get P5E addresses */
PointerP5e = MM::Paging::GetP5eAddress(StartAddress);
EndSpace = MM::Paging::GetP5eAddress(EndAddress);
/* Iterate over all P5Es */
while(PointerP5e <= EndSpace)
{
/* Check if P5E is already mapped */
if(!MM::Paging::PteValid(PointerP5e))
{
/* Map P5E */
MM::Paging::SetPte(TemplateP5e, MM::Pfn::AllocateBootstrapPages(1), 0);
*PointerP5e = *TemplateP5e;
/* Clear the page table */
RTL::Memory::ZeroMemory(MM::Paging::GetPteVirtualAddress(PointerP5e), MM_PAGE_SIZE);
}
/* Get next table entry */
PointerP5e = MM::Paging::GetNextPte(PointerP5e);
}
}
/**
* Maps a range of virtual addresses at the PPE (Page Directory Pointer Entry) level.
*
* @param StartAddress
* The beginning of the virtual address range to map.
*
* @param EndAddress
* The end of the virtual address range to map.
*
* @param TemplatePpe
* A template PPE to use for creating new entries.
*
* @return This routine does not return any value.
*
* @since XT 1.0
*/
XTAPI
VOID
MM::Pte::MapPPE(IN PVOID StartAddress,
IN PVOID EndAddress,
IN PMMPPE TemplatePpe)
{
PMMPPE EndSpace, PointerPpe;
/* Get PPE addresses */
PointerPpe = MM::Paging::GetPpeAddress(StartAddress);
EndSpace = MM::Paging::GetPpeAddress(EndAddress);
/* Iterate over all PPEs */
while(PointerPpe <= EndSpace)
{
/* Check if PPE is already mapped */
if(!MM::Paging::PteValid(PointerPpe))
{
/* Map PPE */
MM::Paging::SetPte(TemplatePpe, MM::Pfn::AllocateBootstrapPages(1), 0);
*PointerPpe = *TemplatePpe;
/* Clear the page table */
RTL::Memory::ZeroMemory(MM::Paging::GetPteVirtualAddress(PointerPpe), MM_PAGE_SIZE);
}
/* Get next table entry */
PointerPpe = MM::Paging::GetNextPte(PointerPpe);
}
}
/**
* Maps a range of virtual addresses at the PXE (PML4) level.
*
* @param StartAddress
* The beginning of the virtual address range to map.
*
* @param EndAddress
* The end of the virtual address range to map.
*
* @param TemplatePxe
* A template PXE to use for creating new entries.
*
* @return This routine does not return any value.
*
* @since XT 1.0
*/
XTAPI
VOID
MM::Pte::MapPXE(IN PVOID StartAddress,
IN PVOID EndAddress,
IN PMMPXE TemplatePxe)
{
PMMPXE EndSpace, PointerPxe;
/* Get PXE addresses */
PointerPxe = MM::Paging::GetPxeAddress(StartAddress);
EndSpace = MM::Paging::GetPxeAddress(EndAddress);
/* Iterate over all PTEs */
while(PointerPxe <= EndSpace)
{
/* Check if PTE is already mapped */
if(!MM::Paging::PteValid(PointerPxe))
{
/* Map PTE */
MM::Paging::SetPte(TemplatePxe, MM::Pfn::AllocateBootstrapPages(1), 0);
*PointerPxe = *TemplatePxe;
/* Clear the page table */
RTL::Memory::ZeroMemory(MM::Paging::GetPteVirtualAddress(PointerPxe), MM_PAGE_SIZE);
}
/* Get next table entry */
PointerPxe = MM::Paging::GetNextPte(PointerPxe);
}
}

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@@ -1,178 +0,0 @@
/**
* PROJECT: ExectOS
* COPYRIGHT: See COPYING.md in the top level directory
* FILE: xtoskrnl/mm/colors.cc
* DESCRIPTION: Memory manager page coloring subsystem
* DEVELOPERS: Aiken Harris <harraiken91@gmail.com>
*/
#include <xtos.hh>
/**
* Computes & initializes the system's page coloring.
*
* @return This routine does not return any value.
*
* @since XT 1.0
*/
XTAPI
VOID
MM::Colors::ComputePageColoring(VOID)
{
UNIMPLEMENTED;
/* Compute L2 paging colors and mask */
PagingColors = MM_PAGING_COLORS;
PagingColorsMask = PagingColors - 1;
}
/**
* Retrieves a pointer to the color table for a specific page list and color.
*
* @param PageList
* The page list type (e.g., FreePageList, ZeroedPageList).
*
* @param Color
* Supplies the specific color index.
*
* @return This routine returns a pointer to the corresponding MMCOLOR_TABLES structure.
*
* @since XT 1.0
*/
XTAPI
PMMCOLOR_TABLES
MM::Colors::GetFreePages(IN MMPAGELISTS PageList,
IN ULONG Color)
{
/* Return a pointer to the requested color table entry */
return &FreePages[PageList][Color];
}
/**
* Retrieves a pointer to the modified pages list for a specific color.
*
* @param Color
* Supplies the specific color index.
*
* @return This routine returns a pointer to the corresponding MMPFNLIST structure.
*
* @since XT 1.0
*/
XTAPI
PMMPFNLIST
MM::Colors::GetModifiedPages(IN ULONG Color)
{
return &ModifiedPages[Color];
}
/**
* Retrieves the next available color for page coloring.
*
* @return This routine returns the next color value, ensuring it stays within the valid color range.
*
* @since XT 1.0
*/
XTAPI
ULONG
MM::Colors::GetNextColor(VOID)
{
/* Increment the color counter and wrap it around using the mask */
return ((++PagingColors) & PagingColorsMask);
}
/**
* Retrieves the total number of page colors configured in the system.
*
* @return This routine returns the number of page colors.
*
* @since XT 1.0
*/
XTAPI
ULONG
MM::Colors::GetPagingColors(VOID)
{
/* Return the total number of page colors */
return PagingColors;
}
/**
* Retrieves the bitmask used for calculating a page's color.
*
* @return This routine returns the page color mask.
*
* @since XT 1.0
*/
XTAPI
ULONG
MM::Colors::GetPagingColorsMask(VOID)
{
/* Return the mask used for page coloring calculations */
return PagingColorsMask;
}
/**
* Initializes the data structures for page coloring.
*
* @return This routine does not return any value.
*
* @since XT 1.0
*/
XTAPI
VOID
MM::Colors::InitializeColorTables(VOID)
{
PMMMEMORY_LAYOUT MemoryLayout;
PMMPTE PointerPte, LastPte;
ULONG Color;
PMMPTE ValidPte;
/* Get the memory layout */
MemoryLayout = MM::Manager::GetMemoryLayout();
/* Set the base address of the color tables to start right after the PFN database */
FreePages[0] = (PMMCOLOR_TABLES)&((PMMPFN)MemoryLayout->PfnDatabaseAddress)[MM::Pfn::GetHighestPhysicalPage() + 1];
/* Calculate the virtual address range for both color tables */
PointerPte = MM::Paging::GetPteAddress(&FreePages[0][0]);
LastPte = MM::Paging::GetPteAddress((PVOID)((ULONG_PTR)FreePages[0] +
(2 * PagingColors * sizeof(MMCOLOR_TABLES)) - 1));
/* Get a pointer to a PTE template */
ValidPte = MM::Pte::GetValidPte();
/* Ensure the entire virtual address range for the color tables is mapped */
while(PointerPte <= LastPte)
{
/* Check if a page in the range is not mapped */
if(!MM::Paging::PteValid(PointerPte))
{
/* Use the bootstrap allocator to get a physical page */
MM::Paging::SetPte(ValidPte, MM::Pfn::AllocateBootstrapPages(1), 0);
*PointerPte = *ValidPte;
/* Zero out the newly mapped page */
RTL::Memory::ZeroMemory(MM::Paging::GetPteVirtualAddress(PointerPte), MM_PAGE_SIZE);
}
/* Move to the next PTE in the range */
PointerPte = MM::Paging::GetNextPte(PointerPte);
}
/* Set the pointer for the second list */
FreePages[1] = &FreePages[0][PagingColors];
/* Initialize all entries in both color tables */
for(Color = 0; Color < PagingColors; Color++)
{
/* Initialize the FreePageList entry for the current color */
FreePages[FreePageList][Color].Flink = MAXULONG_PTR;
FreePages[FreePageList][Color].Blink = (PVOID)MAXULONG_PTR;
FreePages[FreePageList][Color].Count = 0;
/* Initialize the ZeroedPageList entry for the current color */
FreePages[ZeroedPageList][Color].Flink = MAXULONG_PTR;
FreePages[ZeroedPageList][Color].Blink = (PVOID)MAXULONG_PTR;
FreePages[ZeroedPageList][Color].Count = 0;
}
}

103
xtoskrnl/mm/data.cc
View File

@@ -9,18 +9,6 @@
#include <xtos.hh>
/* Array of free page lists segregated by cache color */
PMMCOLOR_TABLES MM::Colors::FreePages[FreePageList + 1];
/* Array of modified pages segregated by cache color */
MMPFNLIST MM::Colors::ModifiedPages[MM_PAGING_COLORS] = {{0, ModifiedPageList, MAXULONG_PTR, MAXULONG_PTR}};
/* Number of supported page colors */
ULONG MM::Colors::PagingColors;
/* Bitmask used to calculate the cache color index */
ULONG MM::Colors::PagingColorsMask;
/* Allocation descriptors dedicated for hardware layer */
LOADER_MEMORY_DESCRIPTOR MM::HardwarePool::HardwareAllocationDescriptors[MM_HARDWARE_ALLOCATION_DESCRIPTORS];
@@ -30,84 +18,23 @@ PVOID MM::HardwarePool::HardwareHeapStart = MM_HARDWARE_HEAP_START_ADDRESS;
/* Number of used hardware allocation descriptors */
ULONG MM::HardwarePool::UsedHardwareAllocationDescriptors = 0;
/* Biggest free memory descriptor */
PLOADER_MEMORY_DESCRIPTOR MM::Init::FreeDescriptor;
/* Highest physical page number */
ULONG_PTR MM::Init::HighestPhysicalPage;
/* Lowest physical page number */
ULONG_PTR MM::Init::LowestPhysicalPage = -1;
/* Number of physical pages */
ULONG MM::Init::NumberOfPhysicalPages;
/* Old biggest free memory descriptor */
LOADER_MEMORY_DESCRIPTOR MM::Init::OldFreeDescriptor;
/* Processor structures data (THIS IS A TEMPORARY HACK) */
UCHAR MM::KernelPool::ProcessorStructuresData[MAXIMUM_PROCESSORS][KPROCESSOR_STRUCTURES_SIZE] = {{0}};
/* Global structure describing the virtual memory layout of the system */
MMMEMORY_LAYOUT MM::Manager::MemoryLayout;
/* Total number of PTEs reserved for system space mapping */
PFN_NUMBER MM::Manager::NumberOfSystemPtes;
/* Instance of the page map routines for the current PML level */
MM::PPAGEMAP MM::Paging::PmlRoutines;
/* Total number of physical pages available for allocation */
PFN_NUMBER MM::Pfn::AvailablePages;
/* Head of the list containing physical pages marked as defective */
MMPFNLIST MM::Pfn::BadPagesList = {0, BadPageList, MAXULONG_PTR, MAXULONG_PTR};
/* Biggest free memory descriptor */
PLOADER_MEMORY_DESCRIPTOR MM::Pfn::FreeDescriptor;
/* List containing free physical pages */
MMPFNLIST MM::Pfn::FreePagesList = {0, FreePageList, MAXULONG_PTR, MAXULONG_PTR};
/* Highest physical page number */
ULONG_PTR MM::Pfn::HighestPhysicalPage;
/* Lowest physical page number */
ULONG_PTR MM::Pfn::LowestPhysicalPage = -1;
/* List containing modified pages */
MMPFNLIST MM::Pfn::ModifiedPagesList = {0, ModifiedPageList, MAXULONG_PTR, MAXULONG_PTR};
/* List containing modified pages mapped as read-only */
MMPFNLIST MM::Pfn::ModifiedReadOnlyPagesList = {0, ModifiedReadOnlyPageList, MAXULONG_PTR, MAXULONG_PTR};
/* Number of physical pages */
ULONGLONG MM::Pfn::NumberOfPhysicalPages;
/* Old biggest free memory descriptor */
LOADER_MEMORY_DESCRIPTOR MM::Pfn::OriginalFreeDescriptor;
/* Array of pointers to PFN lists */
PMMPFNLIST MM::Pfn::PageLocationList[] = {&ZeroedPagesList,
&FreePagesList,
&StandbyPagesList,
&ModifiedPagesList,
&ModifiedReadOnlyPagesList,
&BadPagesList,
NULLPTR,
NULLPTR};
/* Size of the PFN database in pages */
PFN_NUMBER MM::Pfn::PfnDatabaseSize;
/* List containing pages mapped as Read-Only (ROM) */
MMPFNLIST MM::Pfn::RomPagesList = {0, StandbyPageList, MAXULONG_PTR, MAXULONG_PTR};
/* List containing standby pages (clean, can be reclaimed or repurposed) */
MMPFNLIST MM::Pfn::StandbyPagesList = {0, StandbyPageList, MAXULONG_PTR, MAXULONG_PTR};
/* List containing free physical pages that have been zeroed out */
MMPFNLIST MM::Pfn::ZeroedPagesList = {0, ZeroedPageList, MAXULONG_PTR, MAXULONG_PTR};
/* Array of lists for available System PTEs, separated by pool type */
MMPTE MM::Pte::FirstSystemFreePte[MaximumPtePoolTypes];
/* Virtual base address of the System PTE space */
PMMPTE MM::Pte::SystemPteBase;
/* End addresses for the System PTE ranges */
PMMPTE MM::Pte::SystemPtesEnd[MaximumPtePoolTypes];
/* Start addresses for the System PTE ranges */
PMMPTE MM::Pte::SystemPtesStart[MaximumPtePoolTypes];
/* Total count of available System PTEs */
PFN_COUNT MM::Pte::TotalSystemFreePtes[MaximumPtePoolTypes];
/* Template PTE entry containing standard flags for a valid, present kernel page */
MMPTE MM::Pte::ValidPte;

24
xtoskrnl/mm/hlpool.cc
View File

@@ -170,7 +170,7 @@ MM::HardwarePool::MapHardwareMemory(IN PHYSICAL_ADDRESS PhysicalAddress,
{
PVOID BaseAddress, ReturnAddress;
PFN_NUMBER MappedPages;
PMMPTE PtePointer;
PHARDWARE_PTE PtePointer;
/* Initialize variables */
BaseAddress = HardwareHeapStart;
@@ -189,7 +189,7 @@ MM::HardwarePool::MapHardwareMemory(IN PHYSICAL_ADDRESS PhysicalAddress,
}
/* Get PTE pointer and advance to next page */
PtePointer = MM::Paging::GetPteAddress(ReturnAddress);
PtePointer = (PHARDWARE_PTE)MM::Paging::GetPteAddress(ReturnAddress);
ReturnAddress = (PVOID)((ULONG_PTR)ReturnAddress + MM_PAGE_SIZE);
/* Check if PTE is valid */
@@ -219,10 +219,10 @@ MM::HardwarePool::MapHardwareMemory(IN PHYSICAL_ADDRESS PhysicalAddress,
while(MappedPages--)
{
/* Get PTE pointer */
PtePointer = MM::Paging::GetPteAddress(BaseAddress);
PtePointer = (PHARDWARE_PTE)MM::Paging::GetPteAddress(BaseAddress);
/* Fill the PTE */
MM::Paging::SetPte(PtePointer, (PFN_NUMBER)(PhysicalAddress.QuadPart >> MM_PAGE_SHIFT), MM_PTE_READWRITE);
MM::Paging::SetPte(PtePointer, (PFN_NUMBER)(PhysicalAddress.QuadPart >> MM_PAGE_SHIFT), TRUE);
/* Advance to the next address */
PhysicalAddress.QuadPart += MM_PAGE_SIZE;
@@ -259,18 +259,18 @@ VOID
MM::HardwarePool::MarkHardwareMemoryWriteThrough(IN PVOID VirtualAddress,
IN PFN_NUMBER PageCount)
{
PMMPTE PtePointer;
PHARDWARE_PTE PtePointer;
PFN_NUMBER Page;
/* Get PTE address from virtual address */
PtePointer = MM::Paging::GetPteAddress(VirtualAddress);
PtePointer = (PHARDWARE_PTE)MM::Paging::GetPteAddress(VirtualAddress);
/* Iterate through mapped pages */
for(Page = 0; Page < PageCount; Page++)
{
/* Mark pages as CD/WT */
MM::Paging::SetPteCaching(PtePointer, TRUE, TRUE);
MM::Paging::GetNextEntry(PtePointer);
PtePointer++;
}
}
@@ -296,13 +296,13 @@ MM::HardwarePool::RemapHardwareMemory(IN PVOID VirtualAddress,
IN PHYSICAL_ADDRESS PhysicalAddress,
IN BOOLEAN FlushTlb)
{
PMMPTE PtePointer;
PHARDWARE_PTE PtePointer;
/* Get PTE address from virtual address */
PtePointer = MM::Paging::GetPteAddress(VirtualAddress);
PtePointer = (PHARDWARE_PTE)MM::Paging::GetPteAddress(VirtualAddress);
/* Remap the PTE */
MM::Paging::SetPte(PtePointer, (PFN_NUMBER)(PhysicalAddress.QuadPart >> MM_PAGE_SHIFT), MM_PTE_READWRITE);
MM::Paging::SetPte(PtePointer, (PFN_NUMBER)(PhysicalAddress.QuadPart >> MM_PAGE_SHIFT), TRUE);
/* Check if TLB needs to be flushed */
if(FlushTlb)
@@ -334,7 +334,7 @@ MM::HardwarePool::UnmapHardwareMemory(IN PVOID VirtualAddress,
IN PFN_NUMBER PageCount,
IN BOOLEAN FlushTlb)
{
PMMPTE PtePointer;
PHARDWARE_PTE PtePointer;
PFN_NUMBER Page;
/* Check if address is valid hardware memory */
@@ -348,7 +348,7 @@ MM::HardwarePool::UnmapHardwareMemory(IN PVOID VirtualAddress,
VirtualAddress = (PVOID)((ULONG_PTR)VirtualAddress & ~(MM_PAGE_SIZE - 1));
/* Get PTE address from virtual address */
PtePointer = MM::Paging::GetPteAddress(VirtualAddress);
PtePointer = (PHARDWARE_PTE)MM::Paging::GetPteAddress(VirtualAddress);
/* Iterate through mapped pages */
for(Page = 0; Page < PageCount; Page++)

25
xtoskrnl/mm/i686/init.cc Normal file
View File

@@ -0,0 +1,25 @@
/**
* PROJECT: ExectOS
* COPYRIGHT: See COPYING.md in the top level directory
* FILE: xtoskrnl/mm/i686/init.cc
* DESCRIPTION: Architecture specific Memory Manager initialization routines
* DEVELOPERS: Rafal Kupiec <belliash@codingworkshop.eu.org>
* Aiken Harris <harraiken91@gmail.com>
*/
#include <xtos.hh>
/**
* Performs architecture specific initialization of the XTOS Memory Manager.
*
* @return This routine does not return any value.
*
* @since XT 1.0
*/
XTAPI
VOID
MM::Init::InitializeArchitecture(VOID)
{
UNIMPLEMENTED;
}

92
xtoskrnl/mm/i686/mmgr.cc
View File

@@ -1,92 +0,0 @@
/**
* PROJECT: ExectOS
* COPYRIGHT: See COPYING.md in the top level directory
* FILE: xtoskrnl/mm/i686/mmgr.cc
* DESCRIPTION: Memory Manager
* DEVELOPERS: Aiken Harris <harraiken91@gmail.com>
*/
#include <xtos.hh>
/**
* Initializes the kernel's virtual memory layout.
*
* @return This routine does not return any value.
*
* @since XT 1.0
*/
XTAPI
VOID
MM::Manager::InitializeMemoryLayout(VOID)
{
ULONG_PTR PagedPoolSize, PteCount;
PFN_NUMBER PfnDatabaseSize, PhysicalPages;
ULONG PtesPerPage;
/* Define the number of system PTEs */
NumberOfSystemPtes = MM_DEFAULT_NUMBER_SYSTEM_PTES;
/* Retrieve the number of physical pages */
PhysicalPages = MM::Pfn::GetNumberOfPhysicalPages();
/* Verify the number of physical pages */
if(PhysicalPages < 8192)
{
/* Less than 32MiB of physical memory (8192 pages), use the minimum number of system PTEs */
NumberOfSystemPtes = MM_MINIMUM_NUMBER_SYSTEM_PTES;
}
else if(PhysicalPages > 32768)
{
/* More than 128MiB of physical memory (32768 pages), use the maximum number of system PTEs */
NumberOfSystemPtes = MM_MAXIMUM_NUMBER_SYSTEM_PTES;
}
/* Calculate size of paged pool */
PtesPerPage = MM::Pte::GetPtesPerPage();
PteCount = (SIZE_TO_PAGES(33554432) + (PtesPerPage - 1)) / PtesPerPage;
PagedPoolSize = PteCount * PtesPerPage * MM_PAGE_SIZE;
/* Retrieve the PFN database size */
PfnDatabaseSize = MM::Pfn::GetPfnDatabaseSize();
/* Check if 3-level paging (PAE) is enabled */
if(MM::Paging::GetXpaStatus())
{
/* Configure memory layout for 3-level paging, using 36bit address space and providing a 64 GB address space */
MemoryLayout.PfnDatabaseAddress = (PMMPFN)0xB0000000;
MemoryLayout.SelfMapAddress = (PVOID)MM_PTE_BASE;
/* Define the non-paged and paged pool regions */
MemoryLayout.NonPagedPoolStart = (PVOID)((ULONG_PTR)MemoryLayout.PfnDatabaseAddress + PfnDatabaseSize * MM_PAGE_SIZE);
MemoryLayout.NonPagedPoolEnd = (PVOID)0xEEFFFFFF;
MemoryLayout.PagedPoolStart = (PVOID)0xE2000000;
MemoryLayout.PagedPoolEnd = (PVOID)(((ULONG_PTR)MemoryLayout.PagedPoolStart + PagedPoolSize) - 1);
/* Define hyperspace, system PTE space, and the user space limit */
MemoryLayout.HyperSpaceStart = (PVOID)0xC0800000;
MemoryLayout.HyperSpaceEnd = (PVOID)0xC0BFFFFF;
MemoryLayout.SystemSpaceStart = (PVOID)0xC0C00000;
MemoryLayout.SystemSpaceEnd = (PVOID)((ULONG_PTR)MemoryLayout.SystemSpaceStart + (NumberOfSystemPtes + 1) * MM_PAGE_SIZE);
MemoryLayout.UserSpaceEnd = (PVOID)0x7FFEFFFF;
}
else
{
/* Configure memory layout for 2-level paging, using 32bit address space and providing a 4 GB address space */
MemoryLayout.PfnDatabaseAddress = (PMMPFN)0xB0000000;
MemoryLayout.SelfMapAddress = (PVOID)MM_PTE_BASE;
/* Define the non-paged and paged pool regions */
MemoryLayout.NonPagedPoolStart = (PVOID)((ULONG_PTR)MemoryLayout.PfnDatabaseAddress + PfnDatabaseSize * MM_PAGE_SIZE);
MemoryLayout.NonPagedPoolEnd = (PVOID)0xFFBE0000;
MemoryLayout.PagedPoolStart = (PVOID)0xE1000000;
MemoryLayout.PagedPoolEnd = (PVOID)(((ULONG_PTR)MemoryLayout.PagedPoolStart + PagedPoolSize) - 1);
/* Define hyperspace, system PTE space, and the user space limit */
MemoryLayout.HyperSpaceStart = (PVOID)0xC0400000;
MemoryLayout.HyperSpaceEnd = (PVOID)0xC07FFFFF;
MemoryLayout.SystemSpaceStart = (PVOID)0xC0800000;
MemoryLayout.SystemSpaceEnd = (PVOID)((ULONG_PTR)MemoryLayout.SystemSpaceStart + (NumberOfSystemPtes + 1) * MM_PAGE_SIZE);
MemoryLayout.UserSpaceEnd = (PVOID)0x7FFEFFFF;
}
}

931
xtoskrnl/mm/i686/pagemap.cc
View File

File diff suppressed because it is too large Load Diff

36
xtoskrnl/mm/i686/pfault.cc
View File

@@ -1,36 +0,0 @@
/**
* PROJECT: ExectOS
* COPYRIGHT: See COPYING.md in the top level directory
* FILE: xtoskrnl/mm/i686/pfault.cc
* DESCRIPTION: Page fault support for i686 architecture
* DEVELOPERS: Aiken Harris <harraiken91@gmail.com>
*/
#include <xtos.hh>
/**
* Evaluates the PDE for for paged pool and per-session mappings.
*
* @param VirtualAddress
* Specifies the virtual address to verify.
*
* @return This routine returns ACCESS_VIOLATION on PML3 or status code on PML2.
*/
XTFASTCALL
XTSTATUS
MM::PageFault::CheckPdeForPagedPool(IN PVOID VirtualAddress)
{
/* Check if XPA is enabled */
if(MM::Paging::GetXpaStatus())
{
/* Access violation for PML3 */
return STATUS_ACCESS_VIOLATION;
}
/* Unimplemented path for PML2 */
UNIMPLEMENTED;
/* Temporarily, just return access violation */
return STATUS_ACCESS_VIOLATION;
}

342
xtoskrnl/mm/i686/pfn.cc
View File

@@ -1,342 +0,0 @@
/**
* PROJECT: ExectOS
* COPYRIGHT: See COPYING.md in the top level directory
* FILE: xtoskrnl/mm/i686/pfn.cc
* DESCRIPTION: Physical Frame Number for i686 support
* DEVELOPERS: Aiken Harris <harraiken91@gmail.com>
* Rafal Kupiec <belliash@codingworkshop.eu.org>
*/
#include <xtos.hh>
/**
* Initializes the PFN database by mapping virtual memory and populating entries.
*
* @return This routine does not return any value.
*
* @since XT 1.0
*/
XTAPI
VOID
MM::Pfn::InitializePfnDatabase(VOID)
{
PLOADER_MEMORY_DESCRIPTOR Descriptor;
PKERNEL_INITIALIZATION_BLOCK InitializationBlock;
PLIST_ENTRY ListEntry;
PMMMEMORY_LAYOUT MemoryLayout;
PUCHAR PfnDatabaseEnd;
PMMPTE ValidPte;
/* Raise runlevel and acquire PFN lock */
KE::RaiseRunLevel RunLevel(DISPATCH_LEVEL);
KE::QueuedSpinLockGuard SpinLock(SystemSpaceLock);
/* Get the kernel initialization block */
InitializationBlock = KE::BootInformation::GetInitializationBlock();
/* Get memory layout */
MemoryLayout = MM::Manager::GetMemoryLayout();
/* Get the PFN database size and calculate the end of the PFN database virtual address space */
PfnDatabaseEnd = (PUCHAR)MemoryLayout->PfnDatabaseAddress + (PfnDatabaseSize * MM_PAGE_SIZE) - 1;
/* Get a template PTE for mapping the PFN database pages */
ValidPte = MM::Pte::GetValidPte();
/* Map the Page Directory and Page Directory Pointer tables for the PFN database */
MM::Pte::MapPDE(MemoryLayout->PfnDatabaseAddress, PfnDatabaseEnd, ValidPte);
MM::Pte::MapPTE(MemoryLayout->PfnDatabaseAddress, PfnDatabaseEnd, ValidPte);
/* Zero PFN database virtual space */
RTL::Memory::ZeroMemory(MemoryLayout->PfnDatabaseAddress, PfnDatabaseSize * MM_PAGE_SIZE);
/* Initialize the color tables */
MM::Colors::InitializeColorTables();
/* Iterate over memory descriptors to map the PFN database and initialize entries */
ListEntry = InitializationBlock->MemoryDescriptorListHead.Flink;
while(ListEntry != &InitializationBlock->MemoryDescriptorListHead)
{
/* Get the descriptor */
Descriptor = CONTAIN_RECORD(ListEntry, LOADER_MEMORY_DESCRIPTOR, ListEntry);
/* Skip invisible memory regions */
if(MM::Manager::VerifyMemoryTypeInvisible(Descriptor->MemoryType))
{
/* Move to the next descriptor and continue */
ListEntry = ListEntry->Flink;
continue;
}
/* Split PFN DB allocation out of free descriptor */
if(Descriptor == FreeDescriptor)
{
/* Initialize PFNs for the remaining free memory after the PFN database */
ProcessMemoryDescriptor(OriginalFreeDescriptor.BasePage + PfnDatabaseSize,
OriginalFreeDescriptor.PageCount - PfnDatabaseSize,
LoaderFree);
/* Initialize PFNs for the physical pages backing the PFN database itself */
ProcessMemoryDescriptor(OriginalFreeDescriptor.BasePage, PfnDatabaseSize, LoaderMemoryData);
}
else
{
/* Initialize PFNs for the physical pages described by this descriptor */
ProcessMemoryDescriptor(Descriptor->BasePage, Descriptor->PageCount, Descriptor->MemoryType);
}
/* Move to the next descriptor */
ListEntry = ListEntry->Flink;
}
/* Restore original free descriptor */
*FreeDescriptor = OriginalFreeDescriptor;
/* Initialize PFNs backing page tables */
InitializePageTablePfns();
}
/**
* Initializes PFN database entries for the system page tables.
*
* @return This routine does not return any value.
*
* @since XT 1.0
*/
XTAPI
VOID
MM::Pfn::InitializePageTablePfns(VOID)
{
PFN_NUMBER PageFrameIndex;
PMMPFN Pfn;
ULONG RootLevel;
PMMPTE RootPte;
/* Determine root structure based on paging mode */
if(MM::Paging::GetXpaStatus())
{
/* XPA enabled, 3-level paging (PAE) */
RootLevel = 3;
/* Retrieve the PFN of the PML3 table and its virtual base address */
PageFrameIndex = AR::CpuFunc::ReadControlRegister(3) >> MM_PAGE_SHIFT;
RootPte = (PMMPTE)MM::Paging::GetPpeAddress(NULLPTR);
}
else
{
/* XPA disabled, 2-level paging */
RootLevel = 2;
/* Retrieve the PFN of the PML2 table and its virtual base address */
PageFrameIndex = AR::CpuFunc::ReadControlRegister(3) >> MM_PAGE_SHIFT;
RootPte = (PMMPTE)MM::Paging::GetPdeAddress(NULLPTR);
}
/* Initialize the PFN entry for the root page table itself */
Pfn = GetPfnEntry(PageFrameIndex);
if(Pfn)
{
/* Initialize the PFN entry */
Pfn->PteAddress = NULLPTR;
Pfn->u1.WsIndex = 0;
Pfn->u2.ShareCount = 1;
Pfn->u3.e1.CacheAttribute = PfnNonCached;
Pfn->u3.e1.PageLocation = ActiveAndValid;
Pfn->u3.e2.ReferenceCount = 1;
Pfn->u4.PteFrame = 0;
}
/* Start recursive scan from the top level */
if(RootPte)
{
/* Scan the root page table */
ScanPageTable(RootPte, RootLevel);
}
}
/**
* Processes a memory descriptor and initializes the corresponding PFN database entries
*
* @param BasePage
* The starting physical page number of the memory run
*
* @param PageCount
* The number of pages in the memory run
*
* @param MemoryType
* The type of memory as reported by the bootloader (e.g., free, ROM, in-use)
*
* @return This routine does not return any value.
*
* @since XT 1.0
*/
XTAPI
VOID
MM::Pfn::ProcessMemoryDescriptor(IN PFN_NUMBER BasePage,
IN PFN_NUMBER PageCount,
IN LOADER_MEMORY_TYPE MemoryType)
{
PFN_NUMBER PageNumber;
PMMPDE PointerPde;
PMMPFN Pfn;
/* Check if the memory descriptor describes a free memory region */
if(MM::Manager::VerifyMemoryTypeFree(MemoryType))
{
/* Iterate over each page in this free memory run */
for(PageNumber = 0; PageNumber < PageCount; PageNumber++)
{
/* Get the PFN entry for the current page and ensure it is not referenced */
Pfn = GetPfnEntry(BasePage + PageNumber);
if(Pfn->u3.e2.ReferenceCount == 0)
{
/* Add the page to the free list to make it available for allocation */
LinkFreePage(BasePage + PageNumber);
}
}
}
else
{
/* Handle all other (non-free) memory types */
switch(MemoryType)
{
case LoaderBad:
/* This memory is marked as bad and should not be used */
for(PageNumber = 0; PageNumber < PageCount; PageNumber++)
{
/* Link the page to the bad pages list */
LinkPage(&BadPagesList, BasePage + PageNumber);
}
break;
case LoaderXIPRom:
/* This memory range contains Read-Only Memory (ROM) */
for(PageNumber = 0; PageNumber < PageCount; PageNumber++)
{
/* Get the PFN entry for the current ROM page */
Pfn = GetPfnEntry(BasePage + PageNumber);
/* Ensure that the page is not already in-use */
if(Pfn->u3.e2.ReferenceCount == 0)
{
/* Get the page directory entry for the current page */
PointerPde = MM::Paging::GetPdeAddress((PVOID)(KSEG0_BASE + (BasePage << MM_PAGE_SHIFT)));
/* Initialize the PFN entry to represent a ROM page */
Pfn->PteAddress = MM::Paging::GetPteAddress((PVOID)(KSEG0_BASE + (BasePage << MM_PAGE_SHIFT)));
Pfn->u1.Flink = 0;
Pfn->u2.ShareCount = 0;
Pfn->u3.e1.CacheAttribute = PfnNonCached;
Pfn->u3.e1.PageLocation = 0;
Pfn->u3.e1.PrototypePte = 1;
Pfn->u3.e1.Rom = 1;
Pfn->u3.e2.ReferenceCount = 0;
Pfn->u4.InPageError = 0;
Pfn->u4.PteFrame = MM::Paging::GetPageFrameNumber(PointerPde);
}
}
break;
default:
/* All other types are considered in-use (ie, by the kernel, ACPI, etc) */
for(PageNumber = 0; PageNumber < PageCount; PageNumber++)
{
/* Get the PFN entry for the current in-use page */
Pfn = GetPfnEntry(BasePage + PageNumber);
/* Ensure that the page is not already in-use */
if(Pfn->u3.e2.ReferenceCount == 0)
{
/* Get the page directory entry for the current page */
PointerPde = MM::Paging::GetPdeAddress((PVOID)(KSEG0_BASE + (BasePage << MM_PAGE_SHIFT)));
/* Initialize the PFN entry to represent an in-use page and prevent it from being allocated */
Pfn->PteAddress = MM::Paging::GetPteAddress((PVOID)(KSEG0_BASE + (BasePage << MM_PAGE_SHIFT)));
Pfn->u2.ShareCount++;
Pfn->u3.e1.CacheAttribute = PfnNonCached;
Pfn->u3.e1.PageLocation = ActiveAndValid;
Pfn->u3.e2.ReferenceCount = 1;
Pfn->u4.PteFrame = MM::Paging::GetPageFrameNumber(PointerPde);
}
}
break;
}
}
}
/**
* Recursively scans a page table to initialize PFN database entries for active pages.
*
* @param PointerPte
* Pointer to the base of the page table to scan.
*
* @param Level
* The paging level of the table being scanned.
*
* @return This routine does not return any value.
*
* @since XT 1.0
*/
XTAPI
VOID
MM::Pfn::ScanPageTable(IN PMMPTE PointerPte,
IN ULONG Level)
{
PVOID Address;
ULONG Index;
PMMPTE NextLevelPte;
ULONG PtesPerPage;
/* Get the number of PTEs per page */
PtesPerPage = MM::Pte::GetPtesPerPage();
/* Check if PML3 is enabled and current level is PDPT */
if(Level == 3)
{
/* PAE PDPT has only 4 entries */
PtesPerPage = 4;
}
/* Iterate through all entries in the current page table */
for(Index = 0; Index < PtesPerPage; Index++)
{
/* Check if the page table entry is present */
if(MM::Paging::PteValid(PointerPte))
{
/* Mark the PFN pointed to by this entry as active */
LinkPfnForPageTable(MM::Paging::GetPageFrameNumber(PointerPte), PointerPte);
/* Recurse to the next level, if this is not a leaf node (PTE) */
if(Level > 1)
{
/* Calculate the virtual address mapped by this entry to find the next table */
switch(Level)
{
case 3:
/* Calculate PDE */
Address = MM::Paging::GetPpeVirtualAddress(PointerPte);
NextLevelPte = (PMMPTE)MM::Paging::GetPdeAddress(Address);
break;
case 2:
/* Calculate PTE */
Address = MM::Paging::GetPdeVirtualAddress(PointerPte);
NextLevelPte = (PMMPTE)MM::Paging::GetPteAddress(Address);
break;
default:
/* Nothing to calculate, return NULLPTR */
NextLevelPte = NULLPTR;
break;
}
/* Recurse deeper if not at the bottom level (PTE) already */
if(NextLevelPte)
{
/* Recursively scan the next level page table */
ScanPageTable(NextLevelPte, Level - 1);
}
}
}
/* Move to the next entry in the current table */
PointerPte = MM::Paging::GetNextPte(PointerPte);
}
}

128
xtoskrnl/mm/i686/pte.cc
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@@ -1,128 +0,0 @@
/**
* PROJECT: ExectOS
* COPYRIGHT: See COPYING.md in the top level directory
* FILE: xtoskrnl/mm/i686/pte.cc
* DESCRIPTION: Page Table Entry (PTE) for i686 support
* DEVELOPERS: Aiken Harris <harraiken91@gmail.com>
*/
#include <xtos.hh>
/**
* Checks if the virtual address is valid and mapped in the page tables.
*
* @param VirtualAddress
* The virtual address to check.
*
* @return This routine returns TRUE if the address is valid, or FALSE otherwise.
*
* @since XT 1.0
*/
XTAPI
BOOLEAN
MM::Pte::AddressValid(IN PVOID VirtualAddress)
{
/* Check if PDE and PTE are valid */
if(!MM::Paging::PteValid(MM::Paging::GetPdeAddress(VirtualAddress)) ||
!MM::Paging::PteValid(MM::Paging::GetPteAddress(VirtualAddress)))
{
/* Invalid PDE or PTE, return FALSE */
return FALSE;
}
/* Address is valid, return TRUE */
return TRUE;
}
/**
* Retrieves the base virtual address of the system PTEs.
*
* @return This routine returns a pointer to the first PTE in the system PTE space.
*
* @since XT 1.0
*/
XTAPI
PMMPTE
MM::Pte::GetSystemPteBaseAddress(VOID)
{
return MM::Paging::GetPteAddress(NULLPTR);
}
/**
* Performs the initial setup of the system's page table hierarchy.
*
* @return This routine does not return any value.
*
* @since XT 1.0
*/
XTAPI
VOID
MM::Pte::InitializePageTable(VOID)
{
PMMPTE EndSpacePte, PointerPte;
PMMMEMORY_LAYOUT MemoryLayout;
CPUID_REGISTERS CpuRegisters;
MMPTE TemplatePte;
/* Retrieve current paging mode and memory layout */
MemoryLayout = MM::Manager::GetMemoryLayout();
/* Get CPU features */
CpuRegisters.Leaf = CPUID_GET_STANDARD1_FEATURES;
AR::CpuFunc::CpuId(&CpuRegisters);
/* Check if Paging Global Extensions (PGE) is supported */
if(CpuRegisters.Edx & CPUID_FEATURES_EDX_PGE)
{
/* Enable the Global Paging (PGE) feature */
AR::CpuFunc::WriteControlRegister(4, AR::CpuFunc::ReadControlRegister(4) | CR4_PGE);
}
/* Get the PD user-space range for both legacy and PAE paging */
PointerPte = (PMMPTE)MM::Paging::GetPdeAddress(0);
EndSpacePte = (PMMPTE)MM::Paging::GetPdeAddress(MemoryLayout->UserSpaceEnd);
/* Clear all top-level entries mapping the user address space */
while(PointerPte <= EndSpacePte)
{
MM::Paging::ClearPte(PointerPte);
PointerPte = MM::Paging::GetNextPte(PointerPte);
}
/* Flush the TLB to invalidate all non-global entries */
AR::CpuFunc::FlushTlb();
/* Create a template PTE for mapping kernel pages */
MM::Paging::ClearPte(&TemplatePte);
MM::Paging::SetPte(&TemplatePte, 0, MM_PTE_READWRITE | MM_PTE_CACHE_ENABLE);
/* Map the kernel's PD entries */
MM::Pte::MapPDE(MemoryLayout->SystemSpaceStart, (PVOID)MM_HIGHEST_SYSTEM_ADDRESS, &TemplatePte);
}
/**
* Maps a range of virtual addresses at the PPE (Page Directory Pointer Entry) level.
*
* @param StartAddress
* The beginning of the virtual address range to map.
*
* @param EndAddress
* The end of the virtual address range to map.
*
* @param TemplatePpe
* A template PPE to use for creating new entries.
*
* @return This routine does not return any value.
*
* @since XT 1.0
*/
XTAPI
VOID
MM::Pte::MapPPE(IN PVOID StartAddress,
IN PVOID EndAddress,
IN PMMPPE TemplatePpe)
{
/* Just a stub on i686 platform */
return;
}

150
xtoskrnl/mm/init.cc Normal file
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@@ -0,0 +1,150 @@
/**
* PROJECT: ExectOS
* COPYRIGHT: See COPYING.md in the top level directory
* FILE: xtoskrnl/mm/init.cc
* DESCRIPTION: Memory Manager initialization routines
* DEVELOPERS: Rafal Kupiec <belliash@codingworkshop.eu.org>
*/
#include <xtos.hh>
/**
* Performs an early initialization of the XTOS Memory Manager.
*
* @return This routine does not return any value.
*
* @since XT 1.0
*/
XTAPI
VOID
MM::Init::InitializeMemoryManager(VOID)
{
/* Scan memory descriptors provided by the boot loader */
ScanMemoryDescriptors();
/* Check if there are enough physical pages */
if(NumberOfPhysicalPages < MM_MINIMUM_PHYSICAL_PAGES)
{
/* Insufficient physical pages, kernel panic */
DebugPrint(L"Insufficient physical pages! Install additional memory\n");
KE::Crash::Panic(0);
}
/* Proceed with architecture specific initialization */
InitializeArchitecture();
}
/**
* Scans memory descriptors provided by the boot loader.
*
* @return This routine does not return any value.
*
* @since XT 1.0
*/
XTAPI
VOID
MM::Init::ScanMemoryDescriptors(VOID)
{
PLIST_ENTRY LoaderMemoryDescriptors, MemoryMappings;
PLOADER_MEMORY_DESCRIPTOR MemoryDescriptor;
PFN_NUMBER FreePages;
/* Initially, set number of free pages to 0 */
FreePages = 0;
/* Get a list of memory descriptors provided by the boot loader */
LoaderMemoryDescriptors = KE::BootInformation::GetMemoryDescriptors();
/* Iterate through memory mappings provided by the boot loader */
MemoryMappings = LoaderMemoryDescriptors->Flink;
while(MemoryMappings != LoaderMemoryDescriptors)
{
/* Get memory descriptor */
MemoryDescriptor = CONTAIN_RECORD(MemoryMappings, LOADER_MEMORY_DESCRIPTOR, ListEntry);
/* Check if memory type is invisible or cached */
if(VerifyMemoryTypeInvisible(MemoryDescriptor->MemoryType) ||
(MemoryDescriptor->MemoryType == LoaderHardwareCachedMemory))
{
/* Skip this mapping */
MemoryMappings = MemoryMappings->Flink;
continue;
}
/* Make sure that memory type is not bad */
if(MemoryDescriptor->MemoryType != LoaderBad)
{
/* Increment number of physical pages */
NumberOfPhysicalPages += MemoryDescriptor->PageCount;
}
/* Find lowest physical page */
if(MemoryDescriptor->BasePage < LowestPhysicalPage)
{
/* Update lowest physical page */
LowestPhysicalPage = MemoryDescriptor->BasePage;
}
/* Find highest physical page */
if(MemoryDescriptor->BasePage + MemoryDescriptor->PageCount > HighestPhysicalPage)
{
/* Update highest physical page */
HighestPhysicalPage = (MemoryDescriptor->BasePage + MemoryDescriptor->PageCount) - 1;
}
/* Check if memory type should be considered as free */
if(VerifyMemoryTypeFree(MemoryDescriptor->MemoryType))
{
/* Check if this descriptor contains more free pages */
if(MemoryDescriptor->PageCount >= FreePages)
{
/* Update free descriptor */
FreePages = MemoryDescriptor->PageCount;
FreeDescriptor = MemoryDescriptor;
}
}
/* Get next memory descriptor */
MemoryMappings = MemoryMappings->Flink;
}
/* Store original free descriptor */
RTL::Memory::CopyMemory(&OldFreeDescriptor, FreeDescriptor, sizeof(LOADER_MEMORY_DESCRIPTOR));
}
/** Checks whether the specified memory type should be considered as free.
*
* @param MemoryType
* Specifies the memory type to verify.
*
* @return This routine returns TRUE if the specified memory type should be considered as free, or FALSE otherwise.
*
* @since XT 1.0
*/
XTAPI
BOOLEAN
MM::Init::VerifyMemoryTypeFree(LOADER_MEMORY_TYPE MemoryType)
{
return ((MemoryType == LoaderFree) || (MemoryType == LoaderFirmwareTemporary) ||
(MemoryType == LoaderLoadedProgram) || (MemoryType == LoaderOsloaderStack));
}
/**
* Checks whether the specified memory type should be considered as invisible for the memory manager.
*
* @param MemoryType
* Specifies the memory type to verify.
*
* @return This routine returns TRUE if the specified memory type should be considered as invisible, or FALSE otherwise.
*
* @since XT 1.0
*/
XTAPI
BOOLEAN
MM::Init::VerifyMemoryTypeInvisible(LOADER_MEMORY_TYPE MemoryType)
{
return ((MemoryType == LoaderFirmwarePermanent) ||
(MemoryType == LoaderSpecialMemory) ||
(MemoryType == LoaderBBTMemory));
}

102
xtoskrnl/mm/kpool.cc
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@@ -4,7 +4,6 @@
* FILE: xtoskrnl/mm/kpool.cc
* DESCRIPTION: Kernel pool memory management
* DEVELOPERS: Rafal Kupiec <belliash@codingworkshop.eu.org>
* Aiken Harris <harraiken91@gmail.com>
*/
#include <xtos.hh>
@@ -28,68 +27,12 @@
*/
XTAPI
XTSTATUS
MM::KernelPool::AllocateKernelStack(OUT PVOID *Stack,
IN ULONG StackSize)
MM::KernelPool::AllocateKernelStack(IN PVOID *Stack,
IN BOOLEAN LargeStack,
IN UCHAR SystemNode)
{
PFN_COUNT StackPages;
PMMPTE PointerPte, StackPte;
MMPTE TempPte, InvalidPte;
PFN_NUMBER PageFrameIndex;
ULONG Index;
/* Initialize the output stack pointer to NULLPTR */
*Stack = NULLPTR;
/* Convert the requested stack size into a page count */
StackPages = SIZE_TO_PAGES(StackSize);
/* Reserve PTEs for the stack pages, plus a guard page */
StackPte = MM::Pte::ReserveSystemPtes(StackPages + 1, SystemPteSpace);
if(!StackPte)
{
/* Failed to reserve PTEs for the new kernel stack */
return STATUS_INSUFFICIENT_RESOURCES;
}
/* Set up a template for an invalid PTE */
MM::Paging::SetPte(&InvalidPte, 0, 0x18);
/* Set up a template for a valid, writable stack PTE */
MM::Paging::ClearPte(&TempPte);
MM::Paging::SetPte(&TempPte, 0, MM_PTE_READWRITE | MM_PTE_CACHE_ENABLE);
/* Acquire the PFN database lock and raise runlevel to DISPATCH_LEVEL */
KE::RaiseRunLevel RunLevel(DISPATCH_LEVEL);
KE::QueuedSpinLockGuard SpinLock(SystemSpaceLock);
/* Start iterating from the base of the reserved PTE block */
PointerPte = StackPte;
/* Loop through each page of the stack that needs to be allocated */
for(Index = 0; Index < StackPages; Index++)
{
/* Advance to the next PTE */
PointerPte = MM::Paging::GetNextPte(PointerPte);
/* Allocate a physical page and temporarily mark the PTE as invalid */
PageFrameIndex = MM::Pfn::AllocatePhysicalPage(MM::Colors::GetNextColor());
*PointerPte = InvalidPte;
/* Associate the physical page with its corresponding PTE in the PFN database */
MM::Pfn::LinkPfnToPte(PageFrameIndex, PointerPte, 1);
/* Make the PTE valid, mapping the virtual address to the physical page */
MM::Paging::SetPte(&TempPte, PageFrameIndex, 0);
*PointerPte = TempPte;
}
/* Zero the newly allocated stack memory, skipping the guard page */
RTL::Memory::ZeroMemory(MM::Paging::GetPteVirtualAddress(MM::Paging::GetNextPte(StackPte)),
MM_PAGE_SIZE * StackPages);
/* Return a pointer to the top of the new stack */
*Stack = MM::Paging::GetPteVirtualAddress(MM::Paging::AdvancePte(StackPte, StackPages + 1));
return STATUS_SUCCESS;
UNIMPLEMENTED;
return STATUS_NOT_IMPLEMENTED;
}
/**
@@ -153,40 +96,9 @@ MM::KernelPool::AllocateProcessorStructures(IN ULONG CpuNumber,
XTAPI
VOID
MM::KernelPool::FreeKernelStack(IN PVOID Stack,
IN ULONG StackSize)
IN BOOLEAN LargeStack)
{
PFN_COUNT StackPages;
PMMPTE PointerPte;
ULONG Index;
/* Get the PTE for the top of the stack, including the guard page */
MM::Paging::AdvancePte(MM::Paging::GetPteAddress(Stack), -1);
/* Convert the stack size into a page count */
StackPages = SIZE_TO_PAGES(StackSize);
/* Start guarded code block */
{
/* Acquire the PFN database lock */
KE::QueuedSpinLockGuard SpinLock(SystemSpaceLock);
/* Loop through each page of the stack that needs to be freed */
for(Index = 0; Index < StackPages; Index++)
{
/* Ensure the PTE is valid */
if(MM::Paging::PteValid(PointerPte))
{
/* Free the physical page */
MM::Pfn::FreePhysicalPage(PointerPte);
}
/* Advance to the next PTE */
PointerPte = MM::Paging::AdvancePte(PointerPte, -1);
}
}
/* Release all system PTEs used by the stack, including the guard page */
MM::Pte::ReleaseSystemPtes(PointerPte, StackPages + 1, SystemPteSpace);
UNIMPLEMENTED;
}
/**

131
xtoskrnl/mm/mmgr.cc
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@@ -1,131 +0,0 @@
/**
* PROJECT: ExectOS
* COPYRIGHT: See COPYING.md in the top level directory
* FILE: xtoskrnl/mm/mmgr.cc
* DESCRIPTION: Memory Manager
* DEVELOPERS: Rafal Kupiec <belliash@codingworkshop.eu.org>
* Aiken Harris <harraiken91@gmail.com>
*/
#include <xtos.hh>
/**
* Retrieves the amount of total available memory in the system.
*
* @return This routine returns the amount of available memory in the system in megabytes.
*
* @since XT 1.0
*/
XTAPI
ULONG_PTR
MM::Manager::GetInstalledMemorySize(VOID)
{
/* Return the amount of installed memory */
return (MM::Pfn::GetNumberOfPhysicalPages() * MM_PAGE_SIZE) / 1048576;
}
/**
* Retrieves a pointer to the system's virtual memory layout structure.
*
* @return This routine returns a pointer to the memory layout structure.
*
* @since XT 1.0
*/
XTAPI
PMMMEMORY_LAYOUT
MM::Manager::GetMemoryLayout(VOID)
{
/* Return a pointer to the global memory layout structure */
return &MemoryLayout;
}
XTAPI
PFN_NUMBER
MM::Manager::GetNumberOfSystemPtes()
{
return NumberOfSystemPtes;
}
/**
* Performs an early initialization of the XTOS Memory Manager.
*
* @return This routine does not return any value.
*
* @since XT 1.0
*/
XTAPI
VOID
MM::Manager::InitializeMemoryManager(VOID)
{
/* Scan memory descriptors provided by the boot loader */
MM::Pfn::ScanMemoryDescriptors();
/* Check if there are enough physical pages */
if(MM::Pfn::GetNumberOfPhysicalPages() < MM_MINIMUM_PHYSICAL_PAGES)
{
/* Insufficient physical pages, kernel panic */
DebugPrint(L"Insufficient physical pages! Install additional memory\n");
KE::Crash::Panic(0);
}
/* Compute page colors to reduce CPU cache conflicts */
MM::Colors::ComputePageColoring();
/* Compute allocation size for the PFN database */
MM::Pfn::ComputePfnDatabaseSize();
/* Initialize memory layout */
InitializeMemoryLayout();
/* Initialize PTE template */
MM::Pte::InitializeSystemPte();
/* Initialize page table */
MM::Pte::InitializePageTable();
/* Initialize system PTE space */
MM::Pte::InitializeSystemPteSpace();
/* Initialize PFN database */
MM::Pfn::InitializePfnDatabase();
}
/**
* Checks whether the specified memory type should be considered as free.
*
* @param MemoryType
* Specifies the memory type to verify.
*
* @return This routine returns TRUE if the specified memory type should be considered as free, or FALSE otherwise.
*
* @since XT 1.0
*/
XTAPI
BOOLEAN
MM::Manager::VerifyMemoryTypeFree(LOADER_MEMORY_TYPE MemoryType)
{
return ((MemoryType == LoaderFirmwareTemporary) ||
(MemoryType == LoaderFree) ||
(MemoryType == LoaderLoadedProgram) ||
(MemoryType == LoaderOsloaderStack));
}
/**
* Checks whether the specified memory type should be considered as invisible for the memory manager.
*
* @param MemoryType
* Specifies the memory type to verify.
*
* @return This routine returns TRUE if the specified memory type should be considered as invisible, or FALSE otherwise.
*
* @since XT 1.0
*/
XTAPI
BOOLEAN
MM::Manager::VerifyMemoryTypeInvisible(LOADER_MEMORY_TYPE MemoryType)
{
return ((MemoryType == LoaderBBTMemory) ||
(MemoryType == LoaderFirmwarePermanent) ||
(MemoryType == LoaderSpecialMemory));
}

420
xtoskrnl/mm/paging.cc
View File

@@ -9,28 +9,6 @@
#include <xtos.hh>
/**
* Advances a PTE pointer by a given number of entries, considering the actual PTE size.
*
* @param Pte
* The PTE pointer to advance.
*
* @param Count
* The number of PTE entries to advance by.
*
* @return The advanced PTE pointer.
*
* @since XT 1.0
*/
XTAPI
PMMPTE
MM::Paging::AdvancePte(IN PMMPTE Pte,
IN LONG Count)
{
/* Return advanced PTE pointer */
return PmlRoutines->AdvancePte(Pte, Count);
}
/**
* Clears the contents of a page table entry (PTE).
*
@@ -43,9 +21,8 @@ MM::Paging::AdvancePte(IN PMMPTE Pte,
*/
XTAPI
VOID
MM::Paging::ClearPte(IN PMMPTE PtePointer)
MM::Paging::ClearPte(PHARDWARE_PTE PtePointer)
{
/* Clear PTE */
PmlRoutines->ClearPte(PtePointer);
}
@@ -101,77 +78,6 @@ MM::Paging::FlushTlb(VOID)
}
}
/**
* Gets the next entry in a PTE list.
*
* @param Pte
* The PTE pointer to get the next entry from.
*
* @return This routine returns the next entry in the PTE list.
*
* @since XT 1.0
*/
XTAPI
ULONG_PTR
MM::Paging::GetNextEntry(IN PMMPTE Pte)
{
/* Return next entry in PTE list */
return PmlRoutines->GetNextEntry(Pte);
}
/**
* Advances a PTE pointer, considering the actual PTE size.
*
* @param Pte
* The PTE pointer to advance.
*
* @return The advanced PTE pointer.
*
* @since XT 1.0
*/
XTAPI
PMMPTE
MM::Paging::GetNextPte(IN PMMPTE Pte)
{
/* Return advanced PTE pointer */
return PmlRoutines->GetNextPte(Pte);
}
/**
* Checks if a PTE list contains only one entry.
*
* @param Pte
* The PTE pointer to check.
*
* @return This routine returns TRUE if the PTE list has only one entry, FALSE otherwise.
*
* @since XT 1.0
*/
XTAPI
BOOLEAN
MM::Paging::GetOneEntry(IN PMMPTE Pte)
{
/* Return one entry status */
return PmlRoutines->GetOneEntry(Pte);
}
/**
* Gets the page frame number from a corresponding PTE.
*
* @param Pte
* The PTE pointer to get the page frame number from.
*
* @return This routine returns the page frame number.
*
* @since XT 1.0
*/
XTAPI
PFN_NUMBER
MM::Paging::GetPageFrameNumber(IN PMMPTE Pte)
{
return PmlRoutines->GetPageFrameNumber(Pte);
}
/**
* Gets the page map routines for basic paging mode (non-XPA).
*
@@ -184,8 +90,6 @@ MM::PPAGEMAP
MM::Paging::GetPageMapBasicRoutines(VOID)
{
static MM::PageMapBasic PageMapBasicRoutines;
/* Return non-XPA page map routines */
return &PageMapBasicRoutines;
}
@@ -201,8 +105,6 @@ MM::PPAGEMAP
MM::Paging::GetPageMapXpaRoutines(VOID)
{
static MM::PageMapXpa PageMapXpaRoutines;
/* Return XPA page map routines */
return &PageMapXpaRoutines;
}
@@ -218,30 +120,11 @@ MM::Paging::GetPageMapXpaRoutines(VOID)
*/
XTAPI
PMMPDE
MM::Paging::GetPdeAddress(IN PVOID Address)
MM::Paging::GetPdeAddress(PVOID Address)
{
/* Return PDE address */
return PmlRoutines->GetPdeAddress(Address);
}
/**
* Gets the virtual address that is mapped by a given Page Directory Entry.
*
* @param PdePointer
* Specifies the address of the PDE.
*
* @return This routine returns the virtual address mapped by the PDE.
*
* @since XT 1.0
*/
XTAPI
PVOID
MM::Paging::GetPdeVirtualAddress(IN PMMPDE PdePointer)
{
/* Return PTE virtual address */
return PmlRoutines->GetPdeVirtualAddress(PdePointer);
}
/**
* Gets the address of the PPE (Page Directory Pointer Table Entry), that maps given address.
*
@@ -254,48 +137,11 @@ MM::Paging::GetPdeVirtualAddress(IN PMMPDE PdePointer)
*/
XTAPI
PMMPPE
MM::Paging::GetPpeAddress(IN PVOID Address)
MM::Paging::GetPpeAddress(PVOID Address)
{
/* Return PPE address */
return PmlRoutines->GetPpeAddress(Address);
}
/**
* Gets the virtual address that is mapped by a given Page Directory Pointer Table Entry.
*
* @param PpePointer
* Specifies the address of the PPE.
*
* @return This routine returns the virtual address mapped by the PPE.
*
* @since XT 1.0
*/
XTAPI
PVOID
MM::Paging::GetPpeVirtualAddress(IN PMMPPE PpePointer)
{
/* Return PTE virtual address */
return PmlRoutines->GetPpeVirtualAddress(PpePointer);
}
/**
* Gets the entire contents of a Page Table Entry (PTE) as a single value.
*
* @param PtePointer
* Pointer to the Page Table Entry (PTE) to read.
*
* @return This routine returns the contents of the PTE as a single value.
*
* @since XT 1.0
*/
XTAPI
ULONG_PTR
MM::Paging::GetPte(IN PMMPTE PtePointer)
{
/* Return PTE value */
return PmlRoutines->GetPte(PtePointer);
}
/**
* Gets the address of the PTE (Page Table Entry), that maps given address.
*
@@ -308,135 +154,11 @@ MM::Paging::GetPte(IN PMMPTE PtePointer)
*/
XTAPI
PMMPTE
MM::Paging::GetPteAddress(IN PVOID Address)
MM::Paging::GetPteAddress(PVOID Address)
{
/* Return PTE address */
return PmlRoutines->GetPteAddress(Address);
}
/**
* Calculates the distance between two PTE pointers.
*
* @param EndPte
* Pointer to the ending Page Table Entry.
*
* @param StartPte
* Pointer to the starting Page Table Entry.
*
* @return This routine returns a signed value representing the number of PTEs between EndPte and StartPte.
*
* @since XT 1.0
*/
XTAPI
LONG
MM::Paging::GetPteDistance(PMMPTE EndPte,
PMMPTE StartPte)
{
/* Return distance between PTE pointers */
return PmlRoutines->GetPteDistance(EndPte, StartPte);
}
/**
* Gets the size of a PTE.
*
* @return This routine returns the size of a PTE.
*
* @since XT 1.0
*/
XTAPI
ULONG
MM::Paging::GetPteSize(VOID)
{
/* Return the size of MMPTE */
return PmlRoutines->GetPteSize();
}
/**
* Gets the software protection value of the corresponding Page Table Entry.
*
* @param PtePointer
* Specifies the address of the PTE.
*
* @return This routine returns the PTE software protection value.
*
* @since XT 1.0
*/
XTAPI
ULONG
MM::Paging::GetPteSoftwareProtection(IN PMMPTE PtePointer)
{
/* Return PTE software protection value */
return PmlRoutines->GetPteSoftwareProtection(PtePointer);
}
/**
* Gets the software prototype value of the corresponding Page Table Entry.
*
* @param PtePointer
* Specifies the address of the PTE.
*
* @return This routine returns the PTE software prototype value.
*
* @since XT 1.0
*/
XTAPI
ULONG
MM::Paging::GetPteSoftwarePrototype(IN PMMPTE PtePointer)
{
/* Return PTE software prototype value */
return PmlRoutines->GetPteSoftwarePrototype(PtePointer);
}
/**
* Gets the software transition value of the corresponding Page Table Entry.
*
* @param PtePointer
* Specifies the address of the PTE.
*
* @return This routine returns the PTE software transition value.
*
* @since XT 1.0
*/
XTAPI
ULONG
MM::Paging::GetPteSoftwareTransition(IN PMMPTE PtePointer)
{
/* Return PTE software transition value */
return PmlRoutines->GetPteSoftwareTransition(PtePointer);
}
/**
* Gets the virtual address that is mapped by a given Page Table Entry.
*
* @param PtePointer
* Specifies the address of the PTE.
*
* @return This routine returns the virtual address mapped by the PTE.
*
* @since XT 1.0
*/
XTAPI
PVOID
MM::Paging::GetPteVirtualAddress(IN PMMPTE PtePointer)
{
/* Return PTE virtual address */
return PmlRoutines->GetPteVirtualAddress(PtePointer);
}
/**
* Gets current status of eXtended Physical Addressing (XPA).
*
* @return This routine returns TRUE if PAE or LA57 (XPA) is enabled, or FALSE otherwise.
*
* @since XT 1.0
*/
XTAPI
BOOLEAN
MM::Paging::GetXpaStatus()
{
return PmlRoutines->GetXpaStatus();
}
/**
* Detects if eXtended Physical Addressing (XPA) is enabled and initializes page map support.
*
@@ -476,58 +198,13 @@ MM::Paging::InitializePageMapSupport(VOID)
*/
XTAPI
BOOLEAN
MM::Paging::PteValid(IN PMMPTE PtePointer)
MM::Paging::PteValid(PHARDWARE_PTE PtePointer)
{
/* Check if PTE is valid */
return PmlRoutines->PteValid(PtePointer);
}
/**
* Sets the next entry in a PTE list.
*
* @param Pte
* The PTE pointer to modify.
*
* @param Value
* The value to set as the next entry.
*
* @return This routine does not return any value.
*
* @since XT 1.0
*/
XTAPI
VOID
MM::Paging::SetNextEntry(IN PMMPTE Pte,
IN ULONG_PTR Value)
{
/* Set next entry in PTE list */
PmlRoutines->SetNextEntry(Pte, Value);
}
/**
* Sets the flag indicating whether a PTE list contains only one entry.
*
* @param Pte
* The PTE pointer to modify.
*
* @param Value
* The value to set. TRUE if the list has only one entry, FALSE otherwise.
*
* @return This routine does not return any value.
*
* @since XT 1.0
*/
XTAPI
VOID
MM::Paging::SetOneEntry(IN PMMPTE Pte,
IN BOOLEAN Value)
{
/* Set one entry status */
PmlRoutines->SetOneEntry(Pte, Value);
}
/**
* Sets a Page Table Entry (PTE) with the specified physical page and access flags.
* Sets a PML2 page table entry (PTE) with the specified physical page and access flags.
*
* @param PtePointer
* Pointer to the page table entry (PTE) to set.
@@ -535,8 +212,8 @@ MM::Paging::SetOneEntry(IN PMMPTE Pte,
* @param PageFrameNumber
* Physical frame number to map.
*
* @param AttributesMask
* Specifies the attributes mask to apply to the PTE.
* @param Writable
* Indicates whether the page should be writable.
*
* @return This routine does not return any value.
*
@@ -544,33 +221,11 @@ MM::Paging::SetOneEntry(IN PMMPTE Pte,
*/
XTAPI
VOID
MM::Paging::SetPte(IN PMMPTE PtePointer,
IN PFN_NUMBER PageFrameNumber,
IN ULONG_PTR AttributesMask)
MM::Paging::SetPte(PHARDWARE_PTE PtePointer,
PFN_NUMBER PageFrameNumber,
BOOLEAN Writable)
{
/* Set PTE */
PmlRoutines->SetPte(PtePointer, PageFrameNumber, AttributesMask);
}
/**
* Sets a Page Table Entry (PTE) with the specified attributes.
*
* @param PtePointer
* Pointer to the page table entry (PTE) to set.
*
* @param Attributes
* Specifies the attributes to apply to the PTE.
*
* @return This routine does not return any value.
*
* @since XT 1.0
*/
XTAPI
VOID
MM::Paging::SetPte(IN PMMPTE PtePointer,
IN ULONG_PTR Attributes)
{
PmlRoutines->SetPte(PtePointer, Attributes);
PmlRoutines->SetPte(PtePointer, PageFrameNumber, Writable);
}
/**
@@ -591,54 +246,9 @@ MM::Paging::SetPte(IN PMMPTE PtePointer,
*/
XTAPI
VOID
MM::Paging::SetPteCaching(IN PMMPTE PtePointer,
IN BOOLEAN CacheDisable,
IN BOOLEAN WriteThrough)
MM::Paging::SetPteCaching(PHARDWARE_PTE PtePointer,
BOOLEAN CacheDisable,
BOOLEAN WriteThrough)
{
/* Set caching attributes */
PmlRoutines->SetPteCaching(PtePointer, CacheDisable, WriteThrough);
}
/**
* Transitions a Page Table Entry (PTE) to invalid state
*
* @param PointerPte
* Pointer to the page table entry (PTE) to transition.
*
* @param Protection
* Specifies the protection attribute to apply to the PTE.
*
* @return This routine does not return any value.
*
* @since XT 1.0
*/
XTAPI
VOID
MM::Paging::TransitionPte(IN PMMPTE PointerPte,
IN ULONG_PTR Protection)
{
/* Transition PTE */
PmlRoutines->TransitionPte(PointerPte, Protection);
}
/**
* Writes a Page Table Entry (PTE) with the specified value.
*
* @param Pte
* Pointer to the page table entry (PTE) to write.
*
* @param Value
* The value to write to the PTE.
*
* @return This routine does not return any value.
*
* @since XT 1.0
*/
XTAPI
VOID
MM::Paging::WritePte(IN PMMPTE Pte,
IN MMPTE Value)
{
/* Assign PTE value */
PmlRoutines->WritePte(Pte, Value);
}

1137
xtoskrnl/mm/pfn.cc
View File

File diff suppressed because it is too large Load Diff

541
xtoskrnl/mm/pte.cc
View File

@@ -1,541 +0,0 @@
/**
* PROJECT: ExectOS
* COPYRIGHT: See COPYING.md in the top level directory
* FILE: xtoskrnl/mm/pte.cc
* DESCRIPTION: Page Table Entry (PTE) support
* DEVELOPERS: Aiken Harris <harraiken91@gmail.com>
*/
#include <xtos.hh>
/**
* Finds a free cluster of system PTEs that can satisfy a given size.
*
* @param NumberOfPtes
* The number of contiguous PTEs required.
*
* @param SystemPtePoolType
* Specifies the system PTE pool to search within.
*
* @param FoundCluster
* On success, receives a pointer to the first PTE of the found cluster.
*
* @param PreviousClusterNode
* On success, receives a pointer to the list node that precedes the found cluster.
*
* @return This routine returns TRUE if a suitable cluster was found, FALSE otherwise.
*
* @since XT 1.0
*/
XTAPI
BOOLEAN
MM::Pte::FindFreeCluster(IN PFN_COUNT NumberOfPtes,
IN MMSYSTEM_PTE_POOL_TYPE SystemPtePoolType,
OUT PMMPTE *FoundCluster,
OUT PMMPTE *PreviousClusterNode)
{
PMMPTE CurrentCluster;
PMMPTE PreviousNode = &FirstSystemFreePte[SystemPtePoolType];
ULONG ClusterSize;
/* Find a free PTE cluster large enough for the request */
while(MM::Paging::GetNextEntry(PreviousNode) != MAXULONG)
{
/* Retrieve the cluster and its size */
CurrentCluster = MM::Paging::AdvancePte(SystemPteBase, MM::Paging::GetNextEntry(PreviousNode));
ClusterSize = GetClusterSize(CurrentCluster);
/* Check if this cluster is large enough */
if(NumberOfPtes <= ClusterSize)
{
/* Found a suitable cluster */
*FoundCluster = CurrentCluster;
*PreviousClusterNode = PreviousNode;
return TRUE;
}
/* This cluster is too small, check the next one */
PreviousNode = CurrentCluster;
}
/* No suitable cluster was found */
return FALSE;
}
/**
* Decodes and returns the size of a free PTE cluster.
*
* @param Pte
* Supplies a pointer to the first PTE of the free cluster to inspect.
*
* @return This routine returns the total number of contiguous PTEs in the free cluster.
*
* @since XT 1.0
*/
XTAPI
ULONG
MM::Pte::GetClusterSize(IN PMMPTE Pte)
{
/* A special flag in the first PTE indicates a free cluster of size one */
if(MM::Paging::GetOneEntry(Pte))
{
/* Flag is set, so the cluster size is 1 by definition */
return 1;
}
/* For larger clusters, the size is encoded in the second PTE of the block */
Pte = MM::Paging::GetNextPte(Pte);
return MM::Paging::GetNextEntry(Pte);
}
/**
* Calculates the number of Page Table Entries (PTEs) that fit within a single page.
*
* @return This routine returns the number of PTEs per page.
*
* @since XT 1.0
*/
XTAPI
PFN_COUNT
MM::Pte::GetPtesPerPage(VOID)
{
/* Calculate and return the number of PTEs per page */
return MM_PAGE_SIZE / MM::Paging::GetPteSize();
}
/**
* Returns a pointer to the valid PTE.
*
* @return This routine returns a pointer to the valid PTE.
*
* @since XT 1.0
*/
XTAPI
PMMPTE
MM::Pte::GetValidPte()
{
/* Return a pointer to the valid PTE */
return &ValidPte;
}
/**
* Initializes the system's PTE.
*
* @return This routine does not return any value.
*
* @since XT 1.0
*/
XTAPI
VOID
MM::Pte::InitializeSystemPte(VOID)
{
/* Initialize the PTE template */
MM::Paging::SetPte(&ValidPte, MM_PTE_VALID | MM_PTE_EXECUTE_READWRITE | MM_PTE_DIRTY | MM_PTE_ACCESSED);
}
/**
* Formats a range of PTEs into a freelist-based pool for system allocations.
*
* @param StartingPte
* Supplies a pointer to the start of the PTE range to be formatted.
*
* @param NumberOfPtes
* Supplies the total number of PTEs in the contiguous range.
*
* @param PoolType
* The system PTE pool type that this range will be used for.
*
* @return This routine does not return any value.
*
* @since XT 1.0
*/
XTAPI
VOID
MM::Pte::InitializeSystemPtePool(IN PMMPTE StartingPte,
IN PFN_COUNT NumberOfPtes,
IN MMSYSTEM_PTE_POOL_TYPE PoolType)
{
/* Set the system PTE base address */
SystemPteBase = GetSystemPteBaseAddress();
/* Record the boundaries of this new PTE pool */
SystemPtesStart[PoolType] = StartingPte;
SystemPtesEnd[PoolType] = MM::Paging::AdvancePte(StartingPte, NumberOfPtes - 1);
/* Zero the memory for the new PTE pool before use */
RTL::Memory::ZeroMemory(StartingPte, NumberOfPtes * MM::Paging::GetPteSize());
/* Build the free list head to point to the start of the pool */
MM::Paging::SetNextEntry(StartingPte, MAXULONG);
MM::Paging::ClearPte(&FirstSystemFreePte[PoolType]);
MM::Paging::SetNextEntry(&FirstSystemFreePte[PoolType], MM::Paging::GetPteDistance(StartingPte, SystemPteBase));
/* Use the second PTE slot to store the total size of this pool */
StartingPte = MM::Paging::GetNextPte(StartingPte);
MM::Paging::ClearPte(StartingPte);
MM::Paging::SetNextEntry(StartingPte, NumberOfPtes);
/* Record the total number of free PTEs in this pool */
TotalSystemFreePtes[PoolType] = NumberOfPtes;
}
/**
* Sets up the entire system PTE address space.
*
* @return This routine does not return any value.
*
* @since XT 1.0
*/
XTAPI
VOID
MM::Pte::InitializeSystemPteSpace(VOID)
{
PMMPTE PointerPte;
PMMPTE FirstZeroingPte;
PMMMEMORY_LAYOUT MemoryLayout;
/* Retrieve the system's memory layout */
MemoryLayout = MM::Manager::GetMemoryLayout();
/* Map the page table hierarchy for the entire system PTE space */
MM::Pte::MapPPE(MemoryLayout->SystemSpaceStart, MemoryLayout->SystemSpaceEnd, &ValidPte);
MM::Pte::MapPDE(MemoryLayout->SystemSpaceStart, MemoryLayout->SystemSpaceEnd, &ValidPte);
/* Format the main block of system PTEs into a free list pool */
PointerPte = MM::Paging::GetPteAddress(MemoryLayout->SystemSpaceStart);
InitializeSystemPtePool(PointerPte, MM::Manager::GetNumberOfSystemPtes(), SystemPteSpace);
/* Reserve and zero a dedicated block of system PTEs */
FirstZeroingPte = ReserveSystemPtes(MM_RESERVED_ZERO_PTES + 1, SystemPteSpace);
RTL::Memory::ZeroMemory(FirstZeroingPte, (MM_RESERVED_ZERO_PTES + 1) * MM::Paging::GetPteSize());
/* Use the first PTE of this block as a counter for available zeroing PTEs */
MM::Paging::SetPte(FirstZeroingPte, MM_RESERVED_ZERO_PTES, 0);
}
/**
* Maps a range of virtual addresses at the PDE (Page Directory Entry) level.
*
* @param StartAddress
* The beginning of the virtual address range to map.
*
* @param EndAddress
* The end of the virtual address range to map.
*
* @param TemplatePde
* A template PDE to use for creating new entries.
*
* @return This routine does not return any value.
*
* @since XT 1.0
*/
XTAPI
VOID
MM::Pte::MapPDE(IN PVOID StartAddress,
IN PVOID EndAddress,
IN PMMPDE TemplatePde)
{
PMMPDE EndSpace, PointerPde;
/* Get PDE addresses */
PointerPde = MM::Paging::GetPdeAddress(StartAddress);
EndSpace = MM::Paging::GetPdeAddress(EndAddress);
/* Iterate over all PDEs */
while(PointerPde <= EndSpace)
{
/* Check if PDE is already mapped */
if(!MM::Paging::PteValid(PointerPde))
{
/* Map PDE */
MM::Paging::SetPte(TemplatePde, MM::Pfn::AllocateBootstrapPages(1), 0);
MM::Paging::WritePte(PointerPde, *TemplatePde);
/* Clear the page table */
RTL::Memory::ZeroMemory(MM::Paging::GetPteVirtualAddress(PointerPde), MM_PAGE_SIZE);
}
/* Get next table entry */
PointerPde = MM::Paging::GetNextPte(PointerPde);
}
}
/**
* Maps a range of virtual addresses at the PTE (Page Table Entry) level.
*
* @param StartAddress
* The beginning of the virtual address range to map.
*
* @param EndAddress
* The end of the virtual address range to map.
*
* @param TemplatePte
* A template PTE to use for creating new entries.
*
* @return This routine does not return any value.
*
* @since XT 1.0
*/
XTAPI
VOID
MM::Pte::MapPTE(IN PVOID StartAddress,
IN PVOID EndAddress,
IN PMMPTE TemplatePte)
{
PMMPTE EndSpace, PointerPte;
/* Get PTE addresses */
PointerPte = MM::Paging::GetPteAddress(StartAddress);
EndSpace = MM::Paging::GetPteAddress(EndAddress);
/* Iterate over all PTEs */
while(PointerPte <= EndSpace)
{
/* Check if PTE is already mapped */
if(!MM::Paging::PteValid(PointerPte))
{
/* Map PTE */
MM::Paging::SetPte(TemplatePte, MM::Pfn::AllocateBootstrapPages(1), 0);
MM::Paging::WritePte(PointerPte, *TemplatePte);
/* Clear the page table */
RTL::Memory::ZeroMemory(MM::Paging::GetPteVirtualAddress(PointerPte), MM_PAGE_SIZE);
}
/* Get next table entry */
PointerPte = MM::Paging::GetNextPte(PointerPte);
}
}
/**
* Releases a block of system PTEs into a specified pool.
*
* @param StartingPte
* A pointer to the first PTE to release.
*
* @param NumberOfPtes
* The number of contiguous PTEs to release.
*
* @param SystemPtePoolType
* Specifies the system PTE pool to release into.
*
* @return This routine does not return any value.
*
* @since XT 1.0
*/
XTAPI
VOID
MM::Pte::ReleaseSystemPtes(IN PMMPTE StartingPte,
IN PFN_COUNT NumberOfPtes,
IN MMSYSTEM_PTE_POOL_TYPE SystemPtePoolType)
{
PMMPTE NextPte, PreviousPte, ReleasedPte;
ULONG ClusterSize;
/* Clear the PTEs before releasing them */
RtlZeroMemory(StartingPte, NumberOfPtes * MM::Paging::GetPteSize());
/* Raise runlevel and acquire lock to protect the PTE pool */
KE::RaiseRunLevel RunLevel(DISPATCH_LEVEL);
KE::QueuedSpinLockGuard SpinLock(SystemSpaceLock);
/* Increment the total number of available PTEs in this pool */
TotalSystemFreePtes[SystemPtePoolType] += NumberOfPtes;
/* Start at the head of the free list for this pool */
PreviousPte = &FirstSystemFreePte[SystemPtePoolType];
ReleasedPte = NULLPTR;
/* Iterate through the free list to find adjacent blocks */
while(MM::Paging::GetNextEntry(PreviousPte) != MAXULONG)
{
/* Get the next free cluster to check its size */
NextPte = MM::Paging::AdvancePte(SystemPteBase, MM::Paging::GetNextEntry(PreviousPte));
ClusterSize = GetClusterSize(NextPte);
/* Check if the released block is adjacent to the current free block */
if((MM::Paging::AdvancePte(NextPte, ClusterSize) == StartingPte) ||
(MM::Paging::AdvancePte(StartingPte, NumberOfPtes) == NextPte))
{
/* Merge the blocks by adding their sizes */
NumberOfPtes += ClusterSize;
/* Check if the current free block is before the released block */
if(NextPte < StartingPte)
{
/* The new merged block starts at the current free block's address */
StartingPte = NextPte;
}
/* Unlink the current free block as it is being merged */
MM::Paging::SetNextEntry(PreviousPte, MM::Paging::GetNextEntry(NextPte));
/* Check if the block represents more than one PTE */
if(!MM::Paging::GetOneEntry(NextPte))
{
/* Clear block header and move to the size PTE */
MM::Paging::ClearPte(NextPte);
NextPte = MM::Paging::GetNextPte(NextPte);
}
/* Clear the merged block */
MM::Paging::ClearPte(NextPte);
/* Reset insertion point since block size/address changed due to merge */
ReleasedPte = NULLPTR;
}
else
{
/* Select the first free block large enough as insertion point */
if((ReleasedPte == NULLPTR) && (NumberOfPtes <= ClusterSize))
{
/* Mark this as the insertion point */
ReleasedPte = PreviousPte;
}
/* Advance to the next free block */
PreviousPte = NextPte;
}
}
/* Check if there is only one PTE to release */
if(NumberOfPtes == 1)
{
/* Mark it as a single-PTE block */
MM::Paging::SetOneEntry(StartingPte, 1);
}
else
{
/* Otherwise, mark it as a multi-PTE block */
MM::Paging::SetOneEntry(StartingPte, 0);
/* The next PTE stores the size of the block */
NextPte = MM::Paging::GetNextPte(StartingPte);
MM::Paging::SetNextEntry(NextPte, NumberOfPtes);
}
/* Check if no suitable insertion point was found */
if(ReleasedPte == NULLPTR)
{
/* Insert at the end of the list */
ReleasedPte = PreviousPte;
}
/* Link the new block into the free list */
MM::Paging::SetNextEntry(StartingPte, MM::Paging::GetNextEntry(ReleasedPte));
MM::Paging::SetNextEntry(ReleasedPte, MM::Paging::GetPteDistance(StartingPte, SystemPteBase));
}
/**
* Reserves a contiguous block of system PTEs from a specified pool.
*
* @param NumberOfPtes
* The number of contiguous PTEs to reserve.
*
* @param SystemPtePoolType
* Specifies the system PTE pool from which to allocate.
*
* @return This routine returns a pointer to the beginning of the reserved block,
* or NULLPTR if not enough contiguous PTEs are available.
*
* @since XT 1.0
*/
XTAPI
PMMPTE
MM::Pte::ReserveSystemPtes(IN PFN_COUNT NumberOfPtes,
IN MMSYSTEM_PTE_POOL_TYPE SystemPtePoolType)
{
PMMPTE NextPte, PreviousPte, ReservedPte;
ULONG ClusterSize;
/* Raise runlevel and acquire lock to protect the PTE pool */
KE::RaiseRunLevel RunLevel(DISPATCH_LEVEL);
KE::QueuedSpinLockGuard SpinLock(SystemSpaceLock);
/* Find a free PTE cluster large enough for the request */
if(!FindFreeCluster(NumberOfPtes, SystemPtePoolType, &NextPte, &PreviousPte))
{
/* Out of system PTEs for this pool, return NULLPTR */
return NULLPTR;
}
/* We have the cluster, now get its size for the allocation logic below */
ClusterSize = GetClusterSize(NextPte);
/* Unlink the found cluster from the free list for processing */
MM::Paging::SetNextEntry(PreviousPte, MM::Paging::GetNextEntry(NextPte));
/* Handle the allocation based on whether the cluster size is an exact match */
if(ClusterSize == NumberOfPtes)
{
/* Exact match, allocate the entire cluster */
ReservedPte = NextPte;
/* Handle metadata cleanup for a single-PTE cluster */
if(MM::Paging::GetOneEntry(NextPte))
{
/* Clear the PTE that held the list metadata */
MM::Paging::ClearPte(NextPte);
NextPte = MM::Paging::GetNextPte(NextPte);
}
/* Clear the PTE that held the cluster size */
MM::Paging::ClearPte(NextPte);
}
else
{
/* Cluster is larger than needed, so it will be split */
ClusterSize -= NumberOfPtes;
ReservedPte = MM::Paging::AdvancePte(NextPte, ClusterSize);
/* Update metadata for the new, smaller leftover cluster */
if(ClusterSize == 1)
{
/* The leftover fragment is a single PTE */
MM::Paging::SetOneEntry(NextPte, 1);
MM::Paging::ClearPte(ReservedPte);
}
else
{
/* The leftover fragment is larger than one PTE */
NextPte = MM::Paging::GetNextPte(NextPte);
MM::Paging::SetNextEntry(NextPte, ClusterSize);
}
/* Find the correct sorted position to re-insert the leftover fragment */
PreviousPte = &FirstSystemFreePte[SystemPtePoolType];
while(MM::Paging::GetNextEntry(PreviousPte) != MAXULONG)
{
/* Get the next free cluster to check its size */
NextPte = MM::Paging::AdvancePte(SystemPteBase, MM::Paging::GetNextEntry(PreviousPte));
/* Check if the leftover fragment should be inserted here */
if(ClusterSize <= GetClusterSize(NextPte))
{
/* Found the correct sorted position */
break;
}
/* Advance to the next entry */
PreviousPte = NextPte;
}
/* Get a pointer to the start of the leftover fragment */
NextPte = MM::Paging::AdvancePte(ReservedPte, -ClusterSize);
/* Insert the leftover fragment back into the free list at its sorted position */
MM::Paging::SetNextEntry(NextPte, MM::Paging::GetNextEntry(PreviousPte));
MM::Paging::SetNextEntry(PreviousPte, MM::Paging::GetPteDistance(NextPte, SystemPteBase));
}
/* Decrement the total number of available PTEs in this pool */
TotalSystemFreePtes[SystemPtePoolType] -= NumberOfPtes;
/* Flush the TLB to ensure address translation consistency */
AR::CpuFunc::FlushTlb();
/* Return a pointer to the start of the reserved PTE block */
return ReservedPte;
}